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library ieee;
use ieee. std_logic_1164.all;
entity lavadora is
lleno : in std_logic;
tapa : in std_logic;
clock : in std_logic;
);
end lavadora;
component maquina is
X : in std_logic;
clear : in std_logic;
);
end component;
component contadorvar is
cero : in std_logic;
);
end component;
component FFD is
Q: out std_logic);
end component;
component num2let is
port
end component;
component relojcontador is
port(clk50mhz: IN STD_LOGIC;
end component;
component relojbarrido is
port(clk50mhz: IN STD_LOGIC;
end component;
component barrido is
port
clk: IN STD_LOGIC;
end component;
component bcdto7 is
port (
);
end component;
signal
finconteo,clear,cero,relojb,relojcon,relojmdeb,xmaquinadeb,memoria,buzzer,aux,aux2,xmaquina,
relojM,relojC,reiniciar : std_logic;
begin
maquinain:maquina
port map(
clock=>relojM,
X=>xmaquina,
clear=>reiniciar,
estado=>estado,
anterior=>anterior
);
contador:contadorvar
port map(
clock=>relojC,
cero=>relojM,
finconteo=>finconteo,
estado=>estado,
contu=>contu,
contd=>contd
);
reinicio:FFD
port map(
CLOCK=>tapa,
pre=>'1',
clea=>'1',
q=>aux2
);
RelojCont: relojcontador
port map(
clk50mhz=>clock,
clkOUT=>relojcon
);
RelojBarr: relojbarrido
port map(
clk50mhz=>clock,
clkOUT=>relojb
);
Barrid: barrido
port map(
numero7seg1=>contu7,
numero7seg2=>contd7,
numero7seg3=>velocidad,
numero7seg4=>direccion,
clk=>relojb,
segmentos=>seg,
displays=>disp
);
BCDto1: bcdto7
port map(
numbcd=>contu,
segmentos=>contu7
);
BCDto2: bcdto7
port map(
numbcd=>contd,
segmentos=>contd7
);
velo: num2let
port map(
num=>vel,
segmentos=>velocidad
);
dire: num2let
port map(
num=>dir,
segmentos=>direccion
);
reiniciar<=aux2 or (not(encendido));
--aux<='0';
process(relojcon)
begin
vel<="010";
elsif(estado="101") then
vel<="001";
else
vel<="111";
end if;
if(estado="010" and contu(1)='0') then
dir<="011";
dir<="000";
else
dir<="111";
end if;
end if;
end process;
estadol<=estado;
relc<=relojc;
relm<=relojm;
ante<=anterior;
x<=xmaquina;
veloci<=vel;
direc<=dir;
tiempou<=contu;
tiempod<=contd;
end;
Componente FFD
library ieee;
entity FFD is
PORT( D,CLOCK,pre,clea: in std_logic;
Q: out std_logic);
end FFD;
architecture behavioral of FFD is
begin
process(CLOCK)
begin
end process;
end behavioral;
Componente debouncer_top
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity debouncer_top is
port (
clk : in std_logic;
btn_in : in std_logic;
btn_out : out std_logic);
end debouncer_top;
begin
process(clk)
begin
if (clk'event and clk='1') then
if (btn_prev xor btn_in) = '1' then
counter <= (others => '0');
btn_prev <= btn_in;
elsif (counter(CNT_SIZE) = '0') then
counter <= counter + 1;
else
btn_out <= btn_prev;
end if;
end if;
end process;
end beh;
Componente ContadorVar
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity contadorvar is
Port ( clock : in STD_LOGIC;
cero : in std_logic;
finconteo : out std_logic;
estado : in STD_LOGIC_vector (2 downto 0);
contu : out STD_LOGIC_vector(3 downto 0);
contd : out std_logic_vector(3 downto 0)
);
end contadorvar;
component JK is
Port ( j : in STD_LOGIC;
k : in STD_LOGIC;
clock : in STD_LOGIC;
clear : in std_logic;
q : out STD_LOGIC;
noq : out STD_LOGIC
);
end component;
component Bin5toBCD is
PORT(
bin: in STD_LOGIC_VECTOR(4 downto 0);
bcd_u: out STD_LOGIC_VECTOR(3 downto 0);
bcd_d: out STD_LOGIC_VECTOR(3 downto 0);
bcd_c: out STD_LOGIC_VECTOR(3 downto 0));
end component;
signal c : std_logic_vector(4 downto 0):="00000";
signal aux,aux2 :std_logic:='0';
begin
C1:JK
port map(
J=>'1',
K=>'1',
clock=>not(clock),
clear=>cero,
q=>c(0)
);
C2:JK
port map(
J=>'1',
K=>'1',
clock=>not(c(0)),
clear=>cero,
q=>c(1)
);
C3:JK
port map(
J=>'1',
K=>'1',
clock=>not(c(1)),
clear=>cero,
q=>c(2)
);
C4:JK
port map(
J=>'1',
K=>'1',
clock=>not(c(2)),
clear=>cero,
q=>c(3)
);
C5:JK
port map(
J=>'1',
K=>'1',
clock=>not(c(3)),
clear=>cero,
q=>c(4)
);
BCD: Bin5toBCD
port map(
bin=>c,
bcd_u=>contu,
bcd_d=>contd
);
process(clock)
begin
finconteo<=aux2;
end;
Componente Bin5toBCD
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Bin5toBCD is
PORT(
bin: in STD_LOGIC_VECTOR(4 downto 0);
bcd_u: out STD_LOGIC_VECTOR(3 downto 0);
bcd_d: out STD_LOGIC_VECTOR(3 downto 0);
bcd_c: out STD_LOGIC_VECTOR(3 downto 0));
end Bin5toBCD;
Componente bcdto7
library IEEE;
use ieee.std_logic_1164.all;
entity bcdto7 is
port
(
numBCD: in std_logic_vector (3 downto 0);
segmentos: out std_logic_vector(7 downto 0));
end bcdto7;
begin
with numBCD select
Componente Barrido
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity barrido is
port
(
numero7seg1: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
numero7seg2: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
numero7seg3: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
numero7seg4: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clk: IN STD_LOGIC;
segmentos: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
displays: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
end barrido;
BarrDispl:process(clk)
begin
if falling_edge(clk) then
if cont = 1 then
segmentos <= numero7seg1; -- Saco por Segm el numero1
displays <= "1110"; -- Prendo displays de Derecha a Izquierda.
-- Display Activo =
0L.
cont <= cont + 1; -- Actualizo Contador cnt
else
else
null;
end if;
end process;
end behaviour;
Componente RelojContador
library IEEE;
use IEEE.STD_LOGIC_1164.all;
begin
gen_clock: process(clk50mhz, clk_state, count)
begin
if clk50mhz'event and clk50mhz='1' then --if clk50mhz'event and clk50mhz='1'
then
if count < max_count then
count <= count+1;
else
clk_state <= not clk_state;
count <= 0;
end if;
end if;
end process;
end behaviour;
Componente Relojbarrido
library IEEE;
use IEEE.STD_LOGIC_1164.all;
begin
gen_clock: process(clk50mhz, clk_state, count)
begin
if clk50mhz'event and clk50mhz='1' then --if clk50mhz'event and clk50mhz='1'
then
if count < max_count then
count <= count+1;
else
clk_state <= not clk_state;
count <= 0;
end if;
end if;
end process;
end behaviour;
Componente JK
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity JK is
Port ( j : in STD_LOGIC;
k : in STD_LOGIC;
clock : in STD_LOGIC;
clear : in std_logic;
q : out STD_LOGIC;
noq : out STD_LOGIC
);
end JK;
architecture proceso of JK is
signal jk : std_logic_vector(1 downto 0) := "00";
signal qsig : std_logic :='0';
begin
jk <= j & k;
process(clear,clock)
begin
if (clear='1')then
qsig <='0';
elsif (clock'event and clock = '1')then
case (jk) is
when "00" => qsig <= qsig;
when "01" => qsig <= '0';
when "10" => qsig <= '1';
when others => qsig <= not qsig;
end case;
end if;
end process;
q <= qsig;
noq<= not qsig;
end proceso;