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B. van Liempd,
C. Lavín, S. Malotaux, J.R. Long D.J. van den Broek,
B. Debaillie,
C. Palacios Delft University of E.A.M. Klumperink
J. Craninckx University of Twente
TTI Technology
imec Santander, Spain Delft, The Netherlands Twente, The Netherlands
Leuven, Belgium
Tx & Rx channel
Rx channel
Tx channel
mass-market applications and next-generation standards, e.g.
Time
Time
Time
Rx channel
IEEE802.11 and 5G. Measured prototype implementations of an Tx
spacing
Guard
electrical balance duplexer and a dual-polarized antenna both Interval
Rx
achieve >50dB self-interference suppression at RF, operating in
the ISM band at 2.45GHz. Tx
Frequency Frequency Frequency
Keywords-Full-Duplex; RF, Self-Interference Cancellation; Time-division duplex Frequency-division duplex
Full-duplex
(half-duplex) (half-duplex)
Dual-Polarization Antenna; Electrical Balance Duplexer, CMOS (a) (b) (c)
I. INTRODUCTION Figure 1. Half-duplex TDD (a) and FDD (b) compared to FD (c).
Full-duplex (FD) communication has the ability to increase RF SIC LO Baseband processor
data throughput and network efficiency and thus enable (this work) Tx .
PA MOD
sustainable network growth and the introduction of mobile
.
ABB Channel
estimation
standards such as next-generation IEEE 802.11 and 5G [1]. In Φ 50dB Δt 2nd stage Δt >100dB
Multi-path
contrast with time- and frequency-division duplexing RF SIC SIC reflection Total SIC
- - cancellation
(TDD, FDD), the transmitter (Tx) and receiver (Rx) operate at LNA
+ Rx . + DEMOD
the same time and channel in an FD communication link (Fig. 1). Analog
ABB .
Digital SIC
SIC
Hence, self-interference (SI) originating from the Tx degrades
the Rx signal-to-noise ratio (SNR) much more compared to Figure 2. Example of RF, analog and digital SIC applied to a FD transceiver.
conventional (TDD or FDD) links. Large SI at RF can even
cause compression at the first receiver input stage, namely the In this paper, two single-antenna RF SIC techniques are
low noise amplifier (LNA), thereby crippling the whole proposed. First, an electrical balance duplexer provides >50dB
communication link between devices. SIC across >6MHz, measured with a real planar inverted-F
Self-interference cancellation (SIC) is crucial for FD and a antenna (PIFA) at 2.45GHz. Second, a dual-feed antenna using
very high total SIC >100dB is required, likely requiring dual-polarization achieves >50dB of measured isolation by itself
multi-stage SIC [2]. Fig. 2 shows an example architecture with and >65dB across >10MHz when a tuned RF SIC loop is
multiple SIC stages across the Rx chain, i.e. RF SIC before the operated in conjunction with the antenna element.
LNA, post-mixer analog SIC at baseband frequencies and digital These demonstrated results obtain sufficient SIC in an
SIC. Sufficient RF SIC is required in order to avoid problematic commercially attractive small form-factor, allowing FD to
nonlinearity in the Rx chain such as intermodulation distortion become a mainstream mode of operation for devices, such as
and even clipping. Subsequent cancellation stages must ensure tablets, smartphones, and other end-user equipment.
sufficient signal-to-interference ratio (SIR) to establish a robust
device-to-device link across operating conditions, including II. PROPOSED RF SIC TECHNIQUES
cancellation of (delayed) reflected SI [3].
A. RF SIC with an Electrical Balance Duplexer
In recent literature, several designs have demonstrated
several SIC techniques [3],[4]. However, so far, RF SIC In conventional single-antenna devices, surface-acoustic
implementations have not targeted small form-factors. Most wave (SAW)-based duplexers provide the required isolation
solutions [4],[6] use at least two antennas, inappropriate for between the transmitter and the receiver for standards operating
small form-factor devices due to their required physical spacing. in FDD mode. Furthermore, they provide out-of-band filtering
Moreover, using multiple antennas introduces nulls in the to resolve blocker issues in the Rx path. However, such
antenna beam pattern, degrading coverage. In contrast, single duplexers are based on fixed-frequency filters, which only allow
antenna solutions allow integration in compact form-factor antenna sharing when the Tx and Rx operate concurrently on
devices while ensuring good far-field coverage. different frequencies.
The research leading to these results has received funding from the
European Union Seventh Framework Programme (FP7/2007-2013) under
grant agreement n° 316369 – project DUPLO: www.fp7-duplo.eu
VDD
ZANT ZANT
Antenna M2
CDEC
PA LNA PA LNA M1
Receiver
PA C2
Balance Balance
C1
network network Capacitors: LNA
ZBAL ZBAL C1 = 4.35 pF
C2 = 0.50 fF
(a) (b) Hybrid transformer
Capacitors: Capacitors:
133.4 fF 11.53 fF
VDD VDD
(to hybrid transformer)
ZBAL
Analog
VCTRL,R
tunable @ 2.45GHz
(off-chip) R 10 R 100Ω NMOS: NMOS:
Resistors: Resistors:
0.1 C 7pF L = 180nm 74.5 KΩ L = 180nm 21.26 KΩ
W = 5 μm W = 750nm
High-speed #Fingers = 5 #Fingers = 4
DAC Digital
tunable
Network X 15
FPGA C (13b)
ZANT
on
control Chip
CMOS die @ 2.45GHz( )
Figure 4. Proposed balance network topology and tuning circuitry (left) and
measured impedance variations of ZANT (PIFA) with ZBAL tuning range (right). NMOS: Resistors: PMOS:
L = 180nm 200Ω L = 360nm
W = 5 μm
For FD concurrent Tx and Rx operation at the same #Fingers = 10 VDD
W = 360nm
#Fingers = 1
frequency is required. Recently, the use of hybrid transformers Balance network
to achieve signal cancellation based on electrical balance (EB)
has been proposed to achieve tunable duplexer filters for FDD Figure 5. Schematic of the FD electrical balance duplexer circuit.
[7]-[9]. In this paper, we apply this technique in the context of
full-duplex and show how it provides RF self-interference The on-chip impedance tuning range must cover the
cancellation for compact radio devices. frequency-dependent impedance of a real antenna, which varies
Fig. 3 shows the conceptual operation of an EB duplexer, across environmental conditions. The non-ideal antenna
comprising a hybrid transformer and so-called balance network, interconnect causes an additional impedance shift that also must
which is essentially a tunable dummy load impedance. Ideally, be taken into account during the design of ZBAL. For the
the PA signal splits up exactly between the antenna and the measured PIFA impedance (Fig. 4), a parallel resistor and
balance network, so that no differential voltage excitation occurs capacitor are capable of mimicking the required impedance
and the hybrid transformer essentially subtracts the voltage range that covers the variations of ZANT including the antenna
across these impedances. The limit to the SIC provided by this interconnect.
electrical balance condition is limited by the accuracy with Fig. 5 shows the circuit schematic of the implemented
which the balance network can mimic ZANT [7]. By tuning the duplexer. The balance network shows three binary tunable
resistance and reactance of ZBAL independently with high capacitor banks (coarse, fine and superfine), the latter of which
precision, >50dB of SIC can be achieved across the channel is using PMOS transistors as tuned capacitors to achieve the
bandwidth (BW). In virtue of this purely passive cancellation required minimum capacitance-step. The resistor is
process, any noise and nonlinearity products generated in the implemented using an NMOS transistor and a parallel
transmitter are also cancelled by this subtraction. resistance, achieving an analog tuning range between 10 and
The principle of electrical balance is applicable to both FDD 100Ω.
and FD: the Tx-to-ZANT path as well as the ZANT-to-Rx path Note that the Tx power splits across ZANT and ZBAL, hence
have a wideband transformer response, while Tx-to-Rx a >3dB insertion loss is expected even when the transformer
cancellation is required at both the Tx and Rx frequencies does not incur additional loss. Compared to the current SAW
simultaneously (FDD) [9] or instead at a single frequency only based solutions for FDD, which incur ~2.5dB Tx path insertion
(FD), a grace of FD operation. loss, the 0.5dB penalty is rather small to enable small
form-factor FD.
Transmitted Signal
3μm M6:2μm
M5 Received Signal
M4
M1+2+3
GND ANT
Remaining
PA +
200μm - RX Tx Self-Interference
GND BAL
PA Tx suppressed
LNA
through polarization
10μm
Variable Variable
Coupler Amplitude Combiner Coupler
Phase
From PA To LNA
ps d[mm] 10.98
l1 l1[mm] 90.00
ds
a1[mm] 32.59
hs b1[mm] 30.45
ds [mm] 20.61
ps [mm] 12.93
ls [mm] 4.74
hs [mm] 2.39
PORT 2 ws [mm] 3.01
Network-on-Chip Balance
and control bus network
(a) (b)
Figure 10. (a) Duplexer chip and (b) dual-feed, dual-polarization antenna.
(a) (b)
III. MEASUREMENT RESULTS
A. EB Duplexer RF SIC Measurement Results Min. R
2
Fig. 10(a) shows a photograph of the 0.4mm EB-duplexer Max. R
chip fabricated in a bulk 0.18µm CMOS process. An off-chip
DAC is used to set VCTRL for the on-chip resistor tuning. The Max. R
PIFA used in conjunction with the prototype (not shown)
operates at 2.45GHz, and measures 26x5mm.
Min. R
Fig. 11(a) shows the measured ZBAL range for which >60dB
Tx-to-Rx isolation is observed when sweeping the impedance
at the antenna port using a Maury MT982EU impedance tuner. (c)
The worst-case impedance variations of the PIFA due to
environmental condition changes are covered by the tuning Figure 11. FD duplexer measurements: (a) ZBAL tuning range at 2.45GHz,
(b) SIC at 2.45GHz with PIFA and (c) Rx-path gain and NF versus frequency.
range of ZBAL at 2.45GHz, both in simulation and measurement.
Fig. 11(b) shows the measured and simulated isolation curves 0
at 2.45GHz when the PIFA is connected to the duplexer, after
Return loss [dB]