THE HONG KONG

POLYTECHNIC UNIVERSITY_________________________________________________ ___

Department of Electrical Engineering

CHAPTER 6 POWER INVERTERS

6.1. Introduction

Inverters (or called power inverters or DC/AC inverters) are electronic circuits converting DC power to
AC power with desired output voltage, output current and/or output frequency. The output is in the form
of AC and can be single-phase and multi-phase.

Fig. 6.1 shows the connections of a basic inverter system with DC and AC voltage source, respectively.
In the inverter system with DC voltage source as shown in Fig. 6.1(a), the input filter is for reducing
harmonics of input current. In the inverter system with AC voltage source as shown in Fig. 6.1(b), the
rectifier is for rectifying the AC voltage to be DC voltage. The input filter is for filtering the AC
components of the voltage from the rectifier. For high power applications, L-C filter may be applied on
the inverter system on the input side of the rectifier to reduce harmonics of the input current. The output
filters in both inverter systems are for filtering the harmonics of the output voltage of the inverter, vo, to
provide sinusoidal voltage (fundamental of the output voltage of the inverter).

Inverter
Input DC Output

Load
+

Vin Filter Vdc vo Filter vo(fund)

Link

(a) Inverter system with DC voltage source

Rectifier Inverter
Input DC Output Load
+

Vin Filter Vdc vo Filter vo(fund)

Link

(a) Inverter system with AC voltage source

Fig. 6.1. Connection of basic inverter systems

Switching devices of most inverters are IGBTs. MOSFETs are used for low power level inverters.
IGBTs and MOSFETs are commonly used in inverters because of their high speed and easily controlled
features. Forced-commutated thyristors are sometimes used in inverters when the power level or voltage
level is very high, especially in current source inverters (CSIs). Closed-loop control can be implemented
for regulating and controlling the output voltage and current of inverters.

6.2. Types of Inverters

6.2.1. Voltage Source Inverters and Current Source Inverters

Inverters are classified as voltage source inverters (VSIs) and current source inverters (CSIs). A VSI
uses control parameters to regulate its output voltage whereas a CSI uses control parameters to regulate
its output current. Power circuits of VSI and CSI are basically the same. Fig. 6.2 shows circuit
diagrams of 3 of the most common inverters including a half-bridge single-phase inverter, a full-bridge
single-phase inverter and a three-phase inverter.

The main difference of VSI and CSI is that there is a current control loop in a CSI for controlling its
output current while VSI does not have current control loop. VSIs are commonly used in low to high
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POLYTECHNIC UNIVERSITY_________________________________________________ ___
Department of Electrical Engineering

power applications. Some examples of VSIs are variable speed drives (VSDs) for induction machines,
electric drives such as brushless DC (BLDC) machines, uninterruptible power supplies (UPSs),
electronic ballasts for florescent lamps and high intensive discharge (HID) lamps, induction heaters, and
other AC power supplies. CSIs are suitable for very high power and high voltage AC motor drive
applications. CSIs can be also applied in motion control systems.

T1 T1 T3
+

Vin D1 D1 D3
2 C1
A

Load

Load
A

+
Vin N vo Vin C N vo

Vin T2 D2 T4 D4 T2 D2
+

2 C2

(a) Half-bridge single-phase inverter (b) Full-bridge single-phase inverter

Vin T1 T3 T5
+

D1 D3 D5
2 C1
A
Vin B
C
N
Vin T2 T4 T6
+

D2 D4 D6
2 C2

(c) Three-phase full-bridge inverter

Fig. 6.2. Circuit diagrams of power inverters

6.2.2. Matrix Converters

Matrix converters are to convert AC voltage to AC

voltage directly without AC/DC rectification. Fig. 6.3
shows a circuit diagram of a polyphase matrix converter.
Three-phase matrix converters are the most popular in
many applications.

The advantage of this type of inverter is that there is no

intermediate stage needed. The AC is directly converted
into another AC voltage. The disadvantage of matrix
converters is that the output voltage of a converter is
restricted by the amplitude of its input voltage. Also,
complicated and careful switching pattern is needed to Load
avoid short-circuited between its input phases. Fig. 6.3. Circuit diagram of a matrix converter

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POLYTECHNIC UNIVERSITY_________________________________________________ ___
Department of Electrical Engineering

6.3. Principle of Operation of Inverters

Outputs of power inverters can be single-phase and multi-phase. The most common topologies of
inverters are single-phase half-bridge inverter, single-phase full-bridge inverter and three-phase full-
bridge inverter. The principle of operation of these three types of inverters are described and explained
in the following sections. The operation of all of these inverters is acting as voltage source inverters
(VSI).

6.3.1. Single-phase Half-bridge Inverters

Single-phase half-bridge inverters are suitable for low power applications. Fig. 6.2 (a) shows the circuit
diagram of a single-phase half-bridge inverter. This inverter consists of two switching devices, T1 and
T2 and two diodes, D1 and D2. In this case, IGBTs are the switching devices. These two IGBTs and
these two diodes build a one-leg or called a half-bridge. D1 and D2 are called anti-parallel diodes of T1
and T2, respectively. If the switching devices are MOSFETs, these diodes are built internally. The input
capacitors, C1 and C2, share the input equally. Their voltage is the same and equal to Vin/2. The node
between these two capacitors is the neutral point of the output of the inverter, N, and the node between
two IGBTs is the live point of the output of the inverter, A.

Operating this inverter, T1 and T2, are switched on and off alternatively. Assuming all components are
ideal, the duty ratio of the gate signal of each IGBT is 0.5. Deadtime between each switching is applied
to avoid short circuit in practise.

6.3.1.1. Single-phase Half-bridge Inverters with vgs1

Purely Resistive Load 0
vgs2 t
Fig. 6.4 shows the idealised waveforms of a single-
phase half-bridge inverter with a purely resistive vT1
0 t
load. Considering N is the reference point, the Vin
voltage of A is Vin/2 when T1 is on and T2 is off, and vT2
0 t
is -Vin/2 when T1 is off and T2 is on. The output Vin
voltage, vo, is a pure square AC voltage with Vin/2 0 t
vo
peak voltage. For an ideal inverter with a resistive Vin/2
load, the anti-parallel diodes, D1 and D2, are reverse 0 t
biased.
t0 t1 t2 -Vin/2
6.3.1.2. Single-phase Half-bridge Inverters with Fig. 6.4. Idealised waveforms of a single-phase
Resistive and Inductive Load half-bridge inverter with a purely resistive load
Fig. 6.5 and Fig. 6.6 show the circuit diagram and
the idealised waveforms of a single-phase half- iT1 iD1
bridge inverter with a resistive load and an inductive io
Vin T1
+

load. The output current, io, is lagging comparing D1

2 C1
with the output voltage, vo. Because of the inductive L
A
characteristic of the load, D1 and D2 sometimes Vin N vo
conduct and power transfers from the load to Vin
through the diodes. There is a negative part in the Vin T2 D2 R
+

input current in one switching period. Operation of 2 C2

the inverter is classified as four states. Equivalent iT2 iD2
circuits of these four states of operation are shown in
Fig. 6.7. The output voltage is the same as that of Fig. 6.5. Circuit diagram of a single-phase half-
the inverter with a purely resistive load. bridge inverter with a resistive and inductive load

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vgs1
iT1 iD1 iT1
0 io io
vgs2 t Vin T1 Vin T1
D1
2 2
L L
0 t A A
iT1 vo vo
N N
0 t Vin R Vin R
iT2
2 2
0 t
iD1
0 (a) State 1 (b) State 2
iD2 t
io io
0 t Vin Vin
vo
Vin/2 2 2
L L
0 t A A
N vo N vo
io -Vin/2
Vin T2 D2 R Vin T2 R
0 t 2 2
iD2 iT2
iin
0 t (c) State 3 (d) State 4
Fig. 6.7. Equivalent circuits of state of operation of a single-phase
t0 t1 t2 t3 t4 half-bridge inverter with a resistive and inductive load
Fig. 6.6. Idealised waveforms
of a single-phase half-bridge inverter with
a resistive and inductive load

6.3.2. Single-phase Full-bridge Inverters

Single-phase full-bridge inverters are suitable for the applications with higher power level than that of
single-phase half-bridge inverters. Fig. 6.2 (b) shows the circuit diagram of this type of inverter. This
inverter consists of four switching devices, T1, T2, T3 and T4, and four anti-parallel diodes, D1, D2, D3
and D4. In this case, IGBTs are the switching devices. There are 2 legs in an inverter. T1, D1, T4 and D4
form one leg and T2, D2, T3 and D3 form another leg. Comparing with single-phase half-bridge inverter,
two large input capacitors in the single-phase full-bridge inverter are not necessary.

Operating this inverter, the IGBTs, T1 and T2, are on at

the same time, and T3 and T4 are on at the same time.
Also, T1 and T4 are switched on and off alternatively, vgs1,vgs2
and T2 and T3 are switched on and off alternatively. 0 t
Assuming all components are ideal, the duty ratios of vgs3,vgs4
the gate signals of all IGBTs are 0.5. In practise, 0 t
deadtime is applied between the switching of T1 and vT1,vT2
Vin
T4, and T2 and T3. 0 t
vT3,vT4
Vin
6.3.2.1. Single-phase Full-bridge Inverters with
0 t
Purely Resistive Load vo
Vin
Fig. 6.8 shows the idealised waveforms of a single- 0 t
phase full-bridge inverter. When T1 and T2 are on, the
t0 t1 t2 -Vin
output voltage, vo, is equal to Vin. When T3 and T4 are
on, vo is equal to -Vin. For the load is purely resistive, Fig. 6.8. Idealised waveforms of a single-phase
D1, D2, D3 and D4 are all reverse biased. half-bridge inverter with a purely resistive load

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6.3.2.2. Single-phase Full-bridge Inverters with Resistive and Inductive Load

Fig. 6.9 and Fig. 6.10 show the circuit diagram and the idealised waveforms of a single-phase full-bridge
inverter with a resistive and inductive load. The output current in this case is lagging comparing to the
output voltage. The anti-parallel diodes sometimes conduct and power transfers from the load to Vin
through them. There is a negative part in the input current in one switching period. The operation is
classified to four states. Equivalent circuits of each state of operation are shown in Fig. 6.11. The
output voltage is the same as that of the inverter with a purely resistive load.

iT1 iD1
io
T1 D1
L
A
Vin N vo
iT1 iD1 iT3 iD3
io T2 D2 R
T1 D1 T3 D3
iT2 iD2
L
A
+

Vin C N vo (a) State 1

T4 T2 R iT1
D4 D2 io
T1
iT4 iD4 iT2 iD2 L
A
Vin N vo
Fig. 6.9. Circuit diagram of a single-phase full-bridge
inverter with a resistive and inductive load T2 R

iT2
vgs1,vgs2
(b) State 2
0 t
vgs3,vgs4
iT3 iD3
0 t io
iT1,iT2 T3 D3
0 t L
iT3,iT4 A
Vin N vo
0 t T4 R
iD1,iD2 D4
0 t iT4 iD4
iD3,iD4
0 t (c) State 3
vo
Vin
iT3
0 t io
T3
io -Vin
L
0 t A
Vin N vo
iin T4 R
0 t
iT4
t0 t1 t2 t3 t4 (d) State 4
Fig. 6.10. Idealised waveforms Fig. 6.11. Equivalent circuits of operation of
of a single-phase full-bridge inverter a single-phase full-bridge inverter
with a resistive and inductive load with a resistive and inductive load

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6.3.3. Three-phase Full-bridge Inverters

iT1 iD1 iT3 iD3 iT5 iD5

iAB

+
Vin T1 T3 T5
C1 D1 D3 D5
2 vAB vCA
A RA RB
Vin 0 B C
RC iCA
Vin T4 D4 T6 D6 T2 D2
+

iBC
2 C2 vBC
iT4 iD4 iT6 iD6 iT2 iD2

Fig. 6.12. Circuit diagram of a three-phase full-bridge converter

with a delta connected purely resistive load

Fig. 6.12 shows the circuit diagram of a three-phase full-

bridge converter with a delta connected purely resistive
load. A three-phase full-bridge inverter can be considered vgs1
as a parallel connection of three single-phase half-bridge 0 t
inverters operating with 120 degrees phase difference. As vgs4
a result, there are 3 legs built with six switching devices 0 t
vgs3
and six anti-parallel diodes. This type of inverter is able 0 t
to produce three-phase line voltages and phase voltages to vgs6
the load. This converter is commonly operated with 180º 0 t
vgs5
and 120º conduction; i.e., 50% duty ratio and 33.33% duty
0 t
ratio of the gate signals, respectively. vgs2
0 t
Fig. 6.13 shows the idealised waveforms of a three-phase vA0 Vin/2
full-bridge inverter with a delta-connected resistive load 0 t
for 180º conduction. The duty ratio of the gate signals of -Vin/2
vB0
each switching devices are 50%. All the three resistors, 0 t
RA, RB, and RC, are having the same resistance, R. The
vC0
peak output line voltage of each phase of the inverter is Vin
0 t
although the peak values of vA0, vB0, and vC0 are Vin/2. The
on-state sequence is T1 & T2, T2 & T3, T3 & T4, T4 & T5, vAB Vin
T5& T6, T6 & T1 so that each leg is like a single-phase
0 t
half-bridge inverter operating with 120 degrees phase
difference. -Vin
vBC
The rms voltage of the fundamental of each line voltage is
0 t
of this inverter with 180º connection is:

6Vin vCA
VLL ,1  VAB,1  VBC,1  VCA,1  (6.1)
 0 t
The total rms output line voltage is:
t0 t1 t2 t3 t4 t5 t6
2
1 3 2 Fig. 6.13. Idealised waveforms of a three-phase
 Vin dt 
VLL 
2
Vin (6.2)
 0 3 full-bridge inverter with a delta-connected
resistive load for 180º conduction

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If a three-phase full-bridge inverter is connected to three-phase wye-connected resistive load as shown in

Fig. 6.14, and the load resistance, RA, RB, and RC, is equal to R, the output phase current of each phase is:
v AB vCA v v v  v AB v  vBC
iA    AB CA , iB  BC , iC  CA (6.3)
RA  RB RA  RC 2R 2R 2R
Hence, the phase output voltage of each phase is:
v AB  vCA v  v AB v  vBC
v AN  , vBN  BC , vCN  CA (6.4)
2 2 2

vAB Vin
iA
0 t
vAN RA -Vin
vBC
vCA vAB vBN
vCN 0
RB RC t
N
iB vCA
vBC iC
0 t
Fig. 6.14. Wye-connected resistive load
vAN Vin
Idealised output voltage waveforms of a three-
phase full-bridge inverter with a wye-connected 0 t
resistive load for 180º conduction are shown in
Fig. 6.15. This diagram shows that the harmonics -Vin
of the phase voltage of the three-phase full-bridge vBN
inverter with wye-connected load are lower than 0 t
those of the output voltage of each single-phase
half-bridge inverter although the three-phase
inverter consists of three single-phase half-bridge vCN
inverters.
0 t
The output phase voltages of the inverter with a
wye-connected three-phase resistive and inductive t0 t1 t2 t3 t4 t5 t6
load are the same as the inverter with resistive Fig. 6.16. Idealised output voltage waveforms
load. D1 to D6 sometimes conduct when because of a three-phase full-bridge inverter
of the inductive characteristic of the load. with a wye-connected load for 180º conduction

6.4. Sinusoidal Pulse-with-modulation Inverters

Many AC applications required variable AC voltage. For some applications with electric machine such
as washing machines, air-conditioners, and other industrial applications, voltage control and frequency
control are needed for better performance. The most efficient method of controlling the output voltage
of inverters is to incorporate pulse-width-modulation (PWM) technique. The most popular control is
sinusoidal pulse-width-modulation (SPWM) control. Using this method, the output voltage is not only
varied but also modulated to be SPWM so that the low order harmonics of the output voltage are
eliminated.

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SPWM for single phase inverters can be achieved by

comparing two signals, a modulation signal (or called
VˆC
reference signal) and a carrier signal as shown in Fig. 6.16. Modulation Signal Carrier Signal
Comparing these two signals, gate signals of the MOSFETs or VˆM
IGBTs of the inverter are generated. The modulation signal is
a sinusoidal wave. The frequency of the modulation signal is
equal to the fundamental frequency of the output voltage of vgs1Fig. 6.16. Modulation signal and
the inverter, called modulation frequency, fM. The carrier vgs2 carrier signal for SPWM
signal is a high frequency triangular signal. Its frequency is VS/2
v0 Voltage
called carrier frequency, fC. For good SPWM performance, fC
must be over 20 times higher than fM. vM Comparator
+
Fig. 6.17 shows an example of a circuit for comparing the vgs1
-
signals for achieving SPWM. Modulation signal and carrier vC vgs2
signal are compared by a voltage comparator. Since IGBTs in
one leg of an inverter are switched alternatively, a NOT gate Fig. 6.17. Circuit of SPWM
is used for obtaining alternate gate signals. gate signal generation

Modulation Signal Carrier Signal

VˆC
6.4.1. Sinusoidal Pulse-width-modulation
Single-phase Half-bridge Inverters VˆM
A single-phase half-bridge inverter can be
considered as two buck converters. One buck
converter is for positive output voltage and another vgs1
one is for negative output voltage. The ratio of the
peak output voltage and input voltage (similar to vgs2
Vin
voltage conversion ratio of DC/DC converters) of vo 2
one switching period of the inverter is equal to the
duty ratio of the gate signals of the IGBTs. This -Vin
means that the output voltage of the inverter can be vo(fund) 2
controlled by pulse-width-modulation (PWM). (a) Idealised Waveforms

If the output voltage of the inverter is controlled by

T1
+

fixed PWM, the low order harmonics of the output Vin D1

voltage are very high. Solving the low order 2 C1
harmonics problem, sinusoidal pulse-width- A
Load

modulation (SPWM) technique can be applied. Vin N vo

Controlling the output voltage by SPWM, the output T2
Vin D2
+

voltage contains fundamental harmonics and very 2

high order harmonics. These high order harmonics
are easily filtered. Frequency control can be
achieved by SPWM technique as well. The idealised
waveforms and a circuit diagram of a single-phase
half-bridge inverter are shown in Fig. 6.18.
C2
(b) Circuit diagram
Fig. 6.18. Idealised waveforms and circuit diagram
of an SPWM single-phase half-bridge inverter

In Fig. 6.18, vgs1 is the gate signal of T1 and vgs2 is the gate signal of T2. When the modulation signal is
higher than the carrier signal, vgs1 is high so that T1 is on. Meanwhile, vgs2 is low so that T2 is off. When
the modulation signal is lower than the carrier signal, T1 is off and and T2 is on. The output voltage of
the inverter is bipolar.

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The amplitude modulation ratio or called modulation index of the inverter is defined as:

VˆM
M (6.5)
VˆC

The frequency modulation ratio of the inverter is defined as:

f
Mf  C (6.6)
fM
The output voltage of the inverter as shown in Fig. 6.18(a) can be considered as representing a sinusoidal
voltage. The waveform of the output voltage consists of a sine wave which frequency equal to fM and
harmonics at the frequency of the orders of fC. The output voltage of the inverter can be varied by
varying the modulation index. The instantaneous output voltage of the SPWM single-phase half-bridge
inverter is:
MVin
vo  sin  M t  high order harmonics (6.7)
2
The fundamental of the instantaneous output voltage of the SPWM single-phase half-bridge inverter is:
MVin
vo,1  sin  M t (6.8)
2
where  M is the angular modulation frequency and:
 M  2f M (6.9)
As a result, the modulation index of the SPWM single-phase half-bridge inverter is:
2Vˆ
M o (6.10)
Vin
where Vˆ is the peak value of the output voltage of the inverter.
o

The high order harmonic components can be filtered by a low-pass filter. Fig. 6.19 shows the simulated
SPWM inverter output voltage of the inverter in frequency domain by PSIM. The frequency spectrum is
done by Fourier transform function, FFT. In the simulation, fC is 5kHz and fM is 50Hz so that the
frequency modulation ratio, Mf, is 100. The modulation index, M, is 0.8. The input voltage of the half-
bridge inverter, Vin, is 200V. It shows that the harmonics are with the frequency at fC and orders of fC.
The frequencies of the harmonics are high if fC is high. It implies that the orders of harmonics of the
output voltage are nMf where n is 1,2,3,…. The simulation result also shows that the amplitude of Mfth-
harmonic is nearly equal to that of the fundamental, which is quite high.

Vout
100.00
90.00
80.00
70.00
60.00
50.00
40.00
30.00
20.00
10.00
0.0
0.0 5.00 10.00 15.00 20.00
Frequency (KHz)
Fig. 6.19. Simulated output voltage of SPWM half-bridge inverter in frequency domain

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6.4.2. Sinusoidal Pulse-width-modulation Single-phase Full-bridge Inverters

There are two types of SPWM for single-phase full-bridge inverters. One SPWM method is using single
modulation signal and another method is using two modulation signals. Their principle is explained in
the followings.

6.4.2.1. SPWM Single Phase Full-bridge Inverters with Single Modulation Signal
Idealised waveforms and circuit diagram of an SPWM single-phase full-bridge inverter with single
modulation signal is shown in Fig. 6.20. This SPWM method is the same as that for single-phase half-
bridge inverters. vgs1 and vgs3 are the gate signals of T1 and T3. The gate signal of T2, vgs2, is the same as
vgs1, and the gate signal of T4 is the same as vgs3. The output voltage of the inverter is bipolar.

Modulation Signal Carrier Signal

VˆM VˆC

vgs1 T1 D1 T3 D3
vgs2
vgs3

Load
vgs4 A
Vin + C vo
vo Vin N
T4 D4 T2 D2
-Vin
vo(fund)
(a) Idealised waveforms (b) Circuit diagram
Fig. 6.20. Waveforms of an SPWM and a single-phase full-bridge inverter with single modulation signal

Modulation index of an SPWM single-phase full-bridge inverter with single modulation signal is:

VˆM Vˆo
M   (6.11)
VˆC Vin
where Vˆo is the peak value of the output voltage of the inverter.
Instantaneous output voltage of the inverter is:
vo  MVin sin M t  high order harmonics (6.12)
Fundamental of the instantaneous output voltage of the inverter is:
vo,1  MVin sin M t (6.13)

A single-phase full-bridge inverter with this SPWM method is simulated by PSIM. The simulated
output voltage in frequency domain is shown in Fig. 6.21. In this simulation, Vin is 200V, fM is 50Hz, fC
is 5kHz, so that Mf is 100. M is 0.8. It shows that the amplitude of the fundamental is 160V which is 0.8
times of VS and the frequency is 50Hz. The frequencies of the harmonics are nfC where n is 1,2,3….
The amplitude of the Mfth-harmonic is very close to that of the fundamental.

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Vout
200.00
180.00
160.00
140.00
120.00
100.00
80.00
60.00
40.00
20.00
0.0
0.0 5.00 10.00 15.00 20.00
Frequency (KHz)
Fig. 6.21. Simulated output voltage of an SPWM full-bridge inverter
with single modulation signal in frequency domain

6.4.2.1. SPWM Single Phase Full-bridge Inverters with Two Modulation Signals
Reducing harmonics of the output voltage, Modulation Signal Carrier Signal
another SPWM method can be applied by one
VˆM 1 2 VˆC
carrier signal comparing with two modulation
signals as shown in Fig. 6.22. One modulation
signal is an inverse of another modulation signal.
By comparing with the same carrier signal, vgs1 is vgs1
generated with modulation signal 1 and vgs3 is
generated by modulation signal 2. When vgs3
modulation signal 1 is higher than the carrier Vin
signal, vgs1 is high and T1 is on. Also, when
vo
modulation signal 2 is higher than the carrier
signal, vgs3 is high and T3 is on. vgs4 is an inverse vo(fund) -Vin
of vgs1 and vgs2 is an inverse of vgs3. When both Fig. 6.22. Idealised waveforms of an SPWM single-phase
T1 and T3 are on or off, vo is zero. full-bridge inverter with two modulation signals

Using this SPWM method, the output voltage has two voltage pulses in one switching period. The
frequency of vo is double of the modulation signal. There is no negative voltage pulse when the
fundamental output voltage is positive, and no positive voltage pulse when the fundamental output
voltage is negative. As a result, the output voltage of the inverter is unipolar. It can be observed that the
harmonics of the output voltage of the SPWM single-phase full-bridge inverter with two modulation
signals are lower than the one with single modulation signal. Also, nMfth-order harmonics of the output
voltage when n is 1,3,5,… are very low. The main harmonics of the output voltage is in the order of
2nMf and the main harmonics are also reduced as well. Since the frequencies of the main harmonics are
double in this case, the harmonics are more easily filtered. The size and weight of the output low-pass
filter are reduced.

Modulation index of the SPWM single-phase full-bridge inverter with two modulation signals is:

VˆM Vˆo
M   (6.14)
VˆC Vin
where Vˆo is the peak value of the output voltage of the inverter.
Instantaneous output voltage of the inverter with two modulation signals is:
vo  MVin sin M t  high order harmonics (6.15)

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Fundamental of the instantaneous output voltage of the inverter with two modulation signals is:
vo,1  MVin sin M t (6.16)

The simulated output voltage of the SPWM single-phase full-bridge inverter with two modulation
signals by PSIM in frequency domain is shown in Fig. 6.23. In this simulation, Vin is 200V, fM is 50Hz,
fC is 5kHz, so that Mf is 100. M is 0.8. It shows that the amplitude of the fundamental is 160V which is
0.8 times of Vin and its frequency is 50Hz. The frequencies of the harmonics at nfC when n is 1,3,5,…
are very low. The main harmonics are at the frequencies 2nfC when n is 1,2,3…. The amplitude of the
2Mfth-order harmonic is just about 62V which is much lower than the amplitude of the fundamental of
the output voltage. The simulation results evident that the output voltage harmonics are reduced by
using two modulation signals SPWM method.

Vout
200.00
180.00
160.00
140.00
120.00
100.00
80.00
60.00
40.00
20.00
0.0
0.0 10.00 20.00 30.00 40.00
Frequency (KHz)
Fig. 6.23. Simulated output voltage of an SPWM single-phase full-bridge inverter
with two modulation signals in frequency domain

6.4.2. Sinusoidal Pulse-width-modulation Three-phase Full-bridge Inverters

A three-phase full-bridge inverter can be considered as three single-phase half-bridge inverters

connected in parallel. Fig. 6.24 shows a circuit diagram of a three-phase full-bridge inverter with a wye-
connected purely resistive load. SPWM technique can be also applied on this type of inverters.

iA
+

Vin T1 T3 T5
C1 D1 D3 D5
2
vAN RA
Vin A B vCA vAB vBN
0 C N vCN
RB RC
Vin T4 D4 T6 D6 T2 D2
+

iB
2 C2 vBC iC

Fig. 6.24. Circuit diagram of an SPWM three-phase full-bridge inverter with a wye-connected resistive load

Fig. 6.25 shows the idealised waveforms of an SPWM three-phase full-bridge inverter with a wye-
connected resistive load including phase to reference output voltage and line output voltage of each
phase. There are three modulation signals, vMA, vMB and vMC, and one carrier signal. Each modulation
signal is for generating gate signals of one leg of the inverter. vMA, , vMB and vMC are the signal for phase
A, B and C, respectively. The peak voltages and the frequency of all the modulation signals are the

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same but they have 120º degrees phase difference. All of these modulation signals are compared with
the same triangular carrier signal. After comparing the signals, the gate signals for T 1, T3, and T5, which
are vgs1, vgs3, and vgs5, are generated. The gate signal for T4, vgs4, is the inverse of vgs1. The gate signal
for T6, vgs6, is the inverse of vgs3. The gate signal for T2, vgs2, is the inverse of vgs5. As a result, the
operation of the three-phase SPWM inverter is the same as three single-phase SPWM half-bridge
inverters operating in parallel with 120º phase difference. The phase to reference output voltage of each
phase, vA0, vB0, and vC0, is bipolar. The output line voltage of each phase of the inverter, vAB, vBC, and vCA,
is unipolar. Referring to Fig. 6.24, the output phase voltages, vAN, vBN, and vCN, are also unipolar if the
inverter is loaded by a wye-connected load where N is the neutral node.

vMA vMB vMC

vgs1
vgs3
vgs5
Vin
vA0 2
vB0
-Vin
vC0 2
vAB

vBC
Vin
vCA
-Vin
Fig. 6.25. Idealised waveform of an SPWM three-phase full-bridge inverter with a wye-connected resistive load

Modulation index of an SPWM three-phase full-bridge inverter is:

2VˆA0 2VˆB 0 2VˆC 0 2VˆAN 2VˆBN 2VˆCN

M      (6.16)
Vin Vin Vin Vin Vin Vin
where VˆA0 , VˆB 0 , VˆC 0 are the peak value of v A0 , vB 0 and vC 0 , respectively. Also, VˆAN , VˆBN and VˆCN are
the peak value of v AN , vBN and vCN , respectively.

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The instantaneous output phase voltage of each phase of an SPWM three-phase full-bridge inverter is:
MVin
v AN  sin  M t  high order harmonics (6.17)
2
MVin  2 
vBN  sin  M t    high order harmonics (6.18)
2  3 
MVin  2 
vCN  sin   M t    high order harmonics (6.19)
2  3 
The instantaneous output line voltages of each phase of an SPWM three-phase full-bridge inverter is:

3MVin  
v AB  sin   M t    high order harmonics (6.20)
2  6
3MVin  
v BC  sin   M t    high order harmonics (6.21)
2  2
3MVin  5 
vCA  sin   M t    high order harmonics (6.22)
2  6 
The relationship of the output phase voltage and output line voltage is:
VˆLL  3VˆP (6.23)
where VˆLL is the peak output line voltage and VˆP is the peak output phase voltage of the inverter.

Computer simulation of an SPWM three-phase full-bridge inverter with wye-connected purely resistive
load has been done. Fig. 6.26 and Fig. 6.27 show the simulation resultsof the output line voltage and
output phase voltage of one phase of the inverter in frequency domain, respectively. In this simulation,
M is 0.8. fM is 50Hz and fC is 5kHz so that Mf is 100. Vin is 200V. The figures so that the harmonics of
the output voltage occur in the order of nMfth where n is 1,2,3.... The simulation results also evident that
the equation (6.23) is correct.
VAB
200.00
180.00
160.00
140.00
120.00
100.00
80.00
60.00
40.00
20.00
0.0
0.0 10.00 20.00 30.00 40.00
Frequency (KHz)
Fig. 6.26. Simulated waveform of output line voltage
of an SPWM three-phase full-bridge inverter in frequency domain

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VAN
100.00
90.00
80.00
70.00
60.00
50.00
40.00
30.00
20.00
10.00
0.0
0.0 10.00 20.00 30.00 40.00
Frequency (KHz)
Fig. 6.27. Simulated waveform of output phase voltage
of an SPWM three-phase full-bridge inverter in frequency domain

6.5. Switching Patterns of SPWM Inverters

Generating SPWM signals by using MCU or computer is very common in commercial products because
of its low costs for mass production. Sampling methods for generating SPWM is introduced as below.

6.5.1. Natural Sampling

This sampling method is formed by a natural comparison of VˆC

a sinusoidal wave with a triangular wave as shown in Fig. Vk
6.16. Fig. 6.28 shows a SPWM waveforms from natural VˆM
sampling. Vk is the modulating voltage, 0 is a quarter of the
switching period and k is the modulating angle. Let M as
the modulation index and:
δ0 δ0 δ0 δ0
Vˆ
M M (6.24)
Vˆ C δ1k δ2k

For the leading part, αk

Fig. 6.28. Switching pattern of SPWM
   0 
VˆM sin(  k   2 k )  VˆC  2 k  (6.25) from natural sampling
 0 
For the lagging part,
   0 
VˆM sin(  k  1k )  VˆC  1k  (6.26)
 0 
Hence, the switching pattern from natural sampling is:
1k   0 1  M sin(  k  1k ) (6.27)
 2k   0 1  M sin(  k   2k ) (6.28)
1k and 2k in equations (6.27) and (6.28) can be solved by mathematical method.

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6.5.2. Regular Sampling

Fig. 6.29 shows a SPWM waveforms from regular sampling.

This sampling method is modulating the voltage of the middle Vk VˆM
points of the leading and lagging parts, respectively.
Switching patterns from regular sampling for the leading and TS
lagging parts, respectively, are:
δ0 δ0 δ0 δ0
1k   0 1  M sin(  k   0 ) (6.29)
δ1k δ2k
 2k   0 1  M sin(  k   0 ) (6.30)
αk
Comparing with natural sampling, δ1k and δ 2k from regular
Fig. 6.29. Switching pattern of SPWM
sampling can be solved easily. However, natural sampling
from regular sampling
method is more accurate.

6.6. Overmodulation

Modulation index, M, is in the range from 0 to 1. If

VˆM  VˆC , it is overmodulation. Overmodulation should
be avoided because the output voltage is distorted and
low order harmonics occur. Fig. 6.30 shows the carrier
signal and the modulation signal under overmodulation
condition. Under overmodulation, calculated pulse
width of the SPWM signal becomes greater than the Fig. 6.30. Overmodulation
switching period, TS, or less than 0. Under this situation,
the calculated pulse width is limited to TS as maximum and 0 as minimum and hence, DC voltage
clamping occurs. In an inverter, switching devices will be either on or off for certain switching cycles
when the output voltage is near the upper and the lower peaks.

If the output of a 3-phase inverter is connected to a single balanced 3-phase load such as an AC
induction motor, 3rd harmonic modulation may be used. In this case, distortion may not be important
because the motor only understands the line voltages but not the phase voltages. The 3rd harmonic
appeared in each output will be cancelled in the line voltage. The 3rd harmonic modulation equations
from regular sampling with overmodulation are:
1k   0 1  M sin  k   0   KM sin 3 k   0  (6.31)
 2k   0 1  M sin  k   0   KM sin 3 k   0  (6.32)
where K is a constant equal to 1/6.

6.7. Resonant Inverters

Increasing efficiency of inverters, some soft-switching resonant inverters have been developed by
engineers. The most typical topologies are Resonant DC Link Inverters and Resonant Pole Inverters. In
industries, resonant pole inverters are more popular. Both of them are zero-voltage switching resonant
inverters. Fig. 6.31 and Fig. 6.32 show circuit diagrams of a three-phase resonant DC link inverter and a
resonant pole three-phase inverter, respectively.

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Lr
T1 D1 T3 D3 T5 D5
Vin

+
2 C1 A
Tr
Vin Cr Dr B
Vin C

+
2 C2 T2 D2 T4 D4 T6 D6

Fig. 6.31. Circuit diagram of a resonant DC link three-phase inverter

T1 Cr1 CF1 T3 Cr3 CF3 T5 Cr5 CF5

D1 D3 D5
Vin
+

LrA
2 C1 A
Vin B
LrB C
Vin LrC
+

2 C2 T2 D2 T4 D4 T6 D6
Cr2 CF2 Cr4 CF4 Cr6 CF6

Fig. 6.32. Circuit diagram of a resonant pole three-phase inverter

6.8. Charging Current of DC Link Capacitors of Inverters

DC link capacitors of inverters require high capacitance to SW

stabilize their voltage. When an inverter is just turned on,
i.e., connected to the power source, a very high start-up +
Rin
current occurs to charge up the DC link capacitors. This C1
DC

Load
high start-up current may cause instability of input power Vin Inverter
system and interference of other systems. This problem is Link
+

obvious especially in high power inverter systems. C2

Fig. 6.33 shows a block diagram of a DC link capacitor
system of an inverter for solving this problem. In this Fig. 6.33. DC link capacitor charging
system for high power inverters
system, a resistor, Rin, and a switch, SW, are added. The
switch can be a time controlled switch or a voltage
detected relay. In the beginning SW is off. When the inverter is connected to the power source, the DC
link capacitors, C1 and C2, are charged through Rin. Hence, Rin limits the capacitor charging current.
SW is switched on after few seconds or the capacitors fully charged to eliminate power loss on Rin.

6.9. MOSFET/IGBT Drivers for Inverters

In an inverter, e.g., a half-bridge single-phase inverter as shown in Fig. 6.2 (a), the top transistor, T1, is
floating. For controlling this floating transistor, special MOSFET/IGBT drivers are recommended. The
circuit diagrams of the drivers for driving transistors of inverters are shown in Fig. 6.34 and Fig. 6.35.
These drivers have capability to provide a bootstrap driving mechanism for the top transistor. The driver
shown in Fig. 6.34 has no deadtime function. The driver shown in Fig. 6.35 provides deadtime of 650ns
internally. This type of drivers has lower and upper limits of duty ratio for the floating transistors.

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Fig. 6.34. IR2110 Inverter driver for a half-bridge (from International Rectifier)

Fig. 6.35. IR2111 Inverter driver for a half-bridge (from International Rectifier)

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