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Implementing an Ethernet
Interface with the MC9S12NE64
By: Bill Lucas and Steven Torres
Systems Engineering
Austin, Texas
Introduction
This application note provides recommendations for implementing an Ethernet interface with the
MC9S12NE64 microcontroller unit (MCU). The discussion covers many topics including:
• Overview of the MC9S12NE64 including available packages
• Components required to add Ethernet functionality to the MC9S12NE64
• MC9S12NE64 schematics showing the minimum system design
• Circuit connections between the MC9S12NE64 and a high-speed LAN magnetics isolation module
and RJ45 connector
• General printed circuit board (PCB) layout recommendations for 10 and 100 Mbps Ethernet design
• High-speed LAN magnetics isolation module requirements
• Crystal placement and circuitry recommendations
• MC9S12NE64 Ethernet design examples in both 112-pin and 80-pin packages
This section introduces the MC9S12NE64 and provides an overview of the MC9S12NE64 integrated
Ethernet controller and MC9S12NE64 system design.
MC9S12NE64 Overview
The MC9S12NE64 is a 16-bit MCU based on Freescale Semiconductor’s HCS12 CPU platform. It
includes 8K bytes of RAM and 64K bytes of FLASH memory. In the 80-pin package, the MC9S12NE64
has other standard on-chip peripherals including two asynchronous serial communications interface
modules (SCIs), one synchronous serial peripheral interface (SPI), an inter-integrated circuit bus (IIC), a
4-channel/16-bit timer module (TIM), an 8-channel/10-bit analog-to-digital converter (ADC), and up to 18
pins available as keypad wake-up inputs (KWUs) or general-purpose I/O pins. In addition, an expanded
bus that can be operated at 16 MHz1 is available on the 112-pin package.
The MC9S12NE64 introduces a new peripheral for the HCS12 CPU platform, an integrated Ethernet
controller. The MC9S12NE64 integrates an Ethernet controller that includes a media access controller
(MAC) and a physical transceiver (PHY) in one die with the CPU, memory, and other HCS12 standard
on-chip peripherals. The MC9S12NE64 integrated Ethernet controller is compatible with IEEE 802.3 and
802.3u specifications for 10-Mbps or 100-Mbps operation, respectively.
1. At a 16-MHz internal bus speed, the MC9S12NE64 integrated Ethernet controller is limited to 10-Mbps operation. A 25-MHz
internal bus speed is required for 100-Mbps operation.
The MC9S12NE64 can be targeted at low-throughput connectivity applications that require operation
from a nominal 3.3-V power supply. With an on-chip bandgap-based voltage regulator (VREG), the
internal digital supply voltage of 2.5 V (VDD) will be generated internally. Figure 2 shows a block diagram
of the MC9S12NE64. More information on the MC9S12NE64 is available from the
Freescale Semiconductor website: http://freescale.com.
2 X SCI
64K FLASH
SPI IIC
V REG 3.3 V
8K RAM
INTERNAL BUS
TO 2.5 V CONVERTER
18 KEY WAKEUP
IRQ PORTS
ATD
10-BIT, 8 CH
EPHY
TIMER
EMAC 16-BIT, 4 CH
MC9S12NE64 Packages
The MC9S12NE64 is available in two packages. Table 1 provides device numbers for each package
Figure 3 shows the 112-pin LQFP package pin-out. Figure 4 shows the 80-pin TQFP-EP package pin out.
Table 1. MC68HCS908NE64 Package Options
Device Number Mask Set Temp Package
MC9S12NE64CFU 0L19S –40° C, 85° C 80TQFP-EP
MC9S12NE64CPV 0L19S –40° C, 85° C 112LQFP
The 80-pin TQFP-EP package does not have access to the multiplex address and data bus. It is designed
for single-chip applications that use the internal FLASH and RAM memory. The 80-pin TQFP-EP package
has an exposed flag for heat dissipation and requires special PCB layout to accommodate the flag. See
the Exposed Flag section.
PK7/ECS/ROMCTL
PJ6/KWJ6/IIC_SDA
PJ7/KWJ7/IIC_SCL
PK5/XADDR19
PK4/XADDR18
PK3/XADDR17
PK2/XADDR16
PK1/XADDR15
PK0/XADDR14
PT4/TIM_IOC4
PT5/TIM_IOC5
PT6/TIM_IOC6
PT7/TIM_IOC7
PAD7/AN7
PAD6/AN6
PAD5/AN5
PAD4/AN4
PAD3/AN3
PAD2/AN2
PAD1/AN1
PAD0/AN0
PK6/XCS
VDDA
VDD1
VSSA
VSS1
VRH
VRL
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
MII_TXER/KWH6/PH6 1 84 PL0/ACTLED
MII_TXEN/KWH5/PH5 2 83 PL1/LNKLED
MII_TXCLK/KWH4/PH4 3 82 VDDR
MII_TXD3/KWH3/PH3 4 81 PL2/SPDLED
MII_TXD2/KWH2/PH2 5 80 PA7/ADDR15/DATA15
MII_TXD1/KWH1/PH1 6 79 PA6/ADDR14/DATA14
MII_TXD0/KWH0/PH0 7 78 PA5/ADDR13/DATA13
MII_MDC/KWJ0/PJ0 8 77 PA4/ADDR12/DATA12
MII_MDIO/KWJ1/PJ1 9 76 PHY_VSSRX
ADDR0/DATA0/PB0 10 75 PHY_VDDRX
ADDR1/DATA1/PB1 11 74 PHY_RXN
ADDR2/DATA2/PB2 12 73 PHY_RXP
ADDR3/DATA3/PB3 13 72 PHY_VSSTX
VDDX1 14 MC9S12NE64-Family 71 PHY_TXN
VSSX1 15 112LQFP 70 PHY_TXP
ADDR4/DATA4/PB4 16 69 PHY_VDDTX
ADDR5/DATA5/PB5 17 68 PHY_VDDA
ADDR6/DATA6/PB6 18 67 PHY_VSSA
ADDR7/DATA7/PB7 19 66 PHY_RBIAS
MII_CRS/KWJ2/PJ2 20 65 VDD2
MII_COL/KWJ3/PJ3 21 64 VSS2
MII_RXD0/KWG0/PG0 22 63 PA3/ADDR11/DATA11
MII_RXD1/KWG1/PG1 23 62 PA2/ADDR10/DATA10
MII_RXD2/KWG2/PG2 24 61 PA1/ADDR9/DATA9
MII_RXD3/KWG3/PG3 25 60 PA0/ADDR8/DATA8
MII_RXCLK/KWG4/PG4 26 59 PL3/DUPLED
MII_RXDV/KWG5/PG5 27 58 PL4/COLLED
MII_RXER/KWG6/PG6 28 57 BKGD/MODC
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
XFC
KWG7/PG7
SPI_SCK/PS6
MODB/IPIPE1/PE6
MODA/IPIPE0/PE5
SCI0_RXD/PS0
SCI0_TXD/PS1
SCI1_RXD/PS2
SCI1_TXD/PS3
SPI_MISO/PS4
SPI_MOSI/PS5
SPI_SS/PS7
NOACC/PE7
ECLK/PE4
VSSX2
VDDX2
VDDPLL
VSSPLL
EXTAL
XTAL
PL6
PL5
LSTRB/TAGLO/PE3
R/W/PE2
IRQ/PE1
XIRQ/PE0
RESET
TEST
PJ6/KWJ6/IIC_SDA
PJ7/KWJ7/IIC_SCL
PT4/TIM_IOC4/
PT5/TIM_IOC5
PT6/TIM_IOC6
PT7/TIM_IOC7
PAD7/AN7
PAD6/AN6
PAD5/AN5
PAD4/AN4
PAD3/AN3
PAD2/AN2
PAD1/AN1
PAD0/AN0
VDDA
VSSA
VDD1
VSS1
VRH
VRL
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
MII_TXER/KWH6/PH6 1 60 PL0/ACTLED
MII_TXEN/KWH5/PH5 2 59 PL1/LNKLED
MII_TXCLK/KWH4/PH4 3 58 VDDR
MII_TXD3/KWH3/PH3 4 57 PL2/SPDLED
MII_TXD2/KWH2/PH2 5 56 PHY_VSSRX
MII_TXD1/KWH1/PH1 6 55 PHY_VDDRX
MII_TXD0/KWH0/PH0 7 54 PHY_RXN
MII_MDC/KWJ0/PJ0 8 53 PHY_RXP
MII_MDIO/KWJ1/PJ1 9 52 PHY_VSSTX
VDDX1 10 MC9S12NE64-Family 51 PHY_TXN
VSSX1 11 80 TQFP-EP 50 PHY_TXP
MII_CRS/KWJ2/PJ2 12 49 PHY_VDDTX
MII_COL/KWJ3/PJ3 13 48 PHY_VDDA
MII_RXD0/KWG0/PG0 14 47 PHY_VSSA
MII_RXD1/KWG1/PG1 15 46 PHY_RBIAS
MII_RXD2/KWG2/PG2 16 45 VDD2
MII_RXD3/KWG3/PG3 17 44 VSS2
MII_RXCLK/KWG4/PG4 18 43 PL3/DUPLED
MII_RXDV/KWG5/PG5 19 42 PL4/COLLED
MII_RXER/KWG6/PG6 20 41 BKGD/MODC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SCI0_RXD/PS0
SCI0_TXD/PS1
SCI1_RXD/PS2
SCI1_TXD/PS3
SPI_MISO/PS4
SPI_MOSI/PS5
SPI_SCK/PS6
SPI_SS/PS7
ECLK/PE4
VSSX2
VDDX2
VDDPLL
VSSPLL
EXTAL
XTAL
IRQ/PE1
XIRQ/PE0
RESET
TEST
XFC
The MC9S12NE64 is a single-chip Ethernet solution. Having built-in CPU, FLASH, RAM, MAC, and PHY
reduces the cost of implementing an embedded device with Ethernet connectivity, because no active
external components are required. The components required to enable the MC9S12NE64 Ethernet
interface include the following:
• MC9S12NE64 MCU
• 25-MHz crystal
• 3.3-V power supply
• External resistor for PHY_RBIAS pin (see data sheet for value of R Bias)
• High-speed LAN magnetics isolation module
• RJ45 connector
• Miscellaneous capacitors and resistors
• Optional: PHY status LEDs (available in some integrated RJ45 connectors)
• Optional: Background debug (BDM) connector
3.3V
C1
0.22
U1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VSS1
VSSA
VDD1
VRL
VDDA
VRH
PAD7/ AN7
PAD6/ AN6
PAD5/ AN5
PAD4/ AN4
PAD3/ AN3
PAD2/ AN2
PAD1/ AN1
PAD0/ AN0
PT5/ TIM_ IOC5
3.3V
1 60 PL0/ACTLED
MII_TXER/KWH6/PH6 PL0/ACTLED
C2
2 59
MII_TXEN/KWH5/PH5 PL1/LNKLED PL1/LNKLED
3 58 0.01
MII_TXCLK/KWH4/PH4 VDDR 3.3V
4 57 TRANSFORMER / RJ-45 CONNECTOR
MII_TXD3/KWH3/PH3 PL2/SPDLED PL2/SPDLED
R1 R2
5 56 T1
MII_TXD2/KWH2/PH2 PHY_VSSRX MCU SIDE CABLE SIDE
C3 0.22 49.9 49.9
6 55 6 6
MII_TXD1/KWH1/PH1 PHY_VDDRX R- J6 7
7 54 5 75 OHMS J7 8
MII_TXD0/KWH0/PH0 PHY_RXN CT J8 3
8 53 4 J3
MII_MDC/KWJ0/PJ0 PHY_RXP R+
9 52 RJ-45
MII_MDIO/KWJ1/PJ1 PHY_VSSTX
3.3V 10 51 3 2
VDDX1 PHY_TXN T- J2
11
VSSX1
MC9S12NE64 PHY_TXP
50 2
CT
75 OHMS J4
J5
4
5
0.22 1
C4 J1
12 49 1
MII_CRS/KWJ2/PJ2 PHY_VDDTX T+
C5 0.22 R3 R4 1000 pF
13 48 8 2kV
MII_COL/KWJ3/PJ3 PHY_VDDA .
49.9 49.9
14 47
MII_RXD0/KWG0/PG0 PHY_VSSA
R5
15 46
MII_RXD1/KWG1/PG1 PHY_RBIAS EARTH/CHASSIS
12.4k 1% C6 0.22
16 45
MII_RXD2/KWG2/PG2 VDD2
17 44
MII_RXD3/KWG3/PG3 VSS2
18 43
MII_RXCLK/KWG4/PG4 PL3/DUPLED PL3/DUPLED
19
MII_RXDV/KWG5/PG5 PL4/COLLED
42 PL4/COLLED OPTIONAL STATUS LED's
20 41
MII_RXER/KWG6/PG6 BKGD/MODC 3.3V
SCI1_ RXD/ PS2
SCI0_ RXD/ PS0
LED1
SPI_SS/ PS7
J1 R6
XIRQ/ PE0
ECLK/PE4
1 2
IRQ/ PE1
1 2 PL1/LNKLED
VDDPLL
VSSPLL
3 4
RESET
VDDX2
VSSX2
EXTAL
3 4 *RESET 220
TEST
XTAL
5 6 LNK_LED
XFC
5 6
3.3V
BACKGROUND DEBUG
LED2 R7
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
21
22
PL2/SPDLED
SPD_LED 220
*RESET
3.3V LED3 R8
PL3/DUPLED
DUP_LED 220
C7
25 MHz
0.22 Y1 LED4
R9
PL0/ACTLED
R10 220
ACT_LED
R11 C8 10M C9
C10 2.2k LED5
R12
15pF 15pF PL4/COLLED
470Pf C11
COL_LED 220
4700Pf
In Figure 5, the MC9S12NE64 in the 80-pin package will operate in normal single-chip mode. Figure 5
shows that the design operates with the internal voltage regulator enabled. Using the internal voltage
regulator is the recommended configuration for the MC9S12NE64. Figure 5 also illustrates the basic
MC9S12NE64 power and clock input requirements, which are described in following sections.
To configure the MC9S12NE64 (in a 112-pin package) in normal single-chip mode, the MODC, MODB,
and MODA pins may need to be pulled up or down. The operating mode of the MC9S12NE64, as well as
other HCS12 MCUs, out of reset is determined by the states of MODC, MODB, and MODA during reset.
MODC, MODB, and MODA can alternatively be configured by software. Table 2 describes the available
modes on the 112-pin package.
For details about modes, refer to the MC9S12NE64 device user guide.
The internal voltage regulator is a five-stage regulator that provides 2.5 V to the MC9S12NE64, including:
• CPU
• PLL
• PHY analog
• PHY transmitter
• PHY receiver
Alternatively, depending on the embedded design requirements, the MC9S12NE64 can be set up with the
internal voltage regulator disabled, which would require a 2.5-V external power supply for the logic plus
a 3.3-V supply for the PHY I/O. This application note describes MC9S12NE64 configuration with the
internal 2.5-V voltage regulator enabled. For configurations with the internal voltage regulator is disabled,
see the MC9S12NE64 data sheet for special circuitry requirements. Disabling the voltage regulator is not
recommended.
In addition to providing a 25-MHz crystal input, to operate at 100 Mbps, the internal bus clock must be
configured to 25 MHz. With the 25-MHz crystal, the CRG must be configured so the PLL is enabled and
multiplies the crystal oscillator clock to achieve the internal bus clock 25 MHz operational setting.
For 10 Mbps, an internal bus clock setting of 2.5 MHz minimum is acceptable, but a 25-MHz crystal input
is still required.
For details about the CRG and configuring the PLL, see Freescale Semiconductor document AN2692/D:
MC9S12NE64 Integrated Ethernet Controller.
TX CT 3.3 V
T+ PHY_TXP
T- PHY_TXN
RX CT 3.3 V
R+ PHY_RXP
R- PHY_RXN
The section provides recommendations for PCB design and high-speed LAN magnetics isolation module
selection.
The PCB layout must be designed to ensure proper operation of the voltage regulator and the MCU. The
following recommendations are provided to ensure a robust PCB design:
• Every supply pair must be decoupled by a low-ESR (equivalent series resistance) ceramic
capacitor connected as near as possible to the corresponding pins.
• Central point of the ground star should be the VSSX1 and VSSX2 pins.
• Use low-ohmic, low-inductance connections with VSS1, VSS2, VSSX1, and VSSX2 pins.
• VSSPLL must be directly connected to VSSX.
• Keep traces of VSSPLL, EXTAL, and XTAL as short as possible and their occupied board area as
small as possible.
When designing a PCB that uses the MC9S12NE64 Ethernet module, several design considerations
must be made to ensure that Ethernet operation conforms to the IEEE 802.3 physical interface
specification. Use the following recommendations for PCB design between the high-speed LAN
magnetics isolation module and:
• MC9S12NE64 EPHY external pins (most critical)
• RJ45 connector
Ethernet PCB design recommendations:
• The distance between the magnetic module and the RJ-45 jack is the most critical and must always
be as short as possible (must be less than one inch).
• Never use 90° traces. Use 45° angles or radius curves in traces.
• Trace widths of 0.010” are recommended. Wider is better. Trace widths should not vary.
• Route differential Tx and Rx pairs near together (max 0.010” separation with 0.010” traces).
• Trace lengths must always be as short as possible (must be less than one inch).
• Make trace lengths as equal as possible.
• Keep TX and RX differential pairs routes separated (at least 0.020” separation). Better to separate
with a ground plane.
• Avoid routing Tx and Rx traces over or under a plane. Areas under the Tx and Rx traces should be
open, See Figures 9, 10, 11, 17 and 18.
• Use precision components in the line termination circuitry with 1% tolerance.
• Ensure that the power supply is rated for a load of 300 mA minimum.
• Avoid vias and layer changes.
In addition, all termination resistors should be near to the driving source. The MCU is the driving source
for PHY_TXP and PHY_TXN pins. The high-speed LAN magnetics isolation module is the driving source
for PHY_RXP and PHY_RXN pins.
The MC9S12NE64 requires a 1:1 ratio transformer for the high-speed LAN magnetics isolation module
for both the receive and the transmit signals. The basic high-speed LAN magnetics isolation module
specification requirements are provided in Table 5. High-speed LAN magnetics isolation modules that
meet these requirements are available from a variety of manufacturers.
Transformer 1500 V —
The MC9S12NE64 can be used with high-speed LAN magnetics isolation modules that are either discrete
or integrated into a RJ45 connector. Some of these integrated connectors have built-in LEDs as well. For
the MC9S12NE64, an RJ45 connector with an integrated high-speed LAN magnetics isolation module is
recommended because it reduces component count and simplifies PCB layout.
Because the MC9S12NE64 does not implement Auto-MDIX, an Auto-MDIX capable high-speed LAN
magnetics isolation module is not required. A high-speed LAN magnetics isolation module with improved
return loss characteristics is recommended to avoid Ethernet return loss issues.
Table 6 provides discrete and integrated high-speed LAN magnetics isolation modules that have been
found in testing to satisfy the requirements necessary to establish an IEEE-compliant Ethernet interface
with the MC9S12NE64. Other models can be used as long as the high-speed LAN magnetics isolation
module specifications satisfy the requirements.
Although specific hardware is discussed in this section, Freescale Semiconductor does not recommend
or endorse any particular product or vendor. This data is provided only to describe the specification
requirements.
Design Examples
This section shows two MC9S12NE64 design examples of Ethernet interface implementations with the
MC9S12NE64 in a minimum system. These minimum system examples are provided only to demonstrate
recommended MC9S12NE64 PCB design. These MC9S12NE64 design examples are test boards, and
they are not available for purchase.
The first design shows a minimum system using the MC9S12NE64 in a 112-pin package. The second
design is an example of a system using the 80-pin MC9S12NE64 with a very compact PCB footprint.
Schematics and all artwork layer views for both designs will be shown in this section. Both designs are
implemented on 4-layer PCBs to provide better heat dissipation. Both boards are minimum system
designs that use the internal voltage regulator.
A photo of the MC9S12NE64 112-pin package design example is provided in Figure 7. The PCB, which
is approximately 6.3 cm x 6.3 cm, was designed using the recommendations discussed in the PCB Design
Recommendation section. This design and PCB layout are discussed in detail in following sections.
3.3V
.22 .1
112
111
110
106
105
104
103
102
101
100
109
108
107
3.3V
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
U1
VSSA
VSS1
VRL
VDD1
VRH
VDDA
PK6/ XCS/ SYMBOL_ MODE
0.01
1 84 PL0/ACTLED
MII_TXER/KWH6/PH6 PL0/ACTLED/LEDT
2 83
MII_TXEN/KWH5/PH5 PL1/LNKLED/LEDL PL1/LNKLED/LEDL
3 82 R11
MII_TXCLK/KWH4/PH4 VDDR 3.3V
50
4 81
MII_TXD3/KWH3/PH3 PL2/SPDLED/LEDS PL2/SPDLED/LEDS
5 80 J2
MII_TXD2/KWH2/PH2 PA7/ADDR15/DATA15 4
6 79 R14 4 RX+
MII_TXD1/KWH1/PH1 PA6/ADDR14/DATA14 50 5
7 78 5 RX_CT
MIDCOM JFM2411-0101W
MII_TXD0/KWH0/PH0 PA5/ADDR13/DATA13 6
8 77 6 RX-
MII_MDC/KWJ0/PJ0 PA4/ADDR12/DATA12
9 76 1
MII_MDIO/KWJ1/PJ1 PHY_VSSRX .22 C11 1 TX+
10 75 R8 2
ADDR0/DATA0/PB0 PHY_VDDRX 50 2 TX_CT
11 74 3
ADDR1/DATA1/PB1 PHY_RXN 3 TX-
12 73
ADDR2/DATA2/PB2 PHY_RXP R12 14
13 72 50 13 14 LED1AYELLOW
ADDR3/DATA3/PB3 PHY_VSSTX 13 LED1C
14 71 12
3.3V VDDX1 PHY_TXN 11 12 LED2AGREEN
15 70 11 LED2C
9 CASE
VSSX1 PHY_TXP
8ERTH
.22 C10
16 69
10
ADDR4/DATA4/PB4 PHY_VDDTX R13
.22 C9
PL1/LNKLED/LEDL
17 68
10
ADDR5/DATA5/PB5 PHY_VDDA 330
9
18 67 R15
ADDR6/DATA6/PB6 PHY_VSSA
R10 PL2/SPDLED/LEDS
19 66
ADDR7/DATA7/PB7 PHY_RBIAS .22 C6 330
20 65 EARTH/CHASSIS
MII_CRS/KWJ6/PJ2 VDD2
21 64
MII_COL/KWJ7/PJ3 VSS2
22 63
MII_RXD0/KWG0/PG0 PA3/ADDR11/DATA11
23 62
OPTIONAL STATUS LED's
MII_RXD1/KWG1/PG1 PA2/ADDR10/DATA10 3.3V
24 61
MII_RXD2/KWG2/PG2 PA1/ADDR9/DATA9 LED2 R3
SCAN_ ENABLE/ SCI1_ RXD/ PS2
25 60 PL3/DUPLED
MII_RXD3/KWG3/PG3 PA0/ADDR8/DATA8
SCAN_ RESET/ SPI_ SCK/ PS6
DISABLE100/ SCI0_ TXD/ PS1
26 59 DUP_LED 220
MII_RXCLK/KWG4/PG4 PL3/DUPLED/LEDD PL3/DUPLED 3.3V
R16 R5
ANLG_TST/R/W/PE2
MODB/ IPIPE1/ PE6
LSTRB/TAGLO/PE3
28 57 PL0/ACTLED
MII_RXER/KWG6/PG6 BKGD/MODC/SCANCLK2
TEST/ VPP
VDDPLL
VSSPLL
LED1
RESET
VDDX2
EXTAL
R7
VSSX2
BACKGROUND DEBUG
XTAL
XFC
PL4/COLLED
PL6
PL5
1 2
3 1 2 4 COL_LED 220
5 3 4 6 *RESET
48
49
50
51
46
47
52
53
54
55
56
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
5 6
3.3V
J1
3.3V 3.3V
R1
GND 2 3 + C14 C15 330 LED4
R4 3
27k
R9 EARTH J3 C16 100 uF 0.22 0.01 POWER
2.2k C5
C7 C2 10M C1
SW1 2
R2
470 pF C8 0.1 15 pF 15 pF JP1
2
*RESET TP1
47 4700 pF 2-PIN JUMPER
1
RESET
1
C3 GND TESTPOINT
1
0.22
1
Figure 8. Minimum 112-Pin Package System Schematic
Design Examples
SPLIT
Ground planes and how grounds are tied together affect noise immunity. To maximize noise immunity, it
is important to get a good ground plane under the MCU. It is also a good practice to have the ground plane
under the crystal components. Note, on the layout, Figure 10, there is a white area to the left of the MCU.
That area is directly under the Ethernet transmit and receive traces from the MCU to the high-speed LAN
magnetics isolation module. That area under those traces must be devoid of any ground plane to reduce
capacitance.
As shown in Figure 9 and Figure 10, there is a split in the ground plane. It starts just to the right of the top
center of the PC board and continues down to just above the center of connector J3. The center pin of J3
is the system ground connection. This split in the ground plane forces the system’s ground currents to
flow to a common point, the ground connection for the PC board. This technique helps increase noise
immunity in the system.
As shown in Figure 11, attention was given to the length of the Ethernet transmit and receive pairs that
go between the MCU and the Ethernet integrated magnetics/RJ45 connector. They were made as short
as possible for this mechanical layout. The PC board tracks in the Ethernet portion of this design are
0.010” and the maximum conductor length is just under 0.5”. The PC board traces bend on 45° angles,
with no 90° angles. Figure 11 demonstrates these design practices.
SPLIT
Ground Layer
WHITE
AREA
Top Layer
Bottom Layer
As with all designs, place the crystal and its associated components as near to their MCU pins as possible
and use minimum trace lengths. This is also true with the XFC connections (PLL components).
There are a number of power supply decoupling capacitors necessary to decouple the MCU and its
various internal power supplies. These pins are VDD1, VDD2, VDDA, VDDPLL, PHY_VDDRX, and
PHY_VDDTX. These capacitors should be good quality, low ESR type ceramic components.
The second design example uses the 80-pin MC9S12NE64 and uses the PCB design recommendations
discussed for the 112-pin design example. A photo is provided in Figure 12.
This example demonstrates that the MC9S12NE64 can implement Ethernet capability in a very small
package footprint. This 80-pin design example resides on a very small 1” x 1.5” PCB and shows a
complete Ethernet PCB system implementation. The design example uses the PCB recommendations
described in this application note. A schematic of this design example is provided in Figure 13.
76
74
72
71
70
69
68
67
65
63
61
81
80
78
77
75
73
66
64
62
79
U1 3.3V
VSSA
VSS1
VRH
VRL
FLAG
VDDA
VDD1
PAD7/ AN7
PAD6/ AN6
PAD5/ AN5
PAD4/ AN4
PAD3/ AN3
PAD2/ AN2
PAD1/ AN1
PAD0/ AN0
PT4/ TIM_ IOC4
1 60 0.01
MII_TXER/KWH6/PH6 PL0/ACTLED
2 59
MII_TXEN/KWH5/PH5 PL1/LNKLED PL1/LNKLED
3 58 3.3V
MII_TXCLK/KWH4/PH4 VDDR R7
4 57 49.9
MII_TXD3/KWH3/PH3 PL2/SPDLED PL2/SPDLED
5 56
MII_TXD2/KWH2/PH2 PHY_VSSRX J1
C12 0.22
6 55 R5 6
MII_TXD1/KWH1/PH1 PHY_VDDRX 49.9 6 RX-
7 54 5
MII_TXD0/KWH0/PH0 PHY_RXN 5 RX_CT
8 53 4
MIDCOM JFM2411-0101W
MII_MDC/KWJ0/PJ0 PHY_RXP 4 RX+
9 52
MII_MDIO/KWJ1/PJ1 PHY_VSSTX 3
10 51 3 TX-
3.3V VDDX1 PHY_TXN R6 2
11 50 49.9 2 TX_CT
VSSX1 PHY_TXP 1
12 49
C9 0.22 1 TX+
MII_CRS/KWJ6/PJ2 PHY_VDDTX 3.3V
13 48 R8 14 lnk green
MII_COL/KWJ7/PJ3 PHY_VDDA 49.9 13 14 LED1A YELLOW spd green
C11 0.22
14 47 13 LED1C
duplex = third LED green
MII_RXD0/KWG0/PG0 PHY_VSSA 12
R9 12 LED2A GREEN
15 46 11
MII_RXD1/KWG1/PG1 PHY_RBIAS 11 LED2C
CASE
8ERTH
16 45 12.4k 1%
MII_RXD2/KWG2/PG2 VDD2 R2
10
C8 0.22 PL1/LNKLED
9
17 44 330
MII_RXD3/KWG3/PG3 VSS2
10
18 43 3.3V
9
MII_RXCLK/KWG4/PG4 PL3/DUPLED R12 R3
PL2/SPDLED
19 42
MII_RXDV/KWG5/PG5 PL4/COLLED 10k 330
R13
20 41 10k
MII_RXER/KWG6/PG6 BKGD/MODC
SCI0_ RXD/ PS0
J2
SCI1_ TXD/ PS3
SCI0_ TXD/ PS1
1 2
SPI_SS/ PS7
3 1 2 4
XIRQ/ PE0
ECLK/PE4
SCI_Tx 3 4 *RESET
IRQ/ PE1
VDDPLL
5 6
VSSPLL
RESET
VDDX2
VSSX2
EXTAL
5 6
TEST
XTAL
SCI_Rx 3.3V
XFC
BACKGROUND DEBUG
23
25
27
29
30
31
32
33
34
36
38
40
21
24
26
28
35
37
39
22
LED1 R4 3.3V
3.3V
*RESET
SCI_Rx
SCI_Tx
USER_LED 330
3.3V
25 MHz
Y1
Citizen page 627,top left
0.22 C3 300-8105-1-ND
1
C2 470Pf R11
R10 C5
+3.3V P1 C6 + C4 330
1
10M
2
R1 10 uF
C1 C13 C10 GND 0.1 0.01
2
4700pF
LED2
POWER
Figure 14 provides all artwork for the MC9S12NE64 80-pin package design example.
All Layers
Exposed Flag
Because the 80-pin TQFP-EP package has an exposed flag, which provides additional heat dissipation
for the MC9S12NE64, the artwork shows special PCB design to accommodate the exposed flag. There
are two ways to accommodate the flag:
• Have a hatched pattern in the solder mask
• Use small copper areas under the flag
The concept is to have about 50% of the flag soldered to the PC board.
Conclusion
The MC9S12NE64 is a highly integrated, flexible and easy-to-use Ethernet-capable microcontroller with
an integrated MAC and PHY. No external active components are needed to implement an Ethernet
interface. The schematics in this document illustrate the simplicity of implementing such a system.
Interfacing the device to an Ethernet trunk is accomplished with the addition of only four resistors, a
decoupling capacitor and an integrated transformer/RJ45 connector. PCB layout around the high-speed
LAN magnetics isolation module is critical, as with any high frequency design. Using techniques
discussed in this document makes that task easier.
NOTE
With the exception of mask set errata documents, if any other Freescale Semiconductor document
contains information that conflicts with the information in the device user guide, the user guide should be
considered to have the most current and correct data.
Notes
AN2759
Rev. 0.2, 9/2004