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MY PROFILE Solution Report For Digital Electronics Part 1
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Q.1 Consider the circuit given below
Which of the following statements is true for Y.
a.
b.
c.
d.
Q.2 Two half adders are connected in cascade as shown below.
The output ‘S ’ and ‘C ’ is
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a.
b.
c.
d.
Q.3 Consider the circuit shown in figure below
If propagation delay of NOT gate is 10 nsec, AND gate is 20 nsec and X OR gate is
10 nsec. If A is connected to V CC at t = 0, then waveform for output Y is
a.
b.
c.
d.
Q.4 Which of the following statement is Incorrect for the range of n bits binary
numbers
a. Range of unsigned numbers is 0 to 2n – 1.
b. Range of signed numbers is –2n – 1 + 1 to 2n – 1 – 1
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Q.5 Consider the logical functions given below.
f1 (A, B, C) = Σ(2, 3, 4)
f2 (A, B, C) = π(0, 1, 3, 6, 7)
If f is logic zero, then maximum number of possible minterms in function f3 are
_____.
Q.6 A one bit full adder takes 75 nsec to produce sum and 50 nsec to produce carry.
A 4 bit parallel adder is designed using this type of full adder. The maximum rate
of additions per second can be provided by 4 bit parallel adder is A × 106
additions/sec. The value of A is _____ .
Q.7
If in a base ‘r ’ number system the base of the number system is
_________.
Q.8 Consider the digital circuit shown below
It represents
a. Half adder followed by half subtractor
b. Half subtractor followed by half adder
c. Half adder followed by a half adder
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d. A full adder
a. ADE
b.
c.
d. BD(C + E)
Q.10 The logic function f (A, B, C, D) implemented by the circuit shown below is
a.
b.
c.
d.
Q.11 Consider a System S as shown in the figure below
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System S performs 1’s compliment of the input and then 2’s compliment to
produce output. A new System H is designed in which 3 System S are cascaded
a. 1010
b. 0101
c. 1101
d. 1100
Q.12 Consider the logic circuit given below
The minimized expression for F is
a.
b.
c.
d.
Q.13 Consider the logic circuit given below:
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The value of ‘n’ is ______.
Q.14 A logical function is given as F(A, B, C, D) = Σm (0, 4, 5, 10, 11, 13, 15). The number
of Essential Prime Implicants in the minimized expression will be _________.
Q.15 The minimum number of NOR gates required to realize the half adder circuit is
________.
Q.16 The output Y of a 2 bit comparator is logic 1 whenever the 2 bit input A is greater
than the 2bit input B. The number of combinations for which the output is logic 1
is _________.
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