Expt. No.

Date:

STUDY OF LOGIC GATES

OBJECTIVE:
To study and verify the truth table of logic gates.

ACQUISITION:
APPARATUS REQUIRED:

S.NO APPARATUS RANGE TYPE QUANTITY

1. Digital IC Trainer Kit - - 1

2. AND GATE - IC 7408 1
3. OR GATE - IC 7432 1
4. NOR GATE - IC 7402 1
5. NAND GATE - IC 7400 1
6. NOT GATE - IC 7404 1
7. EX-OR GATE - IC 7486 1
8. Patch chords - - few

THEORY:
AND GATE:
An AND gate is one which has two or more inputs. The output is high only when
both the inputs are high for a two input AND gate. The output results from input A & B.
Boolean equation is indicated by
C=A. B
If A=B=1 then C=1.1=1 ; If A=B=0 then C=0.0=0
If A=0, B=1 (or) B=0,A=1 then C=1.0 (or) 0.1=0

OR-GATE:
An OR gate is the one which has two (or) more inputs. If any one of the inputs is in
the high state, than the output is high for two inputs OR gate. The output results from inputs
A or B. Boolean equation relating the variables is an OR gate indicated by
C=A+B
If A=B=1 then C=1+1=1 ; If A=1,B=0 then C=1+0=1
If A=B=0 then C=0+0=0.

NOT GATE:
The NOT gate is the one which has one inputs the output contradict the inputs (i.e.)
when the input is high there is no output, but when the input is low, the output is high. The
outputs results from one input A. Boolean equation is given by
C = A , If A=1 then C=0, If A=0 then C=1

4
NOR GATE:
The NOR gate (or) the NOT-OR gate is the one which is got from two inputs. The
output is high only when both the inputs are low. In all other cases, output is not high.
Boolean equation relating to the variable is a NOR gate is indicated by
C=A+B

NAND GATE:
In NAND gate (or) NOT-AND gate has two (or) more inputs. The output is low only
when both the inputs are high. All other cases the output is high for a two input NAND gate.
Boolean equation is indicated by
C = A.B
If A=B=1 then C=0 ; All other cases, C=1

EX-OR GATE:
Exclusive OR gate or XOR gate has two or more inputs. The output is low only when
both the inputs are equal else the output is high. Boolean equation relating the XOR gate of
two input variables A & B is indicated by
C= A B
If A=B then C=0, A=B then C=1

PROCEDURE:
1. Fix the IC on the IC Trainer Kit.
2. Connections are made as shown, using the pin details of the gates. Toggle
switches and LEDs in the trainer kit are used as inputs and outputs respectively.
3. Switch on the supply on the trainer kit and verify the truth table of the gates.

[1] AND GATE: CIRCUIT

A 1 330
3
7408

B 2

PIN DIAGRAM:

Vcc
14 13 12 11 10 9 8

IC 7408

1 2 3 4 5 6 7

GND
5
[2] OR GATE: CIRCUIT

A 1 330
7432 3

B 2

PIN DIAGRAM:

Vcc
14 13 12 11 10 9 8

IC 7432

1 2 3 4 5 6 7

GND

[3] NOT GATE: CIRCUIT:

330
A A

7404
PIN DIAGRAM:

Vcc
14 13 12 11 10 9 8

IC 7404

1 2 3 4 5 6 7

6
GND
[4] NOR GATE: CIRCUIT

A 2 330
7402 1

B 3

PIN DIAGRAM:

Vcc
14 13 12 11 10 9 8

IC 7402

1 2 3 4 5 6 7

GND
[5] NAND GATE: CIRCUIT

A 1 330
3
7400

B 2

PIN DIAGRAM:

Vcc
14 13 12 11 10 9 8

IC 7400

1 2 3 4 5 6 7

GND
7
[6] EX OR GATE: CIRCUIT
A 2 330
1
7486

B 3

PIN DIAGRAM:

Vcc
14 13 12 11 10 9 8

7
7
4
4
IC 7486

7 7
4 4

1 2 3 4 5 6 7

GND
TRUTH TABLE
[1] AND GATE:

A B C = A.B
0 0 0
0 1 0
1 0 0
1 1 1

[2] OR GATE:

A B C = A+B
0 0 0
0 1 1
1 0 1
1 1 1

[3] NOT GATE:

A C=A

0 1
1 0

8
[4] NOR GATE:

A B C = A+B
0 0 1
0 1 0
1 0 0
1 1 0

[5] NAND GATE

A B C = A.B
0 0 1
0 1 1
1 0 1
1 1 0

[6] EX-OR GATE

A B C=A B
0 0 0
0 1 1
1 0 1
1 1 0

INFERENCE

RESULT

9
Expt. No. Date:

STUDY OF FLIP FLOPS

OBJECTIVE:
To study the working of RS flip flop [using NOR & NAND gate], clocked RS flip
flop [using NOR gate], JK flip flop, T flip flop & D flip flop.
ACQUISITION:
APPARATUS REQUIRED:

S.NO APPARATUS RANGE TYPE QUANTITY

1. Digital IC Trainer Kit - - 1
2. NAND GATE - IC 7400 1
3. NOR GATE - IC 7402 1
4. AND GATE - IC 7408 1
5. JK flip flop - IC 7476 1
6. D flip flop - IC 7474 1
7. Patch chords - - few

THEORY:
FLIP FLOP:
A flip flop is a basic memory element used to store one bit of information. A flip flop
is called as bistable multivibrator (or) catch command. This can be triggered into either of
the two stable states. For any sequential system, we must have a storage device to remember
(or) retain the information about what has happened in the past & to recall the information
later when required. The basic unit for storage is called flip flop. There are several types of
flip flops having different characters with information storage & retrieved. If an input causes
it to go to its state i

R-S FLIP FLOP:

-S
Flip Flop, he application of momentary 1 to set input causes the flip flop to go to the set state
(or) a momentary 1 applied to reset input causes flip flop to go to the clear state. When a 1 is

and is usually avoided. In NAND gate based R-S Flip Flop, the application of momentary 0

state becomes undefined.

CLOCKED R-S FLIP FLOP:

When the clock pulse goes to 1, information from the S and R inputs is allowed to
reach the basic flip-flop. The set state is reached with S=1, R=0 & CP=1. To change to the
reset state, the inputs must be S=0, R=1 & CP=1. With both S=1 and R=1, the occurrence of
a clock pulse causes both outputs to momentarily go to 0. When the pulse is remoed, the
state of the flip-flop is indeterminate.

JK FLIP FLOP:

10
 A JK flip flop is a refinement of RS flip flop in that the indeterminate state of the RS
flip flop is defined in the JK flip flop. Inputs J & K behaves like input S & R, to set & reset
the flip flop, respectively. When both the inputs J=K=1, the flip flop switches to its
complement state (i.e.) if Q=1 it switches to Q=0 & vice versa. Because of the feedback, a
clock that remains in the state while both J & K are equal to 1 will cause the output to
complement again & repeat simultaneously until the pulse goes back to 0. This undesirable
condition must be avoided.

T FLIP FLOP:
The T flip flop is obtained from JK flip flop. When both input are tied together
regardless of the present state, the flip flop complements into output when the CP occurs with

D FLIP FLOP:
One way to eliminate the undesirable condition of the indeterminate state in the RS
flip flop is to ensure that both the input levels are not equal to 1 at the same time. This is done
in the D Flip-flop. So, now one input is complemented & applied to the other. It has only D
input & clock. When CP=1 & D=1, Q output goes to 1 and when D=0, Q goes to 0 (clear
state). The D flip flop receives the designation from its ability to hold data into its internal
storage.

PROCEDURE:
1. Connections are made as shown in the Logic diagrams, using the pin details of

2. Switch on the power supply of the Trainer Kit.

3. Verify the truth table of all flipflops.

[1] RS FLIP FLOP USING NOR GATE:

R
IC
7402

330

IC
S 7402

330

11
[2] RS FLIP FLOP USING NAND GATE:

R IC
7408

330

IC
7408
S

330

[3] CLOCKED RS FLIP FLOP:

R
IC IC
7408 7402

IC 330
7408 IC
S
7402

330

12
[4] D FLIP FLOP:

D
IC IC
7408 7402

IC
7402
330

IC
IC 7402
7408

330

[5] T FLIP FLOP:

330

T
330
IC 7476

13
[6] JK FLIP FLOP:

1K
1 16 330
1 PRE
2 15
1 CLR
3 14
1J
4 13 330
VCC IC 7476 2K
5 12
2CLK 2Q
6 11
2PRE 2Q
7 10
2CLR 2J
8 9

[1] RS FLIP FLOP USING NOR GATE:

TRUTH TABLE :

S R Q Q
0 0 0 1
0 1 0 1
1 0 1 0
1 1 undetermined

SEQUENCE TABLE:

S R QN QN+1 STATE
0 0 0 0 No change
0 0 1 1
0 1 0 0 Reset
0 1 1 0
1 0 0 1 Set
1 0 1 1
1 1 0 X Indeterminate
1 1 X X state

14
[2] RS FLIP FLOP USING NAND GATE:
TRUTH TABLE :

CLK S R Q Q
0 0 Q Q
0 1 0 1
0 0 0 1
1 0 1 0
0 0 1 0
1 1 X X

[3] CLOCKED RS FLIP FLOP:

TRUTH TABLE :

S R Q Q
1 1 Q Q
0 1 1 0
1 0 0 1
0 0 In determinant

SEQUENCE TABLE:

S R QN QN+1 STATE
0 0 0 X In determinant
0 0 1 X
0 1 0 1 Set
0 1 1 1
1 0 0 0 Reset
1 0 1 0
1 1 0 0 No change
1 1 1 1

[4] D FLIP FLOP:

TRUTH TABLE :

CLK D Q n+1
0 0
1
1

15
[5] T FLIP FLOP:
TRUTH TABLE :
Q T Q t+1
0 0 0
0 1 1
1 0 1
1 1 0

[6] JK FLIP FLOP:

TRUTH TABLE :

J K Q Q t+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

INFERENCE

RESULT

16
Expt. No. Date:

IMPLEMENTATION OF ADDER, SUBTRACTOR CIRCUIT

OBJECTIVE:
To design and implement Adder, Subtractor circuits (Half Adder, Full Adder, Half
Subtractor, and Full Subtractor) and to verify their truth table.

ACQUISITION
APPARATUS REQUIRED:
S.NO APPARATUS RANGE TYPE QUANTITY
1. Digital IC Logic Tester - - 1
2. AND GATE - IC 7408 1
3. EX-OR GATE - IC 7486 1
4. OR GATE - IC 7432 1
5. NAND GATE IC 7400 2

THEORY:
HALF ADDER:
When we add 2 binary numbers, we start with least significant column. This means
that we have to add two bits with possibility of carry. The circuit used for this is called a half
adder. In the figure, output of OR gate is sum and output of AND gate is carry.
A half addition is an addition of 2 bits When 2 bits are added, sum and carry will
result. Therefore, for half adder circuit, number of inputs will be 2 and number of outputs will
be 2.

FULL ADDER:
Logic circuits that can add 3 bit at a time is called full adder circuit. The third bit is
the carry from a lower column (i.e.) we need a logic circuit with 3 inputs and 2 outputs. A full
adder is a digital circuit, which is used for adding 3 bits. It accepts 3 inputs and generates a
sum output and a carry output.

SUBTRACTOR:
The subtraction of 2 binary numbers may be accomplished by taking the complement
of the subtrahend and adding it to minuend. By this method the subtraction operation
becomes an addition operation requiring full adder for its machine implementation. If the
minuend bit is smaller than the subtrahend bit, a 1 is borrowed from the next significant
position. The fact that a 1 has been borrowed must be conveyed to next higher pair of bits by
means of a binary signal coming out (output) of a given stage and going into (input) the next
higher stage.

HALF SUBTRACTOR:
It is a combinational circuit that subtracts 2 bits and produces their difference. It also
has an output to specify if a 1 has been borrowed. Let minuend bit be A and subtrahend bit be
B. To perform A-B, we have to check the relative magnitudes of A and B. If A>B, we have 3
possibilities: 0-0=0; 1-0=1 & 1-1 =0. The result is called difference bit.

17
 If A<B we have only one possible operation 0-1 and it is necessary to borrow a 1
from next higher stage. The 1 borrowed from next higher stage adds 2 to minuend bit just as
in the decimal system, a borrow adds 10 to a minuend digit. With the minuend equal to 2, the
difference becomes 2-1=1. Hence, now the half subtractor needs 2 outputs, one output
generates the difference (D). The 2nd output for borrow (B), generates binary signal that
informs the next stage that 1 has been borrowed. The output borrow B is 0 as long as A B.

FULL SUBTRACTOR:
It is a combinational circuit that performs a subtraction between 2 bits, taking into
account that borrow of the lower significant stage. The circuit has 3 inputs and 2 outputs. The
3 inputs A,B,C denotes minuend, subtrahend and previous borrow respectively. The outputs

-B-C.
The combinations having input borrow C=0, reduce to same 4 conditions of half subtractor.

PROCEDURE:
1. Fix all the ICs on the breadboard.
2. Pin 7 and Pin 14 of all ICs are grounded and connected to power supply,
respectively.
3. The truth table is verified for different combinations of input.

[1] HALF ADDER:

A 1
3
7408 Carry =A.B

B 2

1
3
7486
Sum =AB +AB
2

18
[2] FULL ADDER

[2] HALF SUBTRACTOR

1
A 3
7486 D =Difference
B
2

7404
1
1
2 3
7408

19
[4] FULL SUBTRACTOR

1
A 3 4
7408 6 10
7408 8
7408
2
5
9
B
1
7486 3 12
11 1
7408 3
2 7408
13
2

9
8
7486 D = Difference

10

TRUTH TABLE:
[1] HALF ADDER:
A B Carry Sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

[2] HALF SUBTRACTOR

A B Carry Sum
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

20
[3] FULL ADDER

A B C Carry Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

[4] FULL SUBTRACTOR

A B C Borrow Difference
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

INFERENCE

RESULT

21
Expt. No. Date:

BOOLEAN FUNCTION, PARITY GENERATION AND CHECKING

OBJECTIVE:
(i) To implement the given Boolean function using gates.
(ii) To generate, check and detect errors in a code, using Parity bits.

ACQUISITION:
APPARATUS REQUIRED:

S.NO APPARATUS RANGE TYPE QUANTITY

1. Digital IC Trainer Kit - - 1
2. XOR gate - IC 7486 1
3. Patch chords - - few

THEORY:
Exclusive-OR functions are very useful in systems requiring error detection and
correction codes. A parity bit is used for the purpose of detecting errors during transmission.
A parity bit is an extra bit included with a binary messag
odd or even. A circuit that generates the parity bit in the transmitter is called parity generator
and a circuit that checks the parity bit in the receiver is called parity checker.
Consider a 3 bit message to be transmitted together with an even parity bit. The table
shows the truth table, for the even parity generator.
Let X, Y, Z constitute the message and are inputs to the even parity generator circuit
whose output is the parity bit P. From the truth table it can
expressed as 3 variable Exclusive-OR function, P = X Y Z.
These 4 bits (X,Y,Z, & P) are transmitted to their destination, where they are applied
to a parity checker circuit to check for possible errors in the transmission. There it is checked

implemented with EX-OR gate, C = X Y Z. P.

It is worth noting that the parity generator can also be implemented with the circuit of
this figure, if the input P is connected to Logic 0 & the output is marked with P. This is
because Z 0 = Z, causing the value of Z to pass through the gate unchanged. The advantage
of this circuit is that, the same circuit can be used for both parity generation and checking.

PROCEDURE:
1. Connections are given as per the circuit diagram using pin configurations.
2. Toggle Switches and LEDs available in the Trainer kit are used input and output
terminals respectively.
3. Switch on the supply and verify the Truth table.

22
[A] BOOLEAN FUNCTION:

[B] 3 BIT PARITY GENERATOR:

1
X 3 4
7486
6
Y 7486 P
2
5
Z

4 BIT PARITY CHECKER:

1
X 3
7486
Y
2 10
8
7486 C

4 9
Z
7486 6
P
5

23
 ERROR DETECTION WITH OCTAL PARITY BIT:

X X

Y Y

Z Z

1
3
7486

2 10
8
7486
1
3
7486 9 Error
4 detector
4 7486 6
2 6
7486
5
5 Parity Checker
Parity generator

TRUTH TABLE

[A] BOOLEAN FUNCTION

3 bit message Y
A B C D
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

24
[B] 3 BIT PARITY GENERATOR
3 bit message Parity bit
P
X Y Z P (even)
(odd)
0 0 0 0 1
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 0
4 BIT PARITY CHECKER
3 bit message Parity bit
X Y Z P C (Even) C (Odd)
0 0 0 0 0 1
0 0 0 1 1 0
0 0 1 0 1 0
0 0 1 1 0 1
0 1 0 0 1 0
0 1 0 1 0 1
0 1 1 0 0 1
0 1 1 1 1 0
1 0 0 0 1 0
1 0 0 1 0 1
1 0 1 0 0 1
1 0 1 1 1 0
1 1 0 0 0 1
1 1 0 1 1 0
1 1 1 0 1 0
1 1 1 1 0 1

ERROR DETECTION WITH OCTAL PARITY BIT

3 bit message Error detector

X Y Z P
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0

25
INFERENCE:

RESULT

26
Expt. No. Date:

CODE CONVERTER

OBJECTIVE:
To design and construct Binary to Gray and Gray to Binary Code Converter and to
verify their truth table.

ACQUISITION:
APPARATUS REQUIRED:

S.NO APPARATUS RANGE TYPE QUANTITY

1. Digital IC Trainer Kit - - 1
2. AND gate - IC 7408 1
3. OR gate - IC 7432 1
4. XOR gate - IC 7486 1
5. NOT gate - IC 7404 1
6. Patch chords - - few

THEORY
Gray code are used in applications where the normal sequence of binary numbers
generated by the hardware may produce an error or ambiguity during the transition from one
number to the next. This could have serious consequences for the machine using the
information. The Gray code eliminates this problem since only one bit changes its value
during any transition between two numbers.
Gray code is used to represent the analog data by continuous change of a shaft
position. The shaft is partitioned into segments, and each segment isassigned a number. If
the adjacent segments are made to correspond with the gray code sequence, ambiguity is
eliminated when detection is sensed in the line that separates any two segments.
-bit
code, there are 2n n-1
. Although
the minimum number of bits required to code 2n distinct quantities is n, there is no maximum
number of bits that may use in binary code.

PROCEDURE:
1. Connections are given as per the circuit diagram using pin configurations.
2. Toggle Switches and LEDs available in the Trainer kit are used input and output
terminals respectively.
3. Switch on the supply and verify the Truth table.

27
GRAY TO BINARY CONVERTER:

G3 G2 G1 G0

1
3
7486
1
2 3
7486 A
4
6 2
7486

5
10
8
7486
4
6
9 7486 B

11 5
13
7486 C

12
D

BINARY TO GRAY CONVERTER:

D C B A
1
3
7486
G0
2

4
7486 6
G1
5
10
8
7486
G2
9

G3

28
TRUTH TABLE:
GRAY TO BINARY & BINARY TO GRAY:

GRAY BINARY
G3 G2 G1 G0 D C B A
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

INFERENCE:

RESULT

29
Expt. No. Date:

ENCODER AND DECODER

OBJECTIVE:
To realize 8 x 3 Encoder and 3 x 8 Decoder using gates and to verify its truth table.

ACQUISITION:
APPARATUS REQUIRED
S.NO APPARATUS RANGE TYPE QUANTITY
1. Digital IC Trainer Kit - - 1
2. OR GATE - IC 7432 3
3. AND GATE - IC 7411 3
4. Patch chords - - 2

THEORY:
ENCODER:
An encoder is a digital circuit that performs the inverse operation of a decoder. An
encoder has 2n (or fewer) input lines and n output lines. Encoder has enable inputs to activate
encoded outputs. In encoder, the output line generates the binary code corresponding to the
input value. The decode information is presented as 2^n input producing n possible output.

DECODER:
A decoder is a multiple-input, multiple-output logic circuit which converts coded
inputs into coded outputs, where the input and output codes are different. The input code
generally has fewer bits than the output code and there is a one-to-one mapping from input
code words into output code words. In a one-to-one mapping, each input code word produces
a different output code word.
The encoder information is presented as n inputs words producing 2n possible output.
The 2 output value ranges from 0 to 2n-1. Sometimes, an n bit binary code is truncated to
n

represent fewer output value than 2n. For example, in the BCD code, the 4 bit combinations
from 0000 through 1001 represent the decimal digits 0-9 and combinations 1010 through
1111 are not used.

PROCEDURE:
1. Connections are given as per the logic diagram using pin configuration.
2. Give different combination of inputs to the gates and verify accordingly the truth table
of encoder and decoder.

30
 ENCODER

Do D1 D2 D3 D4 D5 D6 D7

1
3
7432 13
2 11
4 7432 X = D4+ D5+ D6+ D7
6 12
7432
5
1
3
7432 13
11
2 7432 Y = D2+ D3+ D6+ D7
4 6 12
7432
5

1
3
7432 13
2 11
4 7432 Z = D1+ D3+ D5+ D7
6 12
7432
5

31
DECODER

X X Y Y Z Z
7404 7404 7404

7411 Do

7411 D1

7411 D2

7411 D3

7411 D4

7411 D5

7411 D6

7411 D7

32
TRUTH TABLE
ENCODER

INPUT OUTPUT
D0 D1 D2 D3 D4 D5 D6 D7 X Y Z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

DECODER
INPUT OUTPUT
X Y Z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0SS 1

INFERENCE:

RESULT:

33
Expt. No. Date:

MULTIPLEXER AND DEMULTIPLEXER

OBJECTIVE:
To realize 4:1 MUX and 1:4 DEMUX using gates and to verify its truth table.

ACQUISITION:
APPARATUS REQUIRED

S.NO APPARATUS RANGE TYPE QUANTITY

1. Digital IC Trainer Kit - - 1
2. OR GATE - IC 7432 1
3. NOR GATE - IC 7404 1
4. AND GATE - IC 7411 2
5. Patch cord - - few

THEORY
MULTIPLEXER:
A digital multiplexer is a combinational circuit that selects binary information from
one of the many input lines and directs it to a single output line. The selection of a particular
input line is controlled by a set of selection lines. Normally, there are 2n input lines and n
selection lines whose bit combinations determine which input is selected.
A 4x1 multiplexer has 4 input lines I0, I1, I2 & I3 each applied as one input of a AND
gate. Selection lines S0, S1 are decoded to select particular AND gate. Consider S0S1=10.
The AND gate associated with input I2 has two of its inputs equal to 1 and the third input
connected to I2. The other 3 AND gates have at least one input equal to 0, which makes their
output equal to zero. The OR gate output is now equal to I2, thus providing a path from the
selected input to the output.

DEMULTIPLEXER:
A demultiplexer is a circuit that receives information on a single line and transmits the
information on anyone of 2n possible output lines. The selection of a specific output line is
controlled by the bit values of n selection lines.
A 1x4 demultiplexer has only one input, which is applied as one input of AND gate.
Selection lines S0, S1 are decoded to select a particular output. Consider S0S1=10, the data
is transferred on D2 line and all other output will be zero.

PROCEDURE:
1. Connections are given as per logic diagram using the pin details of the gates.
2. Connect the data, select and enable inputs to the toggle switches and outputs to the
LEDs.
3. Switch on the trainer and verify the truth table.

34
MULTIPLEXER:

I0
I1 4:1 MUX Y
I2
I3

S0 S1

DEMULTIPLEXER:

Y0
1:4 DEMUX Y1
D
Y2
Y3

S0 S1

35
 MULTIPLEXER:

So 7404 So S1 7404 S1 1

Io

7411
1
7432 3

I1 2

7411
9
7432 8
Y
I2 10

7411 33
4
7432 6

5
I3

7411

36
DEMULTIPLEXER:

So 7404 So S1 7404 S1 D

1
2 12
7411 Y0
13

3
4 6
7411 Y1
5

11
10 8
7411 Y2
9

1
2 12
7411 Y3
13

37
TRUTH TABLE
MULTIPLEXER:
So S1 Y
0 0 Io
0 1 I1
1 0 I2
1 1 I3
DEMULTIPLEXER

So S1 D Yo Y1 Y2 Y3
X X 0 X X X X
0 0 1 1 0 0 0
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 1

INFERENCE

RESULT

38
Expt. No. Date:

SYNCHRONOUS COUNTERS

OBJECTIVE:
To design and construct the synchronous counter and to verify its truth table.

ACQUISITION:
APPARATUS REQUIRED:

S.NO APPARATUS RANGE TYPE QUANTITY

1. Digital IC Trainer Kit - - 1
2. Patch chords - - few

THEORY:
SYNCHRONOUS COUNTER:
Synchronous Counters are distinguished from ripple counter in that clock pulses are
applied to the CP inputs of all flip-flops. The common pulse triggers all the flip-flops
simultaneously, rather than one at a time in succession as in a ripple counter. The decision
whether a flip-flop is to be complemented are not is determined from the values of J & K
inputs at the time of the pulse. If J=K=0, the flip-flop remains unchanged. If J=K=1, the flip-
flop complements.

BINARY COUNTERS:
Synchronous binary counters have a regular pattern and can easily be constructed with
complementing flip-flops and gates. The regular pattern can be clearly seen from the 4 bit
counter depicted in the diagram. The CP terminals of all flip-flops are connected to a
common clock pulse source. The first stage A has its J & K equal to 1 if the counter is
enabled. The other J and K inputs are equal to 1 if all previous low order bits are equal to 1
and the count is enabled. The chain of AND gates generates the required logic for the J & K
inputs in each stage. The counter can be extended to any number of stages, with each stage
having an additional flip-flop and an AND gate that gives an output of 1 if all previous flip-

Note that the flip-flops trigger on the negative edge of the pulse. This is not essential
here as it was with the ripple counter. The counter should also be triggered on the positive
edge of the pulse.

PROCEDURE:
1. Connections are given as per circuit diagram and pin configuration.
2. Clock pulses are applied one by one at the clock input and the output is observed.
3. Truth Table is verified.

39
 4 BIT SYNCHRONOUS BINARY COUNTER

7411 7411
QA QB QA QB QC

Logic 1
J QA J QB J QC J QD
IC 7476 IC 7476 IC 7476 IC 7476
FF-A FF-B FF-C FF-D
K K K K
330 330
330

TIMING DIAGRAM:

CLK

QD

QC

QB

QA

40
TRUTH TABLE:
4 BIT SYNCHRONOUS BINARY COUNTER
CLK QA QB QC QD
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
16 0 0 0 0
17 0 0 0 1

INFERENCE:

RESULT:

41
Expt. No. Date:

ASYNCHRONOUS COUNTERS

OBJECTIVE:
To design and construct the asynchronous counter and to verify its truth table.

ACQUISITION:
APPARATUS REQUIRED:

S.NO APPARATUS RANGE TYPE QUANTITY

1. Digital IC Trainer Kit - - 1
2. Patch chords - - few

THEORY:
BINARY RIPPLE COUNTER (ASYNCHRONOUS):
A binary ripple counter consists of a series connection of complementing flip-flops,
with the output of each flip-flop connected to the CP input of the next higher order flip-flop.
The flip-flop holding the LSB receives the incoming count pulses. The input 1 is given to all
JK flip-flop. The small circle in the CP input indicates that the flip-flop complements during
a negative going transition or when the output to which it is connected goes from 1 to 0.
Every time A1 goes from 1 to 0, it complements A2. Every time A2 goes from 1 to 0, it
complements A3 & so on. For example, take the transition from count 0111 to 1000. The
arrows in the table emphasize the transitions in this case. A1 is complemented with the count
pulse. Since A1 goes from 1 to 0, it triggers A2 and complements it. As a result, A2 goes
from 1 to 0, which in turn complements A3. A3 now goes from 1 to 0, which complements
A4. The output transition of A4, if connected to a next stage, will not trigger the next flip-flop
since it goes from 0 to1. The flip-flops change one at a time in rapid succession, and the
signal propagates through the counter in a ripple fashion. Ripple counters are sometimes
called as asynchronous counters.

PROCEDURE:
1. Connections are given as per circuit diagram and pin configuration.
2. Clock pulses are applied one by one at the clock input and the output is observed.
3. Truth Table is verified.

42
 4 BIT ASYNCHRONOUS COUNTER

A1 A2 A3 AD

J QA J QB J QC J QD
IC 7476 IC 7476 IC 7476 IC 7476
FF-A FF-B FF-C FF-D
Logic 1
K K K K

Count
pulse

43
TRUTH TABLE:
4 BIT SYNCHRONOUS BINARY COUNTER
CLK QA QB QC QD
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
16 0 0 0 0
17 0 0 0 1

INFERENCE:

RESULT

44
Expt. No. Date:

SHIFT REGISTERS

OBJECTIVE:
To implement different types of shift registers like Serial In Serial Out (SISO), Serial
In Parallel Out (SIPO), Parallel In Serial Out (PISO), Parallel In Parallel Out (PIPO) using D
Flip flops and verify their output.

ACQUISITION:
APPARATUS REQUIRED

S.NO APPARATUS RANGE TYPE QUANTITY

1. Digital IC Trainer Kit - - 1
2. Patch chords - - few

THEORY:
SHIFT REGISTER:
A register is a group of binary cells which holds binary information. Each flip flop is
a binary cell capable of storing one bit of information. A register capable of shifting its binary
information either to right or the left is called a shift register.

[a] SISO (SERIAL-IN to SERIAL-OUT):

a left or right direction under clock control.

[b] SIPO (SERIAL-IN to PARALLEL-OUT):

The register is loaded with serial data, one bit at a time, with the stored data being
available at the output in parallel form.

[c] PIPO (PARALLEL-IN to PARALLEL-OUT):

The parallel data is loaded simultaneously into the register, and transferred together
to their respective outputs by the same clock pulse.

[d] PISO (PARALLEL-IN to SERIAL-OUT):

The parallel data is loaded into the register simultaneously and is shifted out of the
register serially one bit at a time under clock control.

PROCEDURE:
1. Connections are given as per circuit diagram.
2. For various combinations of input, the outputs are verified.

45
 [1] SERIAL IN SERIAL OUT SHIFT REGISTER:
+Vcc
14
+Vcc
CLR
1 13 14 1 13 14

5 12 9 2 5 12 9
Data in
A B C D
3 11 3
IC 7474 IC 7474 IC 7474 IC 7474 11

4 10
10 4 330
PRE

CLK

TIMING DIAGRAM

CLK

DA

QD

46
 [2] PARALLEL IN PARALLEL OUT SHIFT REGISTER:

A B +Vcc C D +Vcc

QA QB QC QD
2 12 2 12
A B C D
3 5 11 9 3 5 11 9
IC 7474 IC 7474 IC 7474 IC 7474

330 330 330 330

CLK

TIMING DIAGRAM:

CLK

QD/D

QC/C

Qb/b

Q A/A

47
 [3] SERIES IN PARALLEL OUT SHIFT REGISTER:

330 330 330 330

A 2 5 12 9 2 5 12 9
QA QB QC QD
A B C D
3 11 3 11

IC 7474 IC 7474 IC 7474 IC 7474

14 14
CLK

+Vcc

TIMING DIAGRAM:

CP

QA

QB

QC

QD

48
 [4] PARALLEL IN SERIAL OUT SHIFT REGISTER:
Shift load

DB DC DD

DA

DA QA DB QB DC QC DD QD

A B C D

IC 7474 IC 7474 IC 7474 IC 7474

CLK 330

+Vcc

TIMING DIAGRAM:

CLK

DA

DB

DC

DD

QD

Shift
load
49
[1] SERIAL IN SERIAL OUT SHIFT REGISTER
SEQUENCE TABLE

CP QD QC QB QA
1 1 0 0 0
1 1 1 0 0
1 1 1 1 0
1 1 1 1 1
TRUTH TABLE

A B C D QA QB QC QD
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 0
0 1 0 0 0 1 0 0
1 0 0 0 1 0 0 0

[2] PARALLEL IN PARALLEL OUT SHIFT REGISTER:

TRUTH TABLE

CP A B C D QA QB QC QD
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 0
0 1 0 0 0 1 0 0
1 0 0 0 1 0 0 0

[3] SERIES IN PARALLEL OUT SHIFT REGISTER

TRUTH TABLE

A B C D QA QB QC QD
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 0
0 1 0 0 0 1 0 0
1 0 0 0 1 0 0 0

[4] PARALLEL IN SERIES OUT SHIFT REGISTER

TRUTH TABLE

CP A B C D QA QB QC QD
1 0 0 0 1 0 0 0 1
1 0 0 1 0 0 0 1 0
1 0 1 0 0 0 1 0 0
1 1 0 0 0 1 0 0 0

50
INFERENCE

RESULT

51
Expt. No. Date:

DESIGN AND IMPLEMENTATION OF COMBINATIONAL CIRCUIT

USING VHDL

OBJECTIVE:
To design with Programmable Logic Devices using Xilinx and Implement a simple
Combinational Circuit.

PROCEDURE:
Select Start Programs Xilinx ISE 9.2 Project Navigator.
Create a New Project
Create an HDL Source and then create a VHDL source and type the file name and click
next.
In New Source Wizard-Define module window type the port name and define the port
and click next and next till the finish wizard appears.
Type the VHDL program in editor.
In the left panel select Synthesis/Implementation in the sources and in process menu
select synthesize-XST.
After successfully synthesized the project, select right click on program file and select
add new sources in drop down menu.
Select Test Bench Waveform in source type and type test bench waveform name in
filename and then click next and next till the finish wizard appears.
A window will appear for prompting to ask for timing and clock wizard. Just give the
proper timing signal for timing signal for sequential circuit and click finish.
Select for Behavioural Simulation in sources list and in processes tab select Simulate
Behavioural simulation
Simulation window for your VHDL code and test bench appears.

52
HALF ADDER
LOGIC DIAGRAM

TRUTH TABLE:

PROGRAM:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity halfadder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end halfadder;
architecture Behavioral of halfadder is
begin
s <= a xor b;
c <= a and b;
end Behavioral;

53
OUTPUT:

INFERENCE:

RESULT:

54