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|A| is the capacity of the set A. If one can find several groups of Tab. 1. The STT of the initial FSM from the example
such transitions, they are successively considered.
am X(am , as) as Y(am, as)
3. For the recurrent group of transitions P(ai,aj), one determines
the set Z(ai,aj) of the transition conditions from the state ai to aj. a1 1-- a2 1-
4. On the basis of the set Z(ai,aj) one forms the Boolean function a1 0-- a3 -0
B(ai,aj) that expresses the transition condition from ai to aj. To a2 -1- a3 -0
do it, all the elements of Z(ai,aj) are combined via a logic OR
a2 -00 a4 01
operation: B(ai,aj) = z1 + z2 + … + zK, where the sign “+”
a2 -01 a5 10
denotes the logical OR operator (zk Z(ai,aj), K = |Z(ai, aj)|).
5. The shortest (containing the smallest number of terms) a3 -1- a2 1-
disjunctive normal form (DNF) of the function B(ai,aj) is a3 -00 a4 01
determined by means of one of the known methods, e.g. [11]. a3 -01 a5 10
6. For the shortest DNF of the function B(ai,aj), the set Z*(ai,aj) of
a4 --- a5 11
its terms is found.
7. If |Z*(ai,aj)| < |Z(ai,aj)|, then the transitions corresponding to the a5 --- a1 00
conditions of the set Z(ai,aj) are excluded from the group of
transitions P(ai,aj) and replaced by the transitions corresponding Performing the algorithm [10] of finding the set D of the state
to the conditions of the set Z*(ai,aj). The output vectors that are pairs which meet the conditions for merging for the states a2 and
formed at new transitions, are determined by combining the a3, we have Z(a2) = {x2, x 2 x3 , x2 x3 } and Z(a3) = {x2, x 2 x3 ,
output vectors at the transitions of the set P(ai,aj).
x2 x3 }. For the transition conditions X(a2,a3) = x2 and X(a3,a2) =
8. Steps 3-7 of this algorithm are performed for each group of the
transitions found at Step 2. x2, we have that the transition conditions are equal and the formed
9. Steps 1-8 of this algorithm are performed for all states of the set A. output vectors are not orthogonal (Y(a2,a3) = “-0” and Y(a3,a2) =
10. End. “1-”). The merging conditions are satisfied for states a2 and a3 in
At minimization of the number of FSM transitions one can the case to generate a wait state.
arrive at a situation when certain input variables have no impact Verification of the remaining transition conditions for the sets
on the transition conditions. Suppose, for instance, that one Z (a2) and Z (a3) also admits merging the states a2 and a3. Thus,
transition from a state a1 under condition x1 leads to a state a2 and the pair (a2, a3) can be merged. Table 2 represents the STT after
another transition from a1 under condition x1 leads to a state a3 merging a2 and a3. There are no more pairs of the states in the set
of FSM internal states such that the merging conditions are met.
and the variable x1 does not meet anywhere else in transition Algorithm 2 allows us to minimize the number of transitions from
conditions of the FSM. Suppose that after the states a2 and a3 have the state a1 (by one), and in addition the transition from the state a1
been merged, the transition from the state a1 to the state a2_3 to the state a2_3 becomes unconditional. At transition from the
becomes unconditional, i.e. it does not depend on the values of state a1 the output vector “10” is formed, it is the result of
input variables. The latter means that the variable x1 has no impact combining the output vectors “1-“ and “-0”.
on any FSM transition and therefore it is redundant.
Tab. 2. The STT of the FSM after merging of the states a2 and a3
Algorithm 3 (minimization of the number of FSM input
variables) am X(am , as) as Y(am, as)
a1 1-- a2_3 1-
1. Consider certain FSM input variable xi (xi X). a1 0-- a2_3 -0
2. Check whether the variable xi is in the column X(am,as) of the
a2_3 -1- a2_3 10
STT (in direct or inversed form).
3. If the column X(am,as) of the STT does not contain xi, than the a2_3 -00 a4 01
input variable xi is excluded from set X of FSM input variables. a2_3 -01 a5 10
Put X := X\{xi}. a4 --- a5 11
4. Steps 1-3 of this algorithm are performed for all FSM input
a5 --- a1 00
variables of the set X.
5. End.
Algorithm 3 excludes the variable x1 from the set X. Fig. 2 and
Example Table 3 show the FSM state diagram and FSM STT after
minimization, respectively.
Suppose we need to minimize the FSM given by the state
diagram in Fig. 1, where the transition conditions and the formed
-1-/10
output vectors are assigned to the graph arcs (via a slash). a4
1
-00/0
---/10 ---/11
a1 a2_3 -01/1 0
a2 -00/01
-0
a4
1- -/
1 - 1/ 1
0
a5
---/11
/-0
a1
-1 -
0- - 01 ---/00
-
/ -1 /
-1 -/1
0
-0
-01/10 Fig. 2. The state diagram of the FSM after minimization
a3 a5
---/00
The FSM parameters are now L = 2, N = 2, M = 4, R = 2, and
Q = 6. Thus, by means of the proposed method of FSM
Fig. 1. State diagram of the initial FSM from an example
minimization, we have not only reduced the number of internal
states but also diminished the number of transitions from 10 to 6,
Table 1 represents the FSM STT. The initial FSM has and the number of input variables has been decreased by one.
parameters L = 3, N = 2, M = 5, R = 3, and Q = 10, where Q is the
number of FSM transitions.
Measurement Automation Monitoring, May 2016, no. 05, vol. 62, ISSN 2450-2855 181
The analysis of Table 4 shows that the application of the Valery SALAUYOU, DSc, PhD, eng.
proposed method allows reducing the number of internal states of
the initial FSM on the average by 1.22 times, and on occasion Valery Salauyou received the PhD and DSc degrees in
computer science from the Belarusian State University
(example train11) by 2.75 times. Similarly, the average reduction Informatics and Radioelectronics, in 1986 and 2003,
in the number of the FSM transitions makes 1.32 times, and on respectively. From 1992 he is Associate Professor at the
occasion (example lion9) 2.27 times. Besides, the application of Bialystok University of Technology. His research
the algorithm 6 led to reduction in the number of input variables interests are in the area of VLSI design, with emphasis
on logic synthesis, Embedded Systems, architectures of
from 11 to 8 in example s208 and from 19 to 8 in example s420. programmable logic (CPLD/FPGA/SoC), and
The comparison of the proposed method with the program optimization of FSMs.
STAMINA shows that after applying the proposed method the
number of FSM states is the same as after applying the program e-mail: v.salauyou@pb.edu.pl
STAMINA. However, the offered method, unlike the program
STAMINA, allows reducing significantly the number of FSM
transitions, on the average by 1.55 times and on occasion
(examples bbsse and sse) by 3.92 times.