University of Waterloo

Department of Electrical and Computer Engineering

ECE324/325 Microprocessor Systems & Interfacing

Laboratory Manual

Bill Bishop, Jeff Dungen, Rob Gorbet, Carol Hulls, Wayne Loucks

June 26, 2002

Copyright
c 2001 by Bill Bishop, Jeff Dungen, Rob Gorbet, Carol Hulls, Wayne Loucks, and the University of
Waterloo. All rights reserved.
ii
Contents

1 General Course Information 1

1.0.1 ECE324/325 Course Staff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Marking Scheme and Due Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Course Resources & Reference Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 ECE324 Course Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Laboratory Guide 11
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Operational Specifics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3 The ALTERA Excalibur Development System 15

3.1 Excalibur Development Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Development Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Designing for the Excalibur Development System . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 Other Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4 Lab 0 19
4.1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2 Lab Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3 Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4 Part I: Development of a Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5 Part II: Building a NIOS System Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.6 Part III: Programming and Testing the Excalibur Development Board . . . . . . . . . . . . . . . 31

5 Lab 1 35
5.1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2 Lab Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3 Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

iii
iv CONTENTS

5.4 Part I: Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.4.1 Getting Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.4.2 Generating the Nios System Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.4.3 Compiling the VHDL Source for the SSDI . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.4.4 Completing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.4.5 Compiling the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.4.6 Programming the APEX Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.5 Using the Provided Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.6 Part II: Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.6.1 Getting Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.6.2 Desired Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.6.3 Breaking Down the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.6.4 Compiling & Downloading to the Excalibur Development Board . . . . . . . . . . . . . . 42
5.7 Testing, Debugging, and Going Further . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.8 Deliverables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.8.1 Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.8.2 Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6 Lab 2 47
6.1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.2 Lab Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.3 Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.4 Part I: Development of a Hamming Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.5 Part II: Developing and Testing the Lab 2 System . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.6 Enhancing the System (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.7 Deliverables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.7.1 Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.7.2 Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

7 Lab 3 57
7.1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.2 Lab Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.3 Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7.4 Part I: Initial Microcontroller System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.4.1 NIOS System Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
CONTENTS v

7.4.2 Seven Segment Display Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.4.3 Completing the Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.4.4 Button and Display Software Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.5 Part II - ADC Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.5.1 SPI Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.5.2 ADC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.5.3 Joystick Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.5.4 Desired Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.6 Part III - The Complete System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
7.6.1 Option 1: Music Scale Player . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
7.6.2 Option 2: Motor Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
7.6.3 Desired Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
7.6.4 Intermediate Design Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.7 Testing, Debugging, and Going Further . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7.8 Deliverables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7.8.1 Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7.8.2 Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.9 Daughterboard Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

A NIOS Tutorial for Lab 0 73

vi CONTENTS
List of Figures

4.1 Full Adder Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2 4-Bit Ripple-Carry Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3 Hardware Design Flow for Programmable Logic Devices . . . . . . . . . . . . . . . . . . . . . . . 23
4.4 VHDL Design of a Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.5 Vector Waveform File to Simulate a Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.6 Functional Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.7 Timing Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.8 The NIOS System Module block diagram. Each block represents a component of the complete
system module. External connections have been left off. Blocks are arranged so that their locations
correspond for the most part with the locations of the corresponding pins on the Quartus II-
generated symbol (see Figure 4.9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.9 The NIOS System Module symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.10 The complete NIOS tutorial system. The portion in the dashed line represents the NIOS System
Module; the memories are external to the System Module. . . . . . . . . . . . . . . . . . . . . . 34

5.1 Block Diagram of Lab 1 Hardware System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.2 Wiring diagram for Lab 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.1 The Lab 2 Communication System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.2 Symbols and PORT Declarations for Hamming Encoder (top) and Noise Generator (bottom) . . . 50
6.3 Hamming Decoder Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.4 Sample Display Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7.1 Lab 3 Complete System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.2 Seven Segment Display Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.3 Daughterboard Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7.4 Seven Segment Display Decoder Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.5 SPI communication with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.6 Audio Output for Lab 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

vii
viii LIST OF FIGURES

7.7 Major music scales used in Lab 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7.8 Dip Switch Effect on Motor Movement for Lab 3 . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7.9 Daughterboard Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
List of Tables

1.1 ECE324/325 Marking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 ECE324 Lecture Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.1 Properties for Lab 1 Nios Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.2 Seven Segment Display Interface (SSDI) Functionality . . . . . . . . . . . . . . . . . . . . . . . . 45

6.1 Lab 2 NIOS 32-Bit Processor Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.1 Properties for Lab 3 NIOS Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

ix
x LIST OF TABLES
Chapter 7

Lab 3

7.1 Purpose

As you may have been aware, Spring 2002 is only the second term for these labs. This brings the exciting
opportunity to work with a current leading edge system and set of tools. The tools provide a great deal of
flexibility in terms of how your system may be implemented. Also, Lab 3 involves a significantly more challenging
problem to be solved in comparison to previous labs. While this is an excellent opportunity to further develop your
engineering design skills, particularly in the area of embedded systems, the difficulty of the lab combined with its
newness, does mean that you may encounter unexpected difficulties while working on the lab. It is important to
remember as you work on the lab that the goal of the lab is not necessarily to have a perfectly working system,
but to learn about the process of designing, implementing, and testing an embedded system that uses at least
one analog interface.
The purpose of Lab 3 is to familiarize students with embedded system design, implementation and testing. Upon
completion of this lab, you will have had an opportunity to do the following:

1. design and implement hardware interfaces within a Nios system;

2. interface a microcontroller with an analog joystick and an analog output device;

3. design, simulate and verify the operation of a VHDL core;

4. control and operate devices using a Serial Peripheral Interface (SPI);

5. use Analog to Digital Converters (ADC), Digital to Analog Converters (DAC) and opto-isolators;

6. design and implement C/C++ device drivers; and

7. design and program C/C++ software to operate an embedded system;

7.2 Lab Outline

In this lab you will build a complete embedded system. A block diagram of the system is shown in Figure 7.1.
The system uses the analog output of a joystick to operate an audio speaker or to operate a small DC motor
(Figure 7.1 shows both).

57
58 CHAPTER 7. LAB 3

Figure 7.1: Lab 3 Complete System Diagram

Figure 7.2: Seven Segment Display Outputs

7.2. LAB OUTLINE 59

The system can operate in three different modes. The system enters test mode when push button one is pressed
and released. In test mode, the seven segment display will show the current joystick position as a cardinal compass
point (North, Southwest, etc.). Figure 7.2 shows the display output for the cardinal points.
When push button two is pressed and released, the system should enter music mode. In this mode, the joystick
position and dip switch values will be used to determine the output to the audio speaker. The current position
of the joystick will be shown on the seven segment display as a music note, as seen in Figure 7.2.
Alternatively, when push button three is pressed and released, the system should enter motor mode. In this mode,
the joystick position and dip switch values will be used to determine the output to the DC motor. The current
position of the joystick will be shown on the seven segment display as a either a motor speed or motor command,
as seen in Figure 7.2.
Your system design must be able to operate in test mode and one of either music or motor modes. Each design
uses the following components:

• a joystick that has two analog voltage outputs;

1
• a National Semiconductor ADC08038 analog to digital converter;
2
• a Maxim MAX529 digital to analog converter;
3
• TIL193 opto-isolators;
• one of: an audio speaker or a DC motor;
• a microcontroller system that includes a NIOS processor, timer(s), parallel I/O port(s), RS-232 UART to
communicate with the PC, a master SPI port, and custom interfaces implemented using VHDL;
• Excalibur board components including the dip switches, seven segment display, and push buttons.

The ADC, DAC, and opto-isolators are located on the daughterboard which is connected to the Excalibur devel-
opment board. Figure 7.3 shows a block diagram of the daughterboard. Communication between the Excalibur
board and the ADC and DAC on the daughterboard takes place using a Serial Peripheral Interface (SPI) with the
NIOS assuming mastership. The joystick is connected to the daughterboard via a standard PC joystick connector.
The speaker and motor circuits are connected to the daughterboard via electrical terminals.
The lab will be divided into 3 phases of development as follows:

Part I • implementation of the NIOS system

• implementation of a VHDL seven segment display interface that will display the cardinal compass
points, the musical scale, and the motor value
• modification of functions from lab 1 and 2 to implement device drivers to interface to the dip switches
and for the push buttons
Part II • implementation of a device driver to interface to a master SPI port
• implementation of an interface to the joystick
• implementation of a system that displays the joystick position in terms of the cardinal compass points
on the seven segment display
• implementation of a complete system for test mode
Part III • implementation of a device driver to interface to either an audio speaker or a small DC motor
• implementation of the complete embedded system, including test mode and one of music or motor
modes
1 www.pads.uwaterloo.ca/ece324/protected/labs/lab3/adc.pdf
2 www.pads.uwaterloo.ca/ece324/protected/labs/lab3/dac.pdf
3 www.pads.uwaterloo.ca/ece324/protected/lab3/opto isolator.pdf
60 CHAPTER 7. LAB 3

Figure 7.3: Daughterboard Block Diagram

7.3 Preparation
Prior to attempting this lab, you should be familiar with the Quartus II software and VHDL. It is assumed that
you have successfully completed Labs 0 through 2 before attempting this lab.
It is highly recommended that you review the Altera documentation on the course website, particularly on the
following topics (although only the first two should be new to you at this point):

• the NIOS SPI Peripheral,

• the operation of the seven-segment display,
• the NIOS Timer Peripheral,
• the NIOS Parallel I/O Port (PIO), and
• interrupts in the NIOS processor.

Note that the operation of the NIOS SPI does not completely conform to the standard for SPI as defined by
Motorola.
Examples of VHDL code to drive the seven segment display are given by ssdi.vhd from Lab 1 and in the VHDL
tutorial notes.
It is also highly recommended that you review the following specification sheets included on the course webpage.
Of particular importance are the command codes for communicating with the DAC and ADC.

• DAC - MAX529, www.pads.uwaterloo.ca/ece324/protected/labs/lab3/dac.pdf

• ADC - 08038, www.pads.uwaterloo.ca/ece324/protected/labs/lab3/adc.pdf
7.4. PART I: INITIAL MICROCONTROLLER SYSTEM 61

Table 7.1: Properties for Lab 3 NIOS Peripherals

peripheral properties
boot monitor rom Type: ROM, Width: 32 bits, Size: 1K, Contents:
GERMS Monitor
ext ram no extra properties
ext flash use existing bus: ext ram bus
uart 0 115.2kbps, N-8-2
spi master Master, 16-bit, MSB first, 1.0 MHz, 3 Slave, 1.0us
delay, Polarity 1, Phase 1

• opto-isolator - TIL193, www.pads.uwaterloo.ca/ece324/protected/lab3/opto isolator.pdf

The operation of ADCs and DACs is described in the following references:

• Sections 3.7 and 3.8 of Digital Control System Analysis and Design by C. Philips and H. Nagle

• Sections 11.4 and 11.5 of Embedded Microcomputer Systems: Real Time Interfacing by J. W. Valvano

The operation of LEDs and seven segment displays is discussed in Section 8.2 of Valvano. In addition, students
with weak programming skills may benefit from reading Chapter 2 of Valvano.
Finally, it is important that you review the course notes on the following topics:

• Serial Peripheral Interface (SPI),

• Analog to Digital Conversion (ADC), and

• Digital to Analog Conversion (DAC).

Prior to doing any development, create a project directory for this lab on your user account on Nexus. Then
download the lab3 pin assign.tcl script from the course webpage to this directory. The TCL script assumes
by default that your project is named lab3 and that your highest level entity is also named lab3.
It is very important for this lab to have your hardware and software designs completed, and your software
coded, BEFORE you come to your scheduled lab period.

7.4 Part I: Initial Microcontroller System

In Part I, you will build a NIOS system module using the Quartus II MegaFunction Wizard, according to specifica-
tion. You will also create a seven segment display decoder (SSDD) block using VHDL. You will then instantiate
the NIOS system module and the SSDD, and wire the design. Finally, you will compile the design and program
it into the APEX device on the Excalibur Development Board.

7.4.1 NIOS System Core

Within your lab3 project, from the Tools menu, select MegaWizard Plug-In Manager. Follow the steps to
configure your NIOS 32-bit processor. Your NIOS 32-bit processor will contain the basic components shown in
Table 7.1, plus any other components such as hardware timers, parallel I/O ports, SPI, etc. that will be needed
to implement your design for Part I. Components not listed in this table should be configured as required by your
62 CHAPTER 7. LAB 3

Figure 7.4: Seven Segment Display Decoder Block

overall system design. Note: Choose your interrupt priorities wisely for your NIOS design. Remember that the
lower the IRQ, the higher the priority.
The LEDs are not required in this lab. They are assigned to pins so as to be available for debugging purposes or
for added functionality. Similarly, the from opto pins are not required in this lab. They are included for future
project enhancements. You may safely leave out any pins that you do not use.
Once the peripherals are added to the Nios system module, complete the NIOS system module by:

• setting main program and data memory to reside in the ext ram,

• setting communications to use uart 0,

• choosing a GERMS monitor boot message,

• setting the reset location to 0x0 of the boot monitor rom,

• locating the interrupt vector table at offset 0x3FF00 of the ext ram,

• specifying the target device as being in the APEX20KE family.

7.4.2 Seven Segment Display Decoder

Open a new VHDL file called ssdd.vhd and add it to your project. Create an entity called ssdd which results
in a block resembling that of Figure 7.4. The mode lines are used to select test mode, music mode, or motor
mode. The four data lines are used to determine what to output to the seven segment display in each mode. The
output lines are connected to the seven segment display. Your SSDD block should allow you to display all of the
patterns shown in Figure 7.2.
Once you complete your design, it is a good idea to simulate it to verify that it operates as intended. Remember
to set the compilation focus to ssdd.vhd and compile before simulating. You may ask a TA to check over your
simulation results, as you did in lab 2, to confirm that your SSDD is functioning correctly. When you are confident
that your SSDD functions correctly, you may generate a symbol for the SSDD by selecting Tools/Create symbol
for current file. The SSDD will then appear in the symbol library, under the project folder.

7.4.3 Completing the Hardware Design

Combine your NIOS system module, your SSDD block and any other necessary symbols. Wire and name your
pins.
In order match the tcl script, the following names must be used.

• Project Name: lab3

7.5. PART II - ADC INTERFACING 63

• Top Entity Name: lab3

• For Data bus, Address bus, and related control signals use the following signal names: ext addr ext data
ext be n SRAM Lo cs n SRAM Hi cs n SRAM Lo oe n SRAM Lo we n FLASH we n FLASH ce n FLASH a16
JP12 sel n

• For PIOs use the following signal names: dip switch from opto to opto seven segn pb miso mosi sclk ssn
led

• For UARTs use the following signal names: rxd txd rxd debug txd debug

You are provided with a script, lab3 pin assign.tcl on the course website, which will do the pin assignments for
you. When you are confident that your pins are labelled as listed above, run this script from the Tcl Console. Verify
that the pin assignment has been made correctly by examining the Compiler Settings (found in the Processing
pull-down menu). Also ensure that the target device is set to EP20K200EFC484-2X and explicitly set the unused
pins to tri-stated inputs.
When this is done, set the compilation focus to lab3.bdf and compile the design. Remember to investigate all
compiler warnings as they may indicate problems with your wiring, pin names and pin assignments. Once the
compilation is complete, you may program the hardware into the APEX device.

7.4.4 Button and Display Software Design

Write a function that given an input code and mode will cause the seven segment display to show the desired
pattern. You will use this function in your design for parts 2 and 3 of the lab.
Modify, if necessary, your code from Labs 1 and 2 to implement device drivers to interface to the dip switch and
to the push buttons. Your push button device driver must handle interrupts.
Combine your display software with your button and switch software to implement the following functionality:

• When push button 1 is pressed and released, read the dip switch for a value, and based on this value output
one of the test patterns on the seven segment display.

• Similarly, when push button 2 is pressed and released, the music note pattern corresponding to the dip
switch value is displayed.

• The same functionality is implemented for push button 3, except a motor pattern is displayed.

Good software engineering will save you time and effort in this lab. For example, use constant declarations for
all constants - in C with a #define statement, in C++ with a type const NAME = value; statement. Use
a header file (.h) for your software. In it, include your constant declarations, enumerated type definitions, and
struct or class definitions. This will greatly simplify debugging your design. Design, implement, and test your
software as separate modules. Write functions that can be used for all phases of the lab. As you design your
software, think about how you are going to test it. You may find functions in the C/C++ math library (<math.h>)
useful.

7.5 Part II - ADC Interfacing

The second part of the lab focuses on interfacing to the ADC in order to read the output voltage of the joystick.
The ADC, DAC and opto-isolators are located on a daughterboard that is to be connected to the Excalibur board.
64 CHAPTER 7. LAB 3

7.5.1 SPI Software

Your software will need to include a device driver to interface with the SPI. The device driver includes functions
to send and receive data to and from the ADC and DAC. The ADC and DAC are SPI-compatible devices.
The NIOS SPI ports do not implement the standard as defined by Motorola that was discussed in class. Some of
the important differences are:

• A programmable data size of up to 16 bits is available rather than a fixed size of 8 bits.

• A port is defined as either a master or a slave rather than allowing this to be configurable.

• For a master, a single slave select pin which can be configured as input or output has been replaced by 1-16
output only slave select lines. Rather than using the individual lines to select a slave as described in the
Altera documentation, the daughterboard uses the three least significant bits of the slave select lines as an
address to be decoded. (See Figure 7.3) The DAC is selected by setting the lines to 101, and the ADC is
selected by setting these lines to 110.

• Buffering of the shift register is provided for both write and read by the txdata and rxdata registers.

• A receiver overrun error will occur if you transmit data and do not explicitly read the rxdata register.

• The status of the transfer can be monitored by examining the bits in the status register. These status bits
are similar to those provided by the NIOS UART.

Note: The NIOS SPI documentation describes two functions nr spi rxchar and nr spi txchar to read and
write to a SPI port. Unfortunately there appears to be problems with the implementations of these two functions.
The header file generated as part of the SDK refers to functions spi rxchar and spi txchar. The teaching
team has found that modifying these lines in the header files to reflect the actual routine names will allow your
code to compile. However, the functions still do not seem to work. Thus it is recommended that you write your
own drivers to operate the SPI master port. Although we do not encourage you to spend time trying to debug
the Altera code, should you get the native SPI transfer functions to work, please let us know.

7.5.2 ADC Operation

The ADC is a successive approximation ADC. The CS for the ADC is generated by the output of the daughterboard
decoder. Conversion starts when a start bit followed by configuration information (including which of the 8 single-
ended channels to be used) is serially sent to the ADC. The start bit is automatically sent as part of the serial
transmission.
Figure 7.5 shows the format of the 16-bits of data that is sent and received from the ADC. Bits 15 to 12 of the
transmit data select the channel of the ADC. The rest of the bits are “don’t care” bits. Refer to the ADC data
sheet for additional detail. The ADC is to be operated in Single-Ended mode. The X-Position of the joystick is
connected to channel 2 of the ADC, and the Y-Position is connected to channel 3 of the ADC.
An interesting feature of the ADC is that it converts the analog voltage at the same time that it receives the
“don’t care” bits from the SPI master. Each bit of the conversion, starting from the MSB, is shifted out as
it is calculated 4 . Remember that with a SPI, both transmission and reception occur simultaneously via shift
registers. Page 9 of the ADC datasheet shows a timing diagram of the conversion. The binary code is also stored
in a register to provide a LSB serial output of the value. This occurs immediately following the MSB-first serial
output. The partial information from the LSB-first value can be discarded.
4 This fact should tell you, without referring to the documentation, what type of converter is used within the ADC.
7.5. PART II - ADC INTERFACING 65

Figure 7.5: SPI communication with ADC

7.5.3 Joystick Operation

Movement left and right on the joystick changes the X analog value, while movement forward and back on the
joystick changes the Y analog value. The joystick is ‘asymmetric’. In other words, do not expect the X and Y
analog values to vary linearly with position. It is a good idea to map the analog values with respect to position
BEFORE completing the test mode software. Perhaps write a small program to help you do so. You will want to
determine the voltages at the eight cardinal points (North, NorthWest, etc.) and at a sufficient number of points
in between so as to be able to generate a smooth and continuous measurement of the X and Y position. This will
allow you to smoothly change either the audio speaker value or the motor value when you implement Part III.
It may be difficult to determine a mathematical expression to describe the interpolation between the position and
analog voltage at the cardinal points. An alternative approach is to use an array as a look up table in order to
implement this functionality.

There are many ways to model nonlinear transducers.... A third approach to model a nonlinear
transducer uses a look-up table located in memory. This method is convenient and flexible. Let x
be the measurand and y be the transducer output. The table contains x values, and the measured
y value is used to index into the table. Sometimes a small table coupled with linear interpolation
achieves equivalent results to a large table. 5

The joystick may have calibration wheels. These skew the analog values output to the ADC. It is strongly
recommended that you perform all of your calibration and operation with these wheels near their centre position
such that the range of analog values is maximized. This ensures the best resolution for all joystick positions. Note
also that all of the joysticks in the lab are somewhat different, hence a distinct calibration might be required for
each.

7.5.4 Desired Functionality

Upon completion of Part II, your system should have the following functionality:

• Pressing and releasing push button 1 will immediately put the system into test mode.
• Once in test mode, the system will constantly display the current cardinal point of the joystick on the seven
segment display as illustrated in Figure 7.2.
• While in test mode the seven segment display should read “–” when the joystick is centred and neutral.
• The system will remain in test mode until another mode is selected.
5 J. W. Valvano, Embedded Microcomputer Systems: Real Time Interfacing, p.685
66 CHAPTER 7. LAB 3

• Pressing and releasing push button 2 will immediately put the system into music mode. In this mode, the
seven segment display should display the corresponding music note.
• Pressing and releasing push button 3 will immediately put the system into motor mode. In this mode, the
seven segment display should display the corresponding motor symbol.

7.6 Part III - The Complete System

Complete ONE of the following two options.

7.6.1 Option 1: Music Scale Player

The system for Option 1 uses an audio speaker as an output device. To enter music mode pushbutton two is
pressed and released. When in this mode, the dip switch values determine the base note of the music scale, and
the joystick position determines the note within that scale. The note is output to the seven segment display and
to the speaker as a (pseudo) sine wave of the appropriate frequency. Note that you do not need to be musically
inclined to complete this option: scales, notes and their frequencies are included in this manual.
Figure 7.3 shows the connection of the speaker to the DAC. The speaker is connected to channel 0 of the DAC.
You will need to read the DAC data sheets to determine how to transmit data to the DAC. The DAC should be
operated in full-buffered mode.

7.6.2 Option 2: Motor Control

The system for Option 2 uses a DC electric motor as an output device. To enter motor mode pushbutton three is
pressed and released. When in this mode, the joystick controls either the velocity or position of the motor. When
the joystick is pushed forwards or backwards, the motor spins clockwise or counterclockwise respectively, at a
velocity proportional to joystick position. When the joystick is toggled left or right, the motor changes position by
a fixed amount either clockwise or counterclockwise. This amount is determined by the value on the dip switches.
The motor operation is indicated on the seven segment display.
Figure 7.3 shows the connection of the motor circuit to the opto-isolators. The motor is connected to channel
zero on each of the opto-isolator outputs. Hence, enabling channel zero of the first opto-isolator chip will spin the
motor in one direction, while enabling channel zero of the other chip will spin the motor in the other direction.
If both channels are enabled simultaneously, a short circuit will occur, therefore this situation must never arise.
As shown in Figure 7.8, the DC motor will be controlled via Pulse Width Modulation (PWM). Sections 6.2.5
and 8.5.5 of Valvano discuss PWM.

7.6.3 Desired Functionality

Your system should include the functionality implemented in Part II, as described in Section 7.5.4.
If Option 1 is implemented, your system is to use push button and timer interrupts to implement the following
functionality on the Excalibur Development Board.

• Pressing and releasing pushbutton two will immediately put the system into music mode.
• Upon entry into this mode, the dip switch values are used to determine the starting note of the music scale
as in Figure 7.6. Changing the dip switches should have no effect on system operation until pushbutton
two is pressed and released again.
7.6. PART III - THE COMPLETE SYSTEM 67

Figure 7.6: Audio Output for Lab 3

• While in music mode, if the joystick is centred and neutral, the seven segment display should read “–” and
no output should be sent to the audio speaker.

• While in music mode, if the joystick is at one of the cardinal points, the corresponding musical note should be
displayed on the seven segment display as described in Figure 7.2. Furthermore, the musical note should be
output to the audio speaker as described in Figure 7.6. The ‘Northwest’ position of the joystick corresponds
with the first note in the scale. Subsequent notes are one cardinal point clockwise from the previous as
illustrated in Figure 7.7. Hence, the ‘West’ position corresponds with the last note in the scale.

• While in music mode, if the joystick is outside of the neutral position but between cardinal points, output
should nonetheless be sent to both the speaker and the display. The tone should be at a frequency between
that of the two neighbouring cardinal points such that the frequency varies continuously and fluidly between
them. The display should simply indicate the nearest music note (corresponding to the nearest cardinal
point).

• The system will remain in music mode until a different mode is selected via another push button.

If Option 2 is implemented, your system is to use push button and timer interrupts to implement the following
functionality on the Excalibur Development Board.

• Pressing and releasing pushbutton three will immediately put the system into motor mode.

• Upon entry into this mode, the dip switch values are used to determine the amount of rotation for motor
pulses as illustrated in Figure 7.8. Changing the dip switches should have no effect on system operation
until pushbutton three is pressed and released again.
68 CHAPTER 7. LAB 3

Figure 7.7: Major music scales used in Lab 3

• While in motor mode, if the joystick is centred and neutral, the seven segment display should read “–” and
the electric motor should be still.
• While in motor mode, if the joystick is moved in the Y-plane (forwards and backwards), the motor should
spin, clockwise or counterclockwise respectively, at a velocity proportional to Y-distance from the origin.
The seven segment display should simultaneously output a value proportional to Y-distance from the origin,
hence motor velocity, as described in Figure 7.2.
• While in motor mode, if the joystick is moved in the X-plane (right and left), the motor should pulse
clockwise or counterclockwise respectively, in a manner determined by the dip switch values (Figure 7.8).
Furthermore, the seven segment display should signal the start and stop of the pulse as illustrated in
Figure 7.2. Before another pulse takes place, the joystick must first be returned to the neutral position. In
other words, to make two clockwise pulses, the joystick would have to be moved to the right, returned to
the origin, then moved to the right again.
• The system will remain in motor mode until a different mode is selected via another pushbutton.

When not in use, both the speaker and motor must be off. For example, when changing from motor mode to
test mode, the motor must be explicitly stopped.
If implementing Option 1, to improve audibility, you may wish to output a higher octave than the one given in
this manual.

7.6.4 Intermediate Design Stages

You may wish to consider approaching the software design in stages. The following intermediate design stages
may be useful.

1. Write a program which approximates outputting a sine wave to the audio speaker using the nr delay function
(Option 1).
2. Write a program which spins the motor at various speeds (Option 2).
7.6. PART III - THE COMPLETE SYSTEM 69

Figure 7.8: Dip Switch Effect on Motor Movement for Lab 3

70 CHAPTER 7. LAB 3

3. Then modify your code to fully implement the Option functionality.

7.7 Testing, Debugging, and Going Further

Test your design thoroughly to ensure that it meets the required functionality as described herein. This lab is
more complex than those previous, so if you have questions regarding the lab requirements and the expected
functionality of your system, do not hesitate to ask a TA.
You will doubtless encounter some bugs in your software and hardware. Choose a reliable and effective debugging
strategy and record in your lab diary all bugs and corrective measures. Check the lab FAQ on the course webpage
and the course newsgroup for solutions to typical problems. You may wish to put printf statements in your code
to verify program flow and execution. But remember to remove all debug output (especially printfs) before your
demo. Review the debugging suggestions given in the course notes.
Should you complete lab 3 in less than the allotted number of lab sessions, you may try to implement the other
Option in your system. You will not be awarded bonus marks for doing so, but you will gain additional experience,
and hopefully have fun doing so! You may also expand on the functionality of your given option if time permits.
But remember that you will only be graded on the required functionality of the lab - so ensure that your ‘improved’
design still meets the requirements.

7.8 Deliverables

In order to be graded on Lab 3, you must demonstrate your system, show your code, and submit a (8-10 page)
report. Your report must include as its cover page the signed declaration of authorship form, which is given to
you by the checkoff TA at your demo session.
Demonstrations must be complete and reports submitted by Thursday July 25. Reports should be submitted in
the drop box.
Again, the emphasis on Lab 3 is learning, not necessarily producing an embedded system as described in the
manual. Students whose final systems do not fully meet the specifications may still get full marks on the lab,
if they demonstrate a high level of understanding and insight in the lab report. In order to allow for this, there
will be 5 marks allotted to the demonstration and 10 marks to the lab report. The lab is worth 12 marks. Your
demo and report will be graded out of 15, and your final mark for the lab will be the lesser of this grade or 12.
Put another way, you may lose up to 3 marks on the demonstration, and with a perfect lab report still get 12/12
for Lab 3. This has been done to encourage learning and understanding as goals, rather than getting to the final
system. Put still another way: anything greater than 12/15 can be considered a perfect mark, because these
grades will all translate to a 12/12 in the end.

7.8.1 Demonstration

Sign up for a demonstration slot early. If possible, reserve an early session so that groups requiring more time can
use the later sessions. You can sign up for your demo online at ece.uwaterloo.ca/signup.html.
At your demo session, you will be required to download your hardware design to the development board, then
download and run your software. The check-off TA will determine the operation of your embedded system and
ask you questions about your design. You will also be required to show your C/C++ code.
Once your demo is complete, the check-off TA will present you with a lab sign-off form and a submission statement.
You will submit these with your report.
7.9. DAUGHTERBOARD SCHEMATIC 71

7.8.2 Report

In your report, you should have the following sections.

• An overview of your complete system design, using block diagrams, pseudocode, prose, or a mixture of
some or all of these.
• A discussion of the issues associated with the design of the analog interfacing.
• An indication of one hardware design decision you made and at least one alternative choice which you
discarded.
• A description of the hardware testing & debugging strategy you used for one part of your hardware, and at
least one alternative strategy which you discarded.
• An indication of one software design decision you made and at least one alternative choice which you
discarded.

• A description of the software testing & debugging strategy you used for one part of your software, and at
least one alternative strategy which you discarded.
• An indication of one analog interfacing design decision you made and at least one alternative choice which
you discarded.
• A description of the analog interfacing testing & debugging strategy you used for one part of your analog
interface, and at least one alternative strategy which you discarded.
• A brief discussion of a possible future extension to the lab. Given more choice for a final project (and
possibly 4-5 weeks in which to do it) and the same equipment, what would you have rather done?

The “design decision” sections should include a description of the pros and cons of your choice, with respect to
efficiency, ease of implementation, and ease of testing/debugging.
Note that the “testing & debugging” sections ask for your strategy. This may be a story about how you debugged
a specific problem you ran into. It may also be a decision you made about how you were going to test a specific
portion of your functionality. You should keep a lab diary so that you can easily include this in your report. The
report should contain a summary of your test & debug approach, rather than 10 pages rewritten or photocopied
from the diary. The chances are incredibly small that everything compiled, simulated, downloaded, and ran
perfectly the first time, at every stage, and that you never ran into a single bug, problem, or difficulty. However,
even in this case, you must still show that you had in place a logical, systematic strategy for testing your hardware,
software, and integration.

7.9 Daughterboard Schematic

A complete schematic of the daughterboard is given in Figure 7.9.
In 2002, we were unfortunately not able to include this schematic in the lab manual. It will be available in the
lab for those who wish to view it.
72 CHAPTER 7. LAB 3

Figure 7.9: Daughterboard Schematic