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© 2013 Freescale Semiconductor, Inc.
Chapter 1
About This Book
Chapter 2
Design Checklist
Chapter 3
i.MX 6 Series Layout Recommendations
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor iii
Contents
Paragraph Page
Number Title Number
3.5.1 Swapping data lines ................................................................................................... 3-10
3.5.2 DDR3 (64 bits) T topology considerations................................................................ 3-10
3.5.3 DDR3 (64 bits) Fly-by topology considerations........................................................ 3-10
3.5.4 2-Gigabyte recommendations .................................................................................... 3-10
3.5.5 4-Gigabyte recommendations .................................................................................... 3-11
3.5.6 Four chips T topology routing examples ................................................................... 3-13
3.5.7 Eight chips fly-by topology routing examples........................................................... 3-17
3.5.8 High speed signal routing recommendations............................................................. 3-25
3.5.9 Ground plane recommendations ............................................................................... 3-25
3.6 DDR power recommendations....................................................................................... 3-28
3.7 PCI Express interface recommendations ...................................................................... 3-29
3.7.1 PCI Express general routing guidelines..................................................................... 3-29
3.7.2 PCI Express coupling lane......................................................................................... 3-30
3.7.3 Additional resources for PCI Express signal routing recommendations ................... 3-30
3.8 HDMI recommendations ............................................................................................... 3-30
3.9 SATA recommendations ................................................................................................ 3-30
3.10 LVDS recommendations ................................................................................................ 3-30
3.11 USB recommendations .................................................................................................. 3-31
3.12 Impedance signal recommendations .............................................................................. 3-31
3.13 Reference resistors ......................................................................................................... 3-32
3.14 ESD and radiated emissions recommendations ............................................................. 3-33
3.15 Component placement recommendations ...................................................................... 3-33
3.16 Reducing skew and phase problems in deferential pairs traces..................................... 3-33
3.17 Guideline for power net electrical performance ............................................................ 3-35
Chapter 4
Requirements for Power Management
Chapter 5
Using the Clock Connectivity Table
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
iv Freescale Semiconductor
Contents
Paragraph Page
Number Title Number
Chapter 6
Using the IOMUX Design Aid
Chapter 7
Configuring JTAG Tools
Chapter 8
Avoiding Board Bring-up Problems
Chapter 9
Understanding the IBIS Model
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor v
Contents
Paragraph Page
Number Title Number
9.5.1.2 RGMII...................................................................................................................... 9-9
9.5.2 [Model Selector] gpio ................................................................................................ 9-10
9.5.3 [Model Selector] lvds................................................................................................. 9-11
9.5.4 [Model Selector] mlb ................................................................................................. 9-11
9.5.5 [Model Selector] USB ............................................................................................... 9-11
9.5.6 List of pins not modeled in the i.MX6 IBIS file........................................................ 9-12
9.6 Quality assurance for the IBIS models .......................................................................... 9-12
9.7 IBIS usage...................................................................................................................... 9-13
9.8 References...................................................................................................................... 9-13
Chapter 10
Using the Manufacturing Tool
Chapter 11
Using BSDL for Board-level Testing
Chapter 12
Using the RMII Interface
Appendix A
Development Platforms
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
vi Freescale Semiconductor
Contents
Paragraph Page
Number Title Number
Appendix B
Revision History
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor vii
Contents
Paragraph Page
Number Title Number
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
viii Freescale Semiconductor
Chapter 1
About This Book
1.1 Overview
This document’s purpose is to help hardware engineers design and test their i.MX 6 series processor based
designs. It provides information on board layout recommendations, design checklists to ensure first-pass
success and ways to avoid board bring-up problems. It also provides information on board-level testing
and simulation such as properly configuring JTAG tools, using BSDL for board-level testing, using the
IBIS model for electrical integrity simulation and more.
Engineers are expected to have a working understanding of board layouts and terminology, IBIS modeling,
BSDL testing and common board hardware terminology.
This guide is released along with relevant device-specific hardware documentation such as datasheets,
reference manuals and application notes available on www.freescale.com.
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 1-1
About This Book
1.6 Conventions
This document uses the following notational conventions:
Courier Used to indicate commands, command parameters, code examples, and file and
directory names.
Italics Italics indicates command or function parameters
Bold Function names are written in bold.
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
1-2 Freescale Semiconductor
About This Book
cleared/set When a bit takes the value zero, it is said to be cleared; when it takes a value of
one, it is said to be set.
mnemonics Instruction mnemonics are shown in lowercase bold
Book titles in text are set in italics
sig_name Internal signals are written in all lowercase
nnnn nnnnh Denotes hexadecimal number
0b Denotes binary number
rA, rB Instruction syntax used to identify a source GPR
rD Instruction syntax used to identify a destination GPR
REG[FIELD] Abbreviations for registers are shown in uppercase text. Specific bits, fields, or
ranges appear in brackets. For example, MSR[LE] refers to the little-endian mode
enable bit in the machine state register.
x In some contexts, such as signal encodings, an unitalicized x indicates a don’t
care.
x An italicized x indicates an alphanumeric variable
n, m An italicized n indicates a numeric variable
NOTE
In this guide, notation for all logical, bit-wise, arithmetic, comparison, and
assignment operations follow C Language conventions.
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 1-3
About This Book
GND Ground
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
1-4 Freescale Semiconductor
About This Book
PoP Package-on-package
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 1-5
About This Book
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
1-6 Freescale Semiconductor
Chapter 2
Design Checklist
2.1 Design checklist overview
This chapter provides a design checklist for the following i.MX 6 series families of processors:
• i.MX 6Quad
• i.MX 6Dual
• i.MX 6DualLite
• i.MX 6Solo
The design checklist tables (Table 2-1–Table 2-14) contain recommendations for optimal design. Where
appropriate, the checklist tables also provide an explanation of the recommendation so that users have a
greater understanding of why certain techniques are recommended. All supplemental tables referenced by
the checklist appear in sections following the design checklist tables.
See also the application note Common Hardware Design for i.MX 6Dual/6Quad and i.MX
6Solo/6DualLite (AN4397).
1. Connect ZQPAD to an external 240 Ω 1% resistor This is a reference used during DRAM output buffer
to GND. driver calibration.
2. Connect DRAM_VREF to a source that is 50% of • The user may tie DDR_VREF to a precision external
the voltage value of NVCC_DRAM. resistor divider. Shunt each resistor with a
closely-mounted 0.1 μF capacitor. See Table 2-15 for
resistor values. Using resistors with recommended
tolerances ensures the ±2% DDR_VREF tolerance
per the DDR3 specification.
• The user can use a PMIC’s tracking regulator as
used on Freescale reference designs. A tracking
regulator is recommended as a reference for memory
configurations of more than four devices.
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 2-1
Design Checklist
5. Make sure that the correct LPDDR2 function is MMDC IO names are for the DDR3 default. When
connected to the correct I/O. Note that this does not LPDDR2 is selected, the I/O name (DDR3 MMDC PAD)
necessarily correspond to the I/O name. does not match with the LPDDR2 functionality. See the
“LPDDR2 and DDR3 pin mux mapping” table in the
“Multi Mode DDR Controller (MMDC)” chapter in your
chip reference manual.
1. When EIM boot signals are used as the system’s Because only resistors are used, EIM bus loads can
EIM signals, other functions, or GPIO outputs after cause current drain, leading to higher (false) supply
boot, use a passive resistor network to select the current measurements. Each EIM boot signal should
desired boot mode for development boards. connect to a series resistor to isolate the bus from the
resistors and/or switchers; see Figure 2-1. Each
configured EIM boot signal sees either a 14.7 kΩ
pulldown or a 4.7 kΩ pullup. For each switch-enabled
pulled-up signal, the supply is presented with a 10 kΩ
current load.
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
2-2 Freescale Semiconductor
Design Checklist
2. To reduce incorrect boot-up mode selections, do Using EIM boot interface lines as inputs may result in a
one of the following: wrong boot up due to the source overcoming the pull
• Use EIM boot interface lines only as processor resistor value. A peripheral device may require the EIM
outputs. Ensure EIM boot interface lines are not signal to have an external or on-chip resistor to minimize
loaded down such that the level is interpreted as signal floating.
low during power-up, when the intent is to be a If the usage of the EIM boot signal affects the peripheral
high level, or vice versa. device, then an analog switch, open collector buffer, or
• If an EIM boot signal must be configured as an equivalent should isolate the path. A pullup or pulldown
input, isolate the EIM signal from the target driving resistor at the peripheral device may be required to
source with one analog switch and apply the logic maintain the desired logic level. Review the switch or
value with a second analog switch. Alternately, device data sheet for operating specifications.
peripheral devices with three-state outputs may be
used; ensure the output is high-impedance during
the boot up interval.
3. The BOOT_CFG signals are required for proper See the “System Boot” chapter in your chip reference
functionality and operation and should not be left manual for the correct boot configuration. Note that an
floating. incorrect setting may result from an improper booting
sequence.
1. For BOOT_MODE1 and BOOT_MODE0, use one of Boot inputs BOOT_MODE1 and BOOT_MODE0 each
the following options to achieve logic 0: have on-chip pulldown devices with a nominal value of 100
• Tie to GND through any size external resistor kΩ, a projected minimum of 60 kΩ, and a projected
• Tie directly to GND maximum of 140 kΩ.
• Float Be aware that when these are logic high, current is drawn
For logic 1, use one of the following: from the VDD_SNVS supply.
• Tie directly to the VDD_SNVS_IN rail In production, when on-chip fuses determine the boot
• Tie to the VDD_SNVS_IN rail through an external configuration, both boot mode inputs can be no connects.
resistor 10 kΩ. A value of 4.7 kΩ is preferred in
high-noise environments.
If switch control is desired, no external pulldown
resistors are necessary. Simply connect SPST switches
directly to the VDD_SNVS_IN rail. If desired, a 4.7 kΩ
to 10 kΩ series resistor can be used when current drain
is critical.
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 2-3
Design Checklist
1. Verify the target I2C interface clock rates. The bus can only operate as fast as the slowest peripheral
on the bus. If faster operation is required, move the slow
devices to another I2C port.
2. Verify that the target I2C address range is supported These chips support up to:
and does no conflict with other peripherals. If there is • Three I2C ports for the i.MX 6Quad and 6Dual families
an unavoidable address conflict, move the offending • Four I2C ports for the i.MX 6DualLite and 6Solo
2
device to another I C port. See Table 2-16. families.
If it is undesirable to move a conflicting device to another
I2C port, review the peripheral operation to see if it
supports remapping the address.
3. Do not place more than one set of pullup resistors on This can result in excessive loading. Good design
the I2C lines. practice is to place one pair of pullups only.
1. Do not use external pullup or pulldown resistors on JTAG_TDO is configured with an on-chip keeper circuit
JTAG_TDO. such that the floating condition is actively eliminated if an
external pull resistor is not present. An external pull
resistor on JTAG_TDO is detrimental. See Table 2-19 for
a summary of the JTAG interface.
2. Ensure that the on-chip pullup/pulldown External resistors can be used with all JTAG signals
configuration is followed. If external resistors are used except JTAG_TDO, but they are not required. See
with JTAG signals, with the exception of JTAG_TDO. Table 2-19 for a summary of the JTAG interface.
For example, do not use an external pulldown on an
input that has an on-chip pullup.
3. JTAG_MOD may be referred to as SJC_MOD in When JTAG_MOD is low, the JTAG interface is configured
some documents. Both names refer to the same signal. for common software debug, adding all the system taps to
JTAG_MOD should be externally connected to GND for the chain.
normal operation in a system. Termination to GND When JTAG_MOD is high, the JTAG interface is
through an external pulldown resistor is allowed. configured to a mode compliant with the IEEE 1149.1
Use ≤ 4.7 kΩ. standard.
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
2-4 Freescale Semiconductor
Design Checklist
1. Comply with the power-up sequence guidelines as Any deviation from these sequences may result in the
described in the data sheet to guarantee reliable following situations:
operation of the device. • Excessive current during power-up phase
• Prevention of the device from booting
• Irreversible damage to the processor (worst-case
scenario)
2. Do not overload coin cell backup power rail Freescale PMIC PMPF0100 VSNVS regulator is rated to
VDD_SNVS_IN. Note that the following I/Os are supply 400 μA output current under worst-case operating
associated with VDD_SNVS_IN; most inputs have conditions. The VDD_SNVS_IN regulator can supply
on-chip pull resistors and do not require external larger current in transient situations without damaging the
resistors: regulator.
• POR_B – on-chip pullup; see Table 2-8 #1 Concerning i.MX6:
• ONOFF – on-chip pullup; see Table 2-8 #2 • When VDD_SNVS_IN = VDD_HIGH_IN, SNVS
• BOOT_MODE0 – on-chip pulldown; see Table 2-3 domain current is drawn from both equally.
#1 • When VDD_HIGH_IN > VDD_SNVS_IN,
• BOOT_MODE1 – on-chip pulldown; see Table 2-3 VDD_HIGH_IN supplies all SNVS domain current and
#1 current flows into VDD_SNVS_IN to charge a coin cell
• TAMPER – on-chip pulldown battery.
• PMIC_STBY_REQ – push-pull output • When VDD_SNVS_IN > VDD_HIGH_IN,
• PMIC_ON_REQ – push-pull output VDD_SNVS_IN supplies current to SNVS, and some
• TEST_MODE – on-chip pulldown; see Table 2-14 #1 current flows into VDD_HIGH_IN.
Note:VDD_HIGH_IN must be valid (above the internal
detector threshold, 2.4 V typ) for the current flow to
occur. Thus, current flow only happens when
VDD_HIGH_IN is powered to a level below
VDD_SNVS_IN. If VDD_HIGH_IN is off or low, no extra
current is drawn from VDD_SNVS_IN. The whole
circuit assumes it is charging a coin cell and starts
charging when VDD_HIGH_IN is valid. If you are
driving VDD_SNVS_IN with a non-battery power
source, it must be at the same level as VDD_HIGH_IN
or current will flow between them.
• When VDD_SNVS_IN is not powered by a battery, it is
recommended that VDD_SNVS_IN = VDD_HIGH_IN.
If VDD_SNVS_IN is tied to a battery, the battery eventually
discharges to a value equal to that of VDD_HIGH_IN and
never subsequently charges above VDD_HIGH_IN.
The battery chemistry may add restrictions to
VDD_HIGH_IN’s voltage range. External charging
components should be based on the battery
manufacturer's specifications.
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 2-5
Design Checklist
3. Only one 22 μF bulk capacitor should be connected If the nominal capacitance value is larger than
to each of these on-chip LDO regulator outputs: recommended, power-up ramp time is excessive and
• VDD_ARM_CAP operation cannot be guaranteed. Note that the ramp up
• VDDARM23_CAP time is constant. Larger capacitors mean more inrush
• VDD_SOC_CAP current. Select small capacitors with low ESR (equivalent
• VDD_PU_CAP series resistance).
A 22 μF bulk capacitor must be placed as near as The 22 μF bulk capacitors should be placed as close as
possible with pins/vias. The distance should be less possible to the associated VDD_xx_CAP ball, with trace
than 50mil between bulk cap and VDD_xx_CAP pins. widths and via sizes appropriate to the expected current
Decoupling capacitors such as 0.1 μF or 0.22 μF should draw. A trace length of less than 50 mil is recommended.
also be used. Do not connect any loads to these LDO outputs:
VDDARM_CAP, VDDARM23_CAP, or VDDPU_CAP.
VDDSOC_CAP is restricted to MX6 loads.
4. Only one 10 μF bulk capacitor should be connected If the nominal capacitance value is larger than
to each of these on-chip LDO regulator outputs: recommended, power-up ramp time is excessive and
• VDD_HIGH_CAP operation cannot be guaranteed. Select small capacitors
• NVCC_PLL_OUT with low ESR.
• VDD_USB_CAP These LDOs should only be used to power the loads as
Decoupling capacitors such as 0.1 μF or 0.22 μF should described in the reference manual or data sheet. Do not
also be used. connect any loads to these LDO outputs:
NVCC_PLL_OUT or VDDUSB_CAP. VDDHIGH_CAP is
restricted to MX6 loads.
5. One 0.22 μF decoupling capacitor should be If the nominal value is larger than recommended,
connected to VDD_SNVS_CAP, an on-chip LDO power-up/down ramp time is excessive and
regulator output. A bulk capacitor is not necessary. suspend/resume operation cannot be guaranteed. Select
a small capacitor with low ESR.
Note: Do not connect any loads to VDD_SNVS_CAP.
6. Maximum ripple voltage requirements. Common requirement for ripple noise should be less than
5% Vp-p of supply voltage average value.
Related power rails affected: all VDD_xxx_IN and
VDD_xxx_CAP.
7. NVCC_LVDS2P5 must be powered-on even when The DDR pre-drivers share the NVCC_LVDS2P5 power
not using the LVDS interface. rail with the LVDS interface. VDDHIGH_CAP can be
utilized as the power source; tie NVCC_LVDS2P5 to
VDDHIGH_CAP.
8. Account for the different power design on • i.MX 6Quad and 6Dual chips can support three different
NVCC_EIM between i.MX 6Quad and 6Dual chips and EIM power rail voltage levels: NVCC_EIM0(K19),
i.MX 6DualLite and 6Solo chips. NVCC_EIM1(L19), and NVCC_EIM2(M19).
• i.MX 6DualLite and 6Solo chips support one EIM power
rail: NVCC_EIM (K19, L19, M19). The three power
contacts must be connected to same power supply.
9. If VDD_SNVS_IN is directly supplied by a coin cell, a When no power is supplied to VDD_VSNVS_IN, the diode
schottky diode is required between VDD_HIGH_IN and limits the voltage difference between the two on-chip
VDD_SNVS_IN. The cathode is connected to SNVS power domains to approximately 0.3 V. The
VDD_SNVS_IN. processor is designed to allow current flow between the
Alternately, VDD_HIGH_IN and VDD_SNVS_IN can be two SNVS power domains proportional to the voltage
tied together if the real-time clock function is not difference.
needed during system power-down.
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
2-6 Freescale Semiconductor
Design Checklist
1. Precision 32.768 kHz oscillator The capacitors implemented on either side of the crystal
Connect a crystal between RTC_XTALI and are about twice the crystal load capacitance. To hit the
RTC_XTALO. Choose a crystal with a maximum of target oscillation frequency, board capacitors need to be
100 kΩ ESR (equivalent series resistance) and follow reduced to compensate for board and chip parasitic
the manufacturer’s recommendation for loading capacitance; typically 15–16 pF is employed.
capacitance. The integrated oscillation amplifier has an on-chip
Do not use an external biasing resistor because the self-biasing scheme, but is high-impedance (relatively
bias circuit is on-chip. weak) to minimize power consumption. Care must be
taken to limit parasitic leakage from RTC_XTALI and
RTC_XTALO to either power or ground (> 100 MΩ) as
this negatively affects the amplifier bias and causes a
reduction of startup margin.
Use short traces between the crystal and the processor,
with a ground plane under the crystal, load capacitors,
and associated traces.
2. External kilohertz source The voltage level of this driving clock should not exceed
If feeding an external clock into the device, the voltage of VDD_SNVS_CAP and the frequency
RTC_XTALI can be driven DC-coupled with should be <100 kHz under typical conditions. Do not
RTC_XTALO floated or driven with a complimentary exceed VDD_SNVS_CAP or damage/malfunction may
signal. occur. The RTC_XTALI signal should not be driven if the
VDD_SNVS_CAP supply is off. This can lead to damage
or malfunction.
For RTC_XTALI VIL and VIH voltage levels, see the latest
i.MX 6 series datasheet available at www.freescale.com.
Note that if this external clock is stopped, the internal ring
oscillator starts automatically.
3. Loose-tolerance 40 kHz oscillator When a high-accuracy real-time clock is not required, the
An on-chip loose-tolerance ring oscillator is available system may use the on-chip 40 kHz oscillator. The
of approximately 40 kHz. If RTC_XTALI is tied to GND tolerance is ± 50%.
and RTC_XTALO is floating, the on-chip oscillator is The ring oscillator starts faster than an external crystal
automatically engaged. and is used until the external crystal reaches stable
oscillation. The ring oscillator also starts automatically if
no clock is detected at RTC_XTALI at any time.
4. Precision 24 MHz oscillator Freescale BSP software requires 24 MHz on this clock.
Connect a fundamental-mode crystal between XTALI This clock is used as a reference for USB, PCIe, and
and XTALO. An 80 Ω typical ESR crystal rated for a SATA, so there are strict frequency tolerance and jitter
maximum drive level of 250 μW is acceptable. requirements. See Table 2-20 for guidelines. See the
Alternately, a 50 Ω typical ESR crystal rated for a crystal oscillator (XTALOSC) reference manual chapter
maximum drive level of 200 μW may be used. See the and relevant interface specification chapters for details.
engineering bulletin EB830 on www.freescale.com for To access a calculator for the 24 MHz crystal drive level,
additional options. see EB830 on the i.MX Community.
5. External megahertz source For XTALI VIL and VIH voltage levels, see the latest i.MX
If feeding an external clock into the device, XTALI can 6 series datasheet. This clock is used as a reference for
be driven DC-coupled with XTALO floated. USB, PCIe, and SATA, so there are strict frequency
tolerance and jitter requirements. See Table 2-20 for
guidelines. See the crystal oscillator (XTALOSC)
reference manual chapter and relevant interface
specification chapters for details.
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 2-7
Design Checklist
6. CLK1_P/CLK1_N and CLK2_P/CLK2_N are LVDS The clock inputs/outputs are general-purpose differential
input/output differential pairs compatible with high-speed clock Input/outputs.
TIA/EIA-644 standard. The frequency range is 0 to Any or both of them can be configured:
600 MHz. • As inputs to feed external reference clocks to the
Alternatively, a single-ended signal can be used to on-chip PLLs and/or modules, for example as
drive a CLKx_P input. In this case, the corresponding alternate reference clock for PCIe or/and SATA or
CLKx_N input should be tied to a constant voltage video/audio interfaces.
level equal to 50% of VDD_HIGH_CAP. Termination • As outputs to be used as either a reference clock or as
should be provided with high-frequency signals. a functional clock for peripherals, for example an
See the LVDS pad electrical specification in the data output of the PCIe master clock (root complex use).
sheet for further details. See the chip reference manual for details on the
After initialization, the CLKx inputs/outputs can be respective clock trees.
disabled (if not used) by the PMU_MISC1 register. If
unused, any or both of the CLKx_N/P pairs may be left
floating.
7. Bias XTALI with a 2.2 MΩ resistor to GND. Mount The XTALI bias must be adjusted externally to ensure
the resistor close to the XTALI ball. reasonable start-up time. Without the resistor, start-up
time may be 200 ms or more.
1. The POR_B input must be asserted low at power-up A reset switch may be wired to the chip’s POR_B, which
and remain asserted until after the last power rail for is a cold-reset negative-logic input that resets all modules
devices required for system boot are at their working and logic in the IC. POR_B may be used in addition to
voltage. internally generated power-on reset signal (logical AND,
both internal and external signals are considered active
low).
2. For portable applications, the ONOFF input may be A brief connection to GND in OFF mode causes the
connected to an ON/OFF SPST push-button switch. internal power management state machine to change
On-chip debouncing is provided, and this input has an state to ON.
on-chip pullup. In ON mode, a brief connection to GND generates an
If not used, ONOFF should be a no connect. interrupt (intended to be a software-controllable
power-down).
An approximate 5 second or more connection to GND
causes a forced OFF.
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
2-8 Freescale Semiconductor
Design Checklist
1. This chip requires a 125 MHz reference clock If NVCC_ENET is powered at 3.3 V, the minimum VIH
feeding the ENET_REF_CLK input. This reference level is 70% of 3.3 V or 2.3 V. Designers should ensure
clock should be sourced from an external 125 MHz that there is margin to this minimum value. A starting value
oscillator or an external PHY. could be 500 mV margin, resulting in a requirement of
Designers should be aware of the 125 MHz reference 2.8 V for the logic high. See the Freescale Smart Devices
output level of the PHY because ENET_REF_CLK is development designs for a suitable low-cost level
on the NVCC_ENET supply rail, not the NVCC_RGMII translator.
rail.
2. For IEEE-1588 operation, the GPIO_16 ball must be This allows use of time stamping on the RGMII interface.
configured as either one of the following:
• A no connect to allow the internal time stamp clock
to route through its IOMUX cell to the RGMII
interface
• Driven by an external clock source for the time
stamp
1. Termination is required on the differential clock lines. These termination resistors should be placed as close as
Connect two 49.9 Ω resistors, one between REFCLK- possible to the receiver device inputs in case the chip
and GND, the other between REFCLK+ and GND. LVDS clock outputs are used as the REFCLK source for
Alternately, Connect a 100 Ω resistor between the PCIe endpoint device.
REFCLK- and REFCLK+.
2. The differential transmitter must be ac coupled. Use To ensure PCIe specification compliance, ac coupling is
a 0.1 uF-series capacitor on PCIE_TXP and a second required at each transmitter. The receiver must be dc
0.1 uF on PCIE_TXM. coupled.
1. The designer must ensure that a suitable level shifter The i.MX 6 processors’ I2C cannot operate at the 5 V
and driver be used to interface the chip’s I2C with the required by HMDI EDID. The i.MX 6 processors’ supply
HDMI monitor. limit is 3.6 V maximum.
In addition, ESD (electrostatic discharge) protection The designer could consider the ON Semiconductor
must be used on all HDMI single-ended and differential CM2020 for ESD protection and I2C level conversion.
signals mounted near the board’s HDMI connector. Note: Freescale cannot recommend one supplier over
another and does not suggest that this is the only
HDMI interface chip supplier.
2. DDC (EDID) must be on a dedicated I2C When HDCP is enabled, a dedicated I2C is controlled by
(DDC_SCL/DDC_SDA) port when HDCP the HDMI PHY to exchange the HDCP encryption key and
(High-Bandwidth Digital Content Protection) is enabled. must sync several times per second. DDC does not
behave like a common I2C and cannot be controlled by the
ARM® CPU with HDCP enabled.
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 2-9
Design Checklist
1. HDMI_REF – Connect an external 1.6 kΩ 1% If HDMI is unused, the reference resistor may be
resistor to GND. populated if desired for manufacturability purposes, or left
no-connect for cost savings.
2. SATA_REXT – Connect an external 191 Ω 1% The impedance calibration process requires connection of
resistor to GND. this reference resistor.
If SATA is unused, the reference resistor may be
populated if desired for manufacturability purposes, or left
no-connect for cost savings.
3. PCIE_REXT – Connect an external 200 Ω 1% The impedance calibration process requires connection of
resistor to GND. this reference resistor.
If PCIe is unused, the reference resistor may be populated
if desired for manufacturability purposes, or left
no-connect for cost savings.
4. CSI_REXT – Connect an external 6.04 kΩ 1% If CSI is unused, the reference resistor may be populated
resistor to GND. if desired for manufacturability purposes, or left
no-connect for cost savings.
5. DSI_REXT – Connect an external 6.04 kΩ 1% If DSI is unused, the reference resistor may be populated
resistor to GND. if desired for manufacturability purposes, or left
no-connect for cost savings.
1. The TEST_MODE input is internally connected to an This input is reserved for Freescale manufacturing use.
on-chip pulldown device. The user can either float this
signal or tie it to GND.
3. VDD_FA and FA_ANA should be tied to GND. These inputs are reserved for Freescale manufacturing
use. Best practice is to tie them to ground to avoid floating
inputs.
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2-10 Freescale Semiconductor
Design Checklist
4. GPANAIO must be a no connect. This output is reserved for Freescale manufacturing use.
5. NC contacts are no connect and should be floated. Depending on the feature set, some versions of the IC
may have NC contacts connected inside the BGA.
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 2-11
Design Checklist
2 ≤1.21 kΩ 1%
2 ≤1.54 kΩ 0.5%
2 ≤2.32 kΩ 0.1%
4 ≤768 Ω 1%
4 ≤1 kΩ 0.5%
4 ≤1.5 kΩ 0.1%
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
2-12 Freescale Semiconductor
Design Checklist
Assuming the system can function properly with a reduced bus rate of 250 kbps, the following table
provides a possible I2C port usage table.
Port 1
Port 1
Port 3
Port 3
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Freescale Semiconductor 2-13
Design Checklist
0 30 1650
1 32 1546.875
2 36 1375
3 42 1178.571
4 48 1031.25
5 52 951.9231
6 60 825
7 72 687.5
8 80 618.75
9 88 562.5
A 104 475.9615
B 128 386.7188
C 144 343.75
D 160 309.375
E 192 257.8125
F 240 206.25
10 288 171.875
11 320 154.6875
12 384 128.9063
13 480 103.125
14 576 85.9375
15 640 77.34375
16 768 64.45313
17 960 51.5625
18 1152 42.96875
19 1280 38.67188
1A 1536 32.22656
1B 1920 25.78125
1C 2304 21.48438
1D 2560 19.33594
1E 3072 16.11328
1F 3840 12.89063
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2-14 Freescale Semiconductor
Design Checklist
20 22 2250
21 24 2062.5
22 26 1903.846
23 28 1767.857
24 32 1546.875
25 36 1375
26 40 1237.5
27 44 1125
28 48 1031.25
29 56 883.9286
2A 64 773.4375
2B 72 687.5
2C 80 618.75
2D 96 515.625
2E 112 441.9643
2F 128 386.7188
30 160 309.375
31 192 257.8125
32 224 220.9821
33 256 193.3594
34 320 154.6875
35 384 128.9063
36 448 110.4911
37 512 96.67969
38 640 77.34375
39 768 64.45313
3A 896 55.24554
3B 1024 48.33984
3C 1280 38.67188
3D 1536 32.22656
3E 1792 27.62277
3F 2048 24.16992
1
Shaded cells indicate frequency is outside of the range that guarantees operation.
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 2-15
Design Checklist
Tolerance
Interface
(± ppm)
Ethernet 50
HDMI 100
SATA 350
USB2.0 500
PCIe 300
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
2-16 Freescale Semiconductor
Design Checklist
1 These supplies must remain powered if boundary scan test needs to be done
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 2-17
Design Checklist
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
2-18 Freescale Semiconductor
Chapter 3
i.MX 6 Series Layout Recommendations
This chapter provides recommendations to assist design engineers with the correct layout of their i.MX 6
series-based system. The majority of the chapter discusses the implementation of the DDR interface, but
it also provides recommendation for power, the HDMI, SATA, LVDS, PCIe, USB, reference resistors, ESD
and related emissions.
This chapter uses the i.MX6DQ SABRE SD board as its reference for illustrating the key concepts. See
the i.MX6DQ SABRE SD board layout files as a companion to this chapter.
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 3-1
i.MX 6 Series Layout Recommendations
It is critical to maintain the recommended footprint of a 16 mils pad with a 20 mil open solder mask for
ease of fanout. In this case, the solder paste is the same as the pad with 16 mil, which allows an air gap of
15.496-mil between pads.
When using the Allegro tool, optimal practice is to use the footprint as created by Freescale. When not
using the Allegro tool, use the Allegro footprint export feature (supported by many tools). If export is not
possible, create the footprint as per the package mechanical dimensions outlined in the product data sheet.
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
3-2 Freescale Semiconductor
i.MX 6 Series Layout Recommendations
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 3-3
i.MX 6 Series Layout Recommendations
— Gray = vias
• Bottom layer
— Cyan = GND net
— Brown = power rails
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
3-4 Freescale Semiconductor
i.MX 6 Series Layout Recommendations
Figure 3-6. Example top layer impedance solution from PCB fabricator
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 3-5
i.MX 6 Series Layout Recommendations
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
3-6 Freescale Semiconductor
i.MX 6 Series Layout Recommendations
The DDR3 interface is one of the most critical interfaces for chip routing. It must have the controlled
impedance for the single ended traces be equal to 50 Ω and for the differential pairs be equal to 100 Ω.
The following figure shows the physical connection scheme for both top and bottom placement of the DDR
chips, showing the final placement of the DDR3 memory and the decoupling capacitors. The blue figure
shows the top layer and the red figure shows the bottom layer. It is very important to place the memory as
close to the processor as possible to reduce trace capacitance and keep the propagation delay to the
minimum. Follow the reference board layout as a guideline for memory placement and routing.
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 3-7
i.MX 6 Series Layout Recommendations
Address and Bank Clock length Match the signals ±25 mils of the value
specified in the length column
Routing by byte group requires better control of the signals of each group. It is also more difficult for
analysis and constraint settings. However, its advantage is that the constraint to match lengths can be
applied to a smaller group of signals. This is often more achievable once the constraints are properly set.
The following table explains the rules for routing the signals by byte group.
Table 3-3. DDR3 routing by byte group
Length
Chip signals Group Recommendations
Min Max
DRAM_SDCLK[1:0] Clock Short as possible 2.25 inches Match the signals ± 5 mils.
DRAM_SDCLK_B[1:0] 2.25 inches is recommended.
DRAM_A[15:0] Address Clock (min) – 200 Clock (min)1 Match the signals ± 25 mils.
DRAM_SDBA[2:0] and Command
DRAM_RAS DRAM_CAS
DRAM_SDWE
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i.MX 6 Series Layout Recommendations
Length
Chip signals Group Recommendations
Min Max
DRAM_D[7:0] Byte Group 1 — Clock (min) Match the signals of each byte group ± 25
DRAM_DQM0 mils.
DRAM_SDQS0 Match the differential signals of DQS ± 10
DRAM_SDQS0_B mils.
DRAM_CS[1:0] Control signals Clock (min) – 200 Clock (min) Match the signals ± 50 mils.
DRAM_SDCKE[1:0]
DRAM_SDODT[1:0]
1. Clock (min)—The shortest length of the clock group signals because this group has a ± 5 mil matching tolerance.
Finally, the impedance for the signals should be 50 Ω for single ended and 100 Ω for differential pairs.
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 3-9
i.MX 6 Series Layout Recommendations
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3-10 Freescale Semiconductor
i.MX 6 Series Layout Recommendations
The following figure shows the topology for the ADDR/CMD/CTRL signals. It has a tree topology. Note
the balanced T routing.
The routing for the data groups depends on the bus size. The following figure shows the point-to-point data
bus connection, with routing by byte group.
NOTE
i.MX 6Solo only uses the first two pairs of the 2 Bytes groups. All others are
disabled.
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Freescale Semiconductor 3-11
i.MX 6 Series Layout Recommendations
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3-12 Freescale Semiconductor
i.MX 6 Series Layout Recommendations
Color Meaning
Yellow Clocks
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 3-13
i.MX 6 Series Layout Recommendations
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3-14 Freescale Semiconductor
i.MX 6 Series Layout Recommendations
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Freescale Semiconductor 3-15
i.MX 6 Series Layout Recommendations
The following table shows the total etch of the signals for the byte 0 and byte 1 groups. The layout is an
example, using 2000 mils for the clock.
DRAM_D0 1025.349
DRAM_D1 1028.996
DRAM_D2 1028.752
DRAM_D3 1021.158
DRAM_D4 1021.930
DRAM_D5 1025.398
DRAM_D6 1025.564
DRAM_D7 1029.326
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3-16 Freescale Semiconductor
i.MX 6 Series Layout Recommendations
DRAM_DQM0 1028.555
DRAM_SDQS0 1023.419
DRAM_SDQS0_B 1023.373
DRAM_D8 648.862
DRAM_D9 654.371
DRAM_D10 652.653
DRAM_D11 653.712
DRAM_D12 650.961
DRAM_D13 648.433
DRAM_D14 649.588
DRAM_D15 651.781
DRAM_DQM1 653.106
DRAM_SDQS1 669.240
DRAM_SDQS1_B 669.736
DRAM_SDCLK0 2120.044
DRAM_SDCLK0_B 2118.283
DRAM_SDCLK1 2112.518
DRAM_SDCLK1_B 2112.829
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 3-17
i.MX 6 Series Layout Recommendations
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
3-18 Freescale Semiconductor
i.MX 6 Series Layout Recommendations
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 3-19
i.MX 6 Series Layout Recommendations
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3-20 Freescale Semiconductor
i.MX 6 Series Layout Recommendations
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 3-21
i.MX 6 Series Layout Recommendations
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
3-22 Freescale Semiconductor
i.MX 6 Series Layout Recommendations
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 3-23
i.MX 6 Series Layout Recommendations
The following table shows the total etch of the signals for the byte 0 and byte 1 groups.
DRAM_D0 1244.97
DRAM_D1 1252.82
DRAM_D2 1237.48
DRAM_D3 1242.95
DRAM_D4 1240.12
DRAM_D5 1254.37
DRAM_D6 1254.58
DRAM_D7 1238.18
DRAM_DQM0 1297.45
DRAM_SDQS0 1295.34
DRAM_SDQS0_B 1295.68
DRAM_D8 1103.69
DRAM_D9 1116.14
DRAM_D10 1105.01
DRAM_D11 1105.17
DRAM_D12 1120.4
DRAM_D13 1123.06
DRAM_D14 1105.72
DRAM_D15 1111.24
DRAM_DQM1 1152.16
DRAM_SDQS1 1158.48
DRAM_SDQS1_B 1162.29
DRAM_SDCLK0 4723.96
DRAM_SDCLK0_B 4681.95
DRAM_SDCLK1 4750.69
DRAM_SDCLK1_B 4699.00
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3-24 Freescale Semiconductor
i.MX 6 Series Layout Recommendations
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Freescale Semiconductor 3-25
i.MX 6 Series Layout Recommendations
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3-26 Freescale Semiconductor
i.MX 6 Series Layout Recommendations
Spacing the vias some mils apart facilitates the GND copper flowing in the plane. The following figures
show good practices of ground planes.
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 3-27
i.MX 6 Series Layout Recommendations
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3-28 Freescale Semiconductor
i.MX 6 Series Layout Recommendations
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 3-29
i.MX 6 Series Layout Recommendations
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3-30 Freescale Semiconductor
i.MX 6 Series Layout Recommendations
Layout
Signal Group Impedance
Tolerance (±)
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 3-31
i.MX 6 Series Layout Recommendations
The following figure shows the dimensions of a stripline and microstrip pair. Figure 3-32 shows the
differential pair routing.
• The space between two adjacent differential pairs should be greater than or equal to twice the space
between the two individual conductors.
• The skew between LVDS pairs should be within the minimum recommendation (± 100 mil).
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i.MX 6 Series Layout Recommendations
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 3-33
i.MX 6 Series Layout Recommendations
Figure 3-33 and Figure 3-34 show two examples of static routing where a match is achieved without
needing to tune one element of the differential pair.
The following figure shows the addition of a delay trace to one element of the differential pair to avoid
length mismatch (which reduces skew and phase problems). The green box marks the detail.
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
3-34 Freescale Semiconductor
i.MX 6 Series Layout Recommendations
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Freescale Semiconductor 3-35
i.MX 6 Series Layout Recommendations
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3-36 Freescale Semiconductor
Chapter 4
Requirements for Power Management
4.1 Power management requirements overview
This chapter provides the power requirements for the following i.MX 6 series families of processors:
• i.MX 6Quad
• i.MX 6Dual
• i.MX 6DualLite
• i.MX 6Solo
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 4-1
Requirements for Power Management
Supply
reg
Voltage Generated Power up
Voltage rail Supply reg current Notes
(V) by sequence
capability
(A)
VDDARM_IN SW1A/B 1.35 2.5 PF0100 1 Short these together with a shunt
for quad core operation. Cut shunt
VDDARM23_IN for dual core operation and connect
VDDARM23_IN to GND
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
4-2 Freescale Semiconductor
Requirements for Power Management
Supply
reg
Voltage Generated Power up
Voltage rail Supply reg current Notes
(V) by sequence
capability
(A)
NVCC_CSI SW4, VGEN4 or 1.8–3.3 1.0 or 0.35 PF0100 or 5 Depending on system needs, these
external external voltage domains can be supplied
NVCC_EIM 0, 1, 21 regulator regulator together or independently with
NVCC_ENET equal or different voltages and
regulators. Be sure to account for
NVCC_GPIO the current needs of the domains
and the current capability of the
NVCC_LCD
regulator when making this
NVCC_NANDF decision.
NVCC_SD1, 2
NVCC_SD3
NVCC_JTAG
PCIE_VPTX — — —
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 4-3
Requirements for Power Management
Supply
reg
Voltage Generated Power up
Voltage rail Supply reg current Notes
(V) by sequence
capability
(A)
1 For Solo and DualLite chips, these 3 voltage rails should be connected together to the same voltage value.
Quad and Dual chips can support three different EIM power rails.
2 These voltage domains are supplied by i.MX6 internal regulators.
3 VGEN6, which comes up in sequence 4, does not power any i.MX rails and therefore is not shown. See Table 4-2 for VGEN6.
The following table shows the PF0100 regulators that are available to supply the rest of the system
circuitry.
Supply Output voltage(V) Step size (mV) Maximum Load current (mA)
1 In Table 4-1, it was recommended to supply the NVCC_x voltage domains with SW4 or VGEN4. Depending on the decision,
one of them may not be available to supply the rest of the system circuitry.
LDO_ARM 1.1 —
LDO_SOC 1.2 —
LDO_PU 1.1 —
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4-4 Freescale Semiconductor
Requirements for Power Management
LDO_1P1 1.1 —
LDO_SNVS 1.1 —
LDO_USB 3.0 50
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Freescale Semiconductor 4-5
Requirements for Power Management
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4-6 Freescale Semiconductor
Requirements for Power Management
1
Choose the pullup voltage for the I2C lines based on the I2C channel chosen. For example, for the I2C3 channel,
the corresponding voltage domain is NVCC_GPIO.
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Freescale Semiconductor 4-7
Requirements for Power Management
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
4-8 Freescale Semiconductor
Chapter 5
Using the Clock Connectivity Table
This chapter provides a reference table of the root clock default speed and a list of the i.MX modules
available to exit stop mode.
PERCLK_CLK_ROOT 66
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Freescale Semiconductor 5-1
Using the Clock Connectivity Table
USDHC3_CLK_ROOT 198
USDCH4_CLK_ROOT 198
SSI2_CLK_ROOT 63.525
SSI3_CLK_ROOT 63.525
GPU3D_AXI_CLK_ROOT 270
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
5-2 Freescale Semiconductor
Using the Clock Connectivity Table
• USB
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Freescale Semiconductor 5-3
Using the Clock Connectivity Table
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5-4 Freescale Semiconductor
Chapter 6
Using the IOMUX Design Aid
This chapter provides users with the basic information required to use the IOMUX system design aid
(IOMux.exe). The IOMUX design aid facilitates the assignment of internal signals to external device
balls/pins by helping users:
• Record signal assignments for the supported i.MX device
• Identify conflicts, allowing them to be resolved in real time
• Add notes or comments for each signal to the list of recorded assignments
• Generate C code to configure the IOMUXC registers according to the user’s design
• Move signals to different modules to order configuration code into logical functions
Users can save design configurations for future use and/or export them for use in schematics or software
source code as supplementary documentation of a system.
The following figure shows a screenshot of the IOMUX application window with various areas labeled.
Figure 6-1. IOMUX tool for the i.MX6 families of applications processors
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 6-1
Using the IOMUX Design Aid
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
6-2 Freescale Semiconductor
Chapter 7
Configuring JTAG Tools
This chapter explains how to configure JTAG tools for debugging. The JTAG module is a standard JEDEC
debug peripheral. It provides debug access to important hardware blocks, such as the ARM® processor
and the system bus, which can give users access and control over the entire chip.
To prevent JTAG manipulation while allowing access for manufacturing tests and software debugging, the
i.MX 6 series processor incorporates a secure JTAG controller for regulating JTAG access. The secure
JTAG controller provides four different JTAG security modes, which are selected by e-Fuse configuration.
For more information about the security modes, see the “Security” section in the “System JTAG Controller
(SJC)” chapter of the relevant i.MX6 chip reference manual.
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Configuring JTAG Tools
NOTE
The ICE must be disconnected from any other target at this step.
3. Select the firmware update from the upside menu: RVI → Install Firmware Update
4. Select the following file (or an equivalent more recent version):
C:\Program Files\ARM\RVI\Firmware\4.2\23\ARM-RVI-4.3.0-1-base.rvi
5. Select “Continue” from the install update window and wait until the update is complete.
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Configuring JTAG Tools
NOTE
Be sure to use this path exactly, or the tool-chain configuration will not be
available from the Debugger-Connect to Target.
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Configuring JTAG Tools
5. Select your ICE from the list and press Connect (see Figure 7-1).
6. In the new window, choose Select Platform…
7. Expand the “Freescale” list and select iMX6 Q.
8. Save the file (File → Save).
9. Close the window.
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Configuring JTAG Tools
After finishing this procedure, you should see the following screen:
Add the correct amount of Cortex A-9 cores desired to access your CPUs.
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Configuring JTAG Tools
2. You are now at rvdebug.brd; if you have successfully completed your setup, it looks like the
following screenshot:
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Configuring JTAG Tools
3. Establish the connection to the core of your choice by using the Connect icon or the shortcut
CTRL+N.
You now have a new RVI configuration with four Cortex-A9 targets and the RealView Debugger up and
running. You can now use the RealView Debugger window to access a register, as shown in the
following figure.
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Figure 7-8 shows an example of using the RealView Debugger to access the IOMUX register
IOMUXC_SW_MUX_CTL_PAD_GPIO_0, whose address is 0x020E0220 and whose default value after
reset is 0x5.
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Configuring JTAG Tools
— CPU#2: 0x82154000
— CPU#3: 0x82156000
• For the i.MX6 Solo, CPU#0: 0x82150000.
• For the i.MX 6Dual and 6DualLite
— CPU#0: 0x82150000
— CPU#1: 0x82152000
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Configuring JTAG Tools
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Chapter 8
Avoiding Board Bring-up Problems
This chapter provides recommendations for avoiding typical mistakes when bringing up a board for the
first time. These recommendations consist of basic techniques that have proven useful in the past for
detecting board issues and addressing the three most typical bring-up pitfalls: power, clocks, and reset. A
sample bring-up checklist is provided at the end of the chapter.
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The following table illustrates how a sample voltage report table helps detect errors. The shaded cells in
the PMIC LDO2 row call your attention to the difference in the expected value and measured value, which
indicates a potential problem with that power rail.
Table 8-1. Sample voltage report
3.3 V discrete reg 3V3_DELAYED 3.35 3.334 SH1 Requires LDO3 to enable
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When checking crystal frequencies, use an active probe to avoid excessive loading. A parasitic probe
typically inhibits the 32.768 kHz and 24 MHz oscillators from starting up. Use the following guidelines:
• RTC_XTALI clock is running at 32.768 kHz (can be generated internally or applied externally).
• XTALI/XTALO is running at 24 MHz (used for the PLL reference).
• CLK1_P/N/CLK2_P/N can be used as oscillator inputs for low jitter special frequency sources.
• CLK1_P/N and CLK2_P/N are optional.
In addition to probing the external input clocks, you can check internal clocks by outputting them at the
debug signals CLKO1 and CLKO2 (iomuxed signals). See the CCM chapter in the chip reference manual
for more details about which clock sources can be output to those debug signals. JTAG tools (see
Chapter 7, “Configuring JTAG Tools”) can be used to configure the necessary registers to do this.
5V_MAIN
Feeds 3.3 V Reg
SNVS
SW1A/B
(VDDARM_IN)
POR_B
RESETBMCU
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SW1A/B
(VDDARM_IN)
SW1C
(VDDSOC_IN)
SW2
(VDDHIGH_IN)
VGEN2
(System 1.5V)
Findings &
Checklist Item Details Owner
status
1. Perform a visual inspection. Check major components to make sure nothing has been
misplaced or rotated before applying power.
2. Verify all i.MX6 voltage rails. Confirm that the voltages match the data sheet’s
requirements. Be sure to check voltages not only at the
voltage source, but also as close to the i.MX6 as possible
(like on a bypass capacitor). This reveals any IR drops on
the board that will cause issues later.
Ideally all of the i.MX6 voltage rails should be checked, but
VDD_ARM_IN and VDD_SOC_IN are particularly important
voltages. These are the core logic voltages and must fall
within the parameters provided in the i.MX6 data sheet.
VDD_SNVS_IN, NVCC_JTAG, and NVCC_DRAM are also
critical to the i.MX6 boot up.
Note: NVCC_LVDS2V5 must be powered when using the
chip DDR interface. This power input is used as the
Pre-Driver power source for the DDR I/O pads.
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Findings &
Checklist Item Details Owner
status
3. Verify power-up sequence. Verify that power on reset (POR_B) is de-asserted (high)
after all power rails have come up and are stable. See the
i.MX6 data sheet for details about power-up sequencing.
4. Measure/probe input clocks (32 kHz, Without a properly running clock, the i.MX6 will not function
24MHz, others). properly.
5. Check JTAG connectivity (RV-ICE). This is one of the most fundamental and basic access points
to the i.MX6 to allow the debug and execution of low level
code.
Note: The following items may be worked on in parallel with other bring up tasks.
Access internal RAM. Verify basic operation of the i.MX6 in system. The on-chip
internal RAM starts at address 0090_0000h and is
256 Kbytes in density. Perform a basic test by performing a
write-read-verify to the internal RAM. No software
initialization is necessary to access internal RAM.
Verify CLKO outputs (measure and This ensures that the corresponding clock is working and
verify default clock frequencies for that the PLLs are working.
desired clock output options) if the board Note that this step requires chip initialization, for example
design supports probing of the CLKO via the JTAG debugger, to properly set up the IOMUX to
pin. output CLKO and to set up the clock control module to
Note: output the desired clock. See the reference manual for more
details.
Measure boot mode frequencies. Set This verifies the specified signals’ connectivity between the
the boot mode switch for each boot i.MX6 and boot device and that the boot mode signals are
mode and measure the following properly set.
(depending on system availability): See the “System Boot” chapter in the reference manual for
• NAND (probe CE to verify boot, details about configuring the various boot modes.
measure RE frequency)
• SPI-NOR (probe slave select and
measure clock frequency)
• MMC/SD (measure clock frequency)
Run basic DDR initialization and test 1. Assuming the use of a JTAG debugger, run the DDR
memory. initialization and open a debugger memory window pointing
to the DDR memory map starting address.
2. Try writing a few words and verify if they can be read
correctly.
3. If not, recheck the DDR initialization sequence and
whether the DDR has been correctly soldered onto the
board.
It is also recommended that users recheck the schematic to
ensure that the DDR memory has been connected to the
i.MX6 correctly.
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Chapter 9
Understanding the IBIS Model
This chapter explains how to use the IBIS (input output buffer information specification) model, which is
an Electronic Industries Alliance standard for the electronic behavioral specifications of integrated circuit
input/output analog characteristics. The model is generated in ASCII text format and consists of multiple
tables that capture current vs. voltage (IV) and voltage vs. time (VT) characteristics of each buffer. IBIS
models are generally used to perform PCB-board-level signal integrity (SI) simulations and timing
analyses.
The IBIS model’s features are as follows:
• Supports fast chip-package-board simulation, with SPICE-level accuracy and faster than any
transistor-level model
• Provides the following for portable model data
— I/O buffers, series elements, terminators
— Package RLC parasitics
— Electrical board description
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[Comment char] No Change the comment character. Defaults to the pipe (|) character
[File Name] Yes Name of this file. All file names must be lower case. The file name extension for an IBIS file is .ibs
[File Rev] Yes The revision level of this file. The specification contains guidelines for assigning revision levels.
[Source] No The source of the data in this file. Data is taken from a simulation and validated on the board.
[Component] Yes The name of the component being modeled. Standard practice has been to use the industry
standard part designation. Note that IBIS files may contain multiple [Component] descriptions.
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[Package] Yes This keyword contains the range (minimum, typical and maximum values) over which the
packages’ lead resistance, inductance, and capacitance vary (the R_pkg, L_pkg, and C_pkg
parameters).
[Pin] Yes This keyword contains the pin-to-buffer mapping information. In addition, the model creator can
use this keyword to list the package information: R, L, and C data for each individual pin (R_pin,
L_pin, and C_pin parameters).
[Package No If the component model includes an external package model (or uses the [Define Package Model]
Model] keyword within the IBIS file itself), this keyword indicates the name of that package model.
[Pin Mapping] No This keyword is used if the model creator wishes to include information on buffer power and ground
connections. This information may be used for simulations involving multiple outputs switching.
[Diff Pin] No This keyword is used to associate buffers that should be driven in a complementary fashion as a
differential pair.
[Model This keyword provides a simple means by which several buffers can be made optionally available
Selector] for simulation at the same physical pin of the component.
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Keyword Comment
[Temperature Range] The temperature range over which the min, typ and max IV and switching data have been
gathered.
[Voltage Range] The range over which Vcc is varied to obtain the min, typ and max pullup and power clamp data.
[Ramp] VT information. For more details, see Section 9.4.2, “VT information.”
[Rising Waveform]
[Falling Waveform]
[Test Data] VT golden model information. For more details, see Section 9.4.3, “Golden Model VT information.”
[Rising Waveform Near]
[Rising Waveform Far]
[Falling Waveform Near]
[Falling Waveform Far]
[Test Load]
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Understanding the IBIS Model
9.4.1 IV information
IV information is composed of four Current-over-Voltage tables: [Pullup], [Pulldown], [GND_clamp], and
[Power_clamp]. Each look-up table describes a different part of the IO cell model, as shown in Table 9-1.
9.4.2 VT information
The following table defines the keywords that provide the information about an output or I/O buffer, and
Example 9-3 shows what they look like in an IBIS file.
Table 9-4. Ramp and waveform keywords
[Ramp] Yes Basic ramp rate information, given as a dV/dt_r for rising edges and dV/dt_f for falling
edges, see the following equation.
dV 20 % to 80% voltage swing
------- = ----------------------------------------------------------------------------------
dt time taken to swing above voltage
Note: The dV value is the 20% to 80% voltage swing of the buffer when driving into
the specified load, R_load (for [Ramp], this load defaults to 50). For CMOS
drivers or I/O buffers, this load is assumed to be connected to the voltages
defined by the [Voltage Range] keyword for falling edges and to ground for
rising edges.
[Rising Waveform] No The actual rising (low to high transition) waveform, provided as a VT table.
[Falling Waveform] No The actual falling (high to low transition) waveform, provided as a VT table.
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The [Ramp] keyword is always required, even if the [Rising Waveform] and [Falling Waveform] keywords
are used. However, the VT tables under [Rising Waveform] and [Falling Waveform] are generally
preferred to [Ramp] for the following reasons:
• VT data may be provided under a variety of loads and termination voltages
• VT tables may be used to describe transition data for devices as they turn on and turn off.
• [Ramp] effectively averages the transitions of the device, without providing any details on the
shapes of the transitions themselves. All detail of the transition ledges would be lost.
The VT data should be included under two [Rising Waveform] and two [Falling Waveform] sections, each
containing data tables for a Vcc-connected load and a Ground-connected load (although other loading
combinations are permitted).
The most appropriate load is a resistive value corresponding to the impedance of the system transmission
lines the buffer will drive (own impedance). For example, a buffer intended for use in a 60 Ω system is
best modeled using a 60 Ω load (R_fixture).
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Understanding the IBIS Model
[Test Data] No • Provides a set of golden waveforms and references the conditions under which
they were derived.
• Useful for verifying the accuracy of behavioral simulation results against the
transistor level circuit model from which the IBIS model parameters originated.
[Rising Waveform Near] Yes Current-Over-Voltage tables, for far and near portions of the golden model as
[Rising Waveform Far] described by Figure 9-3.
[Falling Waveform Near]
[Falling Waveform Far]
[Test Load] Yes • Defines a test load network and its associated electrical parameters for reference
by golden waveforms under the [Test Data] keyword.
• If Test_load_type is Differential, the test load is a pair of the circuits shown in . If the
R_diff_near or R_diff_far subparameter is used, a resistor is connected between
the near or far nodes of the two circuits.
• If Test_load_type is Single_ended, R_diff_near and R_diff_far are ignored.
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Understanding the IBIS Model
DDR write models ("_mio" suffix) have no simulated ODT, as ODT is disabled during write. Write
models' DS parameter is meaningful and changes to describe the different levels of drive strength.
DDR read models ("_mi" suffix) have no meaningful DS parameter, as no driving happens during read.
Read models’ ODT parameter is meaningful and changes to describe different levels of ODT impedance.
DDR Protocol Selected according to the used DDR. DDR IO voltage level is selected
accordingly.
DDR IO Type Controlled by the IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE[19:18] register
in IOMUXC (IOMUX controller) DDR_SEL bits, to select between DDR3 &
LPDDR2.
Drive strength Controlled by bits [5:3] (DSE) of the following registers in IOMUXC (IOMUX
controller):
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_x (2 registers)
IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
IOMUXC_SW_PAD_CTL_PAD_GRP_ADDDS
IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKEx (2 registers)
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODTx (2 registers)
IOMUXC_SW_PAD_CTL_PAD_GRP_CTLDS
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQSx (8 registers)
IOMUXC_SW_PAD_CTL_PAD_DRAM_BxDS (8 registers)
IOMUXC_SW_PAD_CTL_PAD_DRAM_DQMx (8 registers)
ODT value Controlled by bits [18:16], [14:12], [10:8], and [6:4] in MPODTCTRL register of
MMDC.
Example 9-4. [Model Selector] DDR in IBIS file
See the register description in the IOMUXC chapter in the chip reference manual for further details about
this model.
9.5.1.2 RGMII
This model has the following parameters:
• RGMII voltage
• Drive strength
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Understanding the IBIS Model
The IBIS model name is composed from the parameters’ values as follows:
rgmii_sel11_ds<drive_strength>_mio
Voltage Level IBIS currently supports only the 2.5 V option. 2.5 V is applied to NVCC_RGMII.
No further register programing is required.
Drive strength Controlled by bits [5:3] (DSE) of the following registers in IOMUXC (IOMUX
controller):
IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC
IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL
IOMUXC_SW_PAD_CTL_PAD_RGMII_TDx (4 registers)
IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC
IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL
IOMUXC_SW_PAD_CTL_PAD_RGMII_RDx (4 registers)
IO Type Regardless of the voltage level, he ddr_sel of
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII should always be set to
‘11’.
Example 9-5. [Model Selector] RGMII in IBIS file
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Understanding the IBIS Model
See the register description in the IOMUXC chapter in the chip reference manual for further details about
this model.
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CSI_D2P HDMI_D2P
CSI_D3M HDMI_DDCCEC
CSI_D3P HDMI_HPD
DSI_CLK0M
DSI_CLK0P
DSI_D0M
DSI_D0P
DSI_D1M
DSI_D1P
NOTE
In rev3 of the i.MX6 IBIS, some of the above unsupported pins are
described as “GPIO” cells. These are no more than placeholders and cannot
be used for signal modeling.
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Understanding the IBIS Model
Correlation Level A means for categorizing I/O buffer characterization data based on how much the
modeling engineer knows about the processing conditions of a sample component
and which correlation metric he or she used.
All models (GPIO, DDR, LVDS, MLB) have passed the following checks:
• IBISCHK without errors or unexplained warnings
• Data for basic simulation checked
• Data for timing analysis checked
• Data for power analysis checked
• Correlated against Spice simulations
Validation reports can be provided upon demand.
9.8 References
Consult the following references for more information about the IBIS model.
• IBIS Open Forum (http://www.eda.org/ibis/)
The IBIS Open Forum consists of EDA vendors, computer manufacturers, semiconductor vendors,
universities, and end-users. It proposes updates and reviews, revises standards, and organizes
summits. It promotes IBIS models and provides useful documentation and tools.
• IBIS specification (http://eda.org/pub/ibis/ver5.0/)
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Chapter 10
Using the Manufacturing Tool
10.1 Overview
The i.MX manufacturing tool is designed to program firmware onto storage devices such as NAND or eSD
through the EVK and preload the data area with media files in an efficient and convenient manner. It is
intended for Freescale Semiconductor customers or their OEMs who plan to mass manufacture
i.MX-based products.
The application is not designed to test the devices or to diagnose manufacturing problems. Devices
initialized with this application still need to be functionally verified.
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Chapter 11
Using BSDL for Board-level Testing
11.1 BSDL overview
Boundary scan description language (BSDL) is used for board-level testing after components have been
assembled. The interface for this test uses the JTAG pins. The definition is contained within IEEE Std
1149.1.
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The appearance of ”linkage” in a pin’s file implies that the pin cannot be used with boundary scan. These
are usually power pins or analog pins that cannot be defined with a digital logic state.
e‐Fuse bits
JTAG_SMODE[1:0] [0:0] JTAG enable mode
[0:1] Secure JTAG mode
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Chapter 12
Using the RMII Interface
12.1 Overview
This chapter provides supporting instructions for the use of the i.MX 6 series Ethernet RMII interface.
NOTE
This chapter only covers the required hardware and register settings.
Modifications to the Ethernet driver or its initialization code are beyond its
scope. For this information, see your BSP documentation.
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Using the RMII Interface
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Using the RMII Interface
Figure 12-1 provides a reference schematic, which shows the connections required to use the RMII
interface. These signal connections are generally self-explanatory or explained in the chip reference
manual. However, there are some required modifications.
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Using the RMII Interface
GPR1[21] (ENET_CLK_SEL) = 1
IOMUX
GPIO_16
ANATOP
PHY
X
ENET
IOMUXC_SW_MUX_CTL_PAD_GPIO16[4] SION =
Note that the block labeled “ANATOP” is really the Analog Ethernet PLL. See your chip reference manual
for its control register figure. Bits 1–0 of CCM_ANALOG_PLL_ENETn control the frequency fed to the
Ethernet MAC and should be set to 01b to obtain 50 MHZ.
To use GPIO_16 as the RMII reference clock source, use the following:
• Set mode to ALT2 (MUX_MODE[2:0] = 010).
• Set the SION bit. Note that this is not required because the function setting controls the signal path,
but it is good practice as it reminds the user that the clock needs to fed back into the Ethernet MAC.
• For the internal clock case, set GPR1[21].
GPR1[21] controls the actual clock source.
• When cleared, it obtains the ENET Tx reference clock from a pad (external OSC for both external
PHY and internal controller).
• When set, it obtains the ENET Tx reference clock from ANATOP (loopback through pad) and
sends out to the external PHY.
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The Daisy Chain register also needs to be set correctly to force the input to use the right pin. Note that there
is a subtle difference between the i.MX 6Quad/6Dual families and the i.MX 6DualLite/6Solo families that
affects the correct setting:
• For i.MX6Quad/6Dual—To use GPIO_16, set DAISY[0] = 1. If DAISY[0] is left at its reset value
(0b), RGMII_TX_CTL will be used instead. See the Select Input Register
(IOMUX_ENET_REF_CLK_SELECT_INPUT) in the IOMUXC chapter of the i.MX
6Dual/6Quad Reference Manual (IMX6DQRM), available at www.freescale.com
• For i.MX 6Solo/6DualLite—To use GPIO_16, leave the value of DAISY[0] at is reset value (0b).
To use RGMII_TX_CTL, set DAISY[0] = 1.
For further information, see the “DAISY (IOMUXC_ENET_REF_CLK_SELECT_INPUT)” section in
the “IOMUX Controller (IOMUXC)” chapter of your chip reference manual.
Note that while you can use the default pad settings as shown in the “SW_PAD_CTL
(IOMUXC_SW_PAD_CTL_PAD_GPIO16)” section in the IOMUX controller chapter, it may be
desirable to set the Slew Rate Field, SRE[0], to Fast (SRE[0] = 1).
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
12-6 Freescale Semiconductor
Using the RMII Interface
GPR1[21] (ENET_CLK_SEL) = 0
IOMUX
GPIO_16
ANATOP
PHY
X
Oscillator
ENET
IOMUXC_SW_MUX_CTL_PAD_GPIO16[4] SION = 1
Figure 12-4 shows how to use an external clock. This configuration is almost identical when using an
external oscillator or the RMII PHY to supply a clock. The only required modification to an RMII PHY
instead of the external oscillator is to clear GPR1[21] (GPR1[21] = 0) to select the external clock input.
All other settings remain the same.
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor 12-7
Using the RMII Interface
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
12-8 Freescale Semiconductor
Appendix A
Development Platforms
This appendix provides a complete list of the development platforms that are available from Freescale to
support the following i.MX 6 families of processors:
• i.MX 6Quad
• i.MX 6Dual
• i.MX 6DualLite
• i.MX 6Solo
You can use these tables as a quick guide for finding the best development platform for your needs. Note
that although these development platforms are based on a specific product family, they will work with any
of the i.MX product families listed above.
• 1 Gbyte DDR3
• SPI Nor
• eMMC Socket
• SD Card Socket
• SATA
• LVDS Ports 0 & 1
• HDMI
• Port of CSI CMOS Sensor (camera)
• MIPI CMOS Sensor
• MIPI Display Port
Features • Parallel Display Port
• TouchScreen
• Audio CODEC
• Ethernet
• 3 Axis Accelerometer
• Barometer
• Digital eCompass
• Aux SDIO Socket
• CAN Port (optional)
• Mini PCIe
•
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor A-1
Development Platforms
• i.MX 6Quad
Version i.MX used
• i.MX 6DualLite
• 1Gbyte DDR3
• SPI Nor
• eMMC Socket
• SD Card Socket
• SATA
• LVDS Ports 0 & 1
• HDMI
• Port of CSI CMOS Sensor (camera)
• MIPI CMOS Sensor
• MIPI Display Port
• EPD Display Port
• Parallel Display Port
Features
• TouchScreen
• Audio CODEC
• Ethernet
• Light Sensor
• 3 Axis Accelerometer
• Barometer
• Digital eCompass
• Aux SDIO Socket
• CAN Port (optional)
• Mini PCIe
• GPS Receiver
• Battery Charger Options
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
A-2 Freescale Semiconductor
Appendix B
Revision History
Table B provides a revision history for this document.
Rev.
Date Substantive Change(s)
Number
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
Freescale Semiconductor BB-1
Revision History
Hardware Development Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite Applications Processors, Rev. 1
B-2 Freescale Semiconductor