www.SeminarsTopics.

com

Welcome To www.SeminarsTopics.com For Download Latest Seminar Topics.

We are adding More Research Seminar Topics Please keep visiting

www.SeminarsTopics.com for Regular Updates

www.SeminarsTopics.com
SeminarsTopics.com is now a true collaboration of the best minds in education,
with more than 1000 students/ Professors, subject experts and editors
contributing to it every day.

Students/Professors are most welcome to contribute here by Uploading Seminar

Thanks
FPGA based wireless control system for Robotic applications 2017-2018

CHAPTER 1

INTRODUCTION TO FPGA

FPGA stands for Field Programmable Gate Array. An FPGA is an integrated circuit
(IC) that can be programmed and configured by the embedded system developer in the field
after it has been manufactured. FPGA is a semi-conductor Device which is not limited to any
pre defined hardware function; it is rather highly flexible in its functionality and may be
configured by the embedded system developer according to his design requirements. FPGAs
use pre-built logic blocks and programmable routing channels for implementing custom
hardware functionality depending upon how embedded system developer configure these
devices. The FPGAs are programmed and configured using hardware description
languages(HDL) like Verilog and VHDL similar to that used for an application-specific
integrated circuit(ASIC). FPGAs give a lot of flexibility to the embedded systems developer.
FPGA may easily be reconfigured and reprogrammed in the field according to the new
features and end-user’s requirements.

In the fast growing world, real time controlling of any robotic application is very
important. The idea behind developing the system is to make a single control system to
control multiple robotic applications simultaneously because individual controller for every
application is very difficult to synchronize and development of logic for every different
application is also very time consuming. So the system is to be developed such that it can
control any robotic application from remote area simultaneously in real time. Communication
interfaces are also to be developed using which user can easily control any application
remotely. The whole control logic should be inside the system, so the selection of controller
is important. It should be such that it contains large number of memory storage inside it, so
more numbers of logics can be added within it. For general applications, microcontroller is
good enough but critical applications would need real-time processing that is time critical. In
this case, FPGA would be the best solution.

FPGA are used for time critical applications like real time multi motor control in
robotic arms, any multi-motor precision application or any parallel processing application.

Dept. Of ECE, SCTIT Page 1

FPGA based wireless control system for Robotic applications 2017-2018

1.1. HISTORY OF FPGA

The FPGA industry sprouted from programmable read only memory(PROM) and
programmable logic devices(PLDs).PROM and PLDs both had the option of being
programmed in batches in a factory or in a field(field programmable)however programmable
logic was hard-wired between logic gates.

In the late 1980s the naval service warfare department funded an experiment proposed
by Steve Casselmanto develop a computer that would implement 600,000 reprogrammable
gates. Casselman was successful and a patent related to the system was issued in 1992.

Xilinx co-founders Ross Freeman and Bernerd Vonderschmitt invented the first
commercially viable field programmable gate array in 1985- the XC2064. [10]The XC2064
had programmable gates and programmable interconnects between gates, the beginnings of a
new technology in market.

The XC2064 boasted a mere 64 configurable logic blocks (CLBs), with two 3-input
lookup tables (LUTs). More than 20 years later, Freeman was entered into the national
Inventors Hall of Fame for his invention. Xilinx continued unchallenged and quickly growing
from 1985 to the mid-1990s.

The 1990s were an explosive period of time for FPGAs, both in sophistication and the
volume of production. In the early 1990s, FPGAs were primarily used in telecommunication
and networking.

Dept. Of ECE, SCTIT Page 2

FPGA based wireless control system for Robotic applications 2017-2018

1.2. MAJOR MANUFACTURERS

With the top two FPGA companies taking up 89% of the FPGA market, you can be
forgiven for thinking there was no one else out there. Xilinx and Altera have done a good job
of defending the duopoly but a few companies are gradually winning market share by
targeting specific applications and sub-markets. Here is a list of the top 5 FPGA companies.

1.2.1 Xilinx

The leader in FPGAs for many years, Xilinx has a good range of FPGAs in terms of
cost and performance. In recent years, the popular Spartan series has covered the low-to-mid-
end market while the Virtex series has covered the high-end. Recently, Xilinx released the
“7” family of FPGAs which are built on 28-nm process and for the first time introduced the
Artex-7 and Kintex-7 series which provide better coverage of the lower and mid-end
applications previously covered by the Spartan series. The Kintex-7 recently won the “Highly
Commended Prize” Semiconductor of the year award for 2011.

1.2.2 Altera

The Altera FPGAs cover the low, mid and upper end markets with the Cyclone, Arria
and Stratix series respectively. The most recent offering from Altera is the Cyclone-V, Arria-
V and Stratix-V, all build on 28-nm process technology.

Larger than Xilinx in market value, Altera has made great progress in winning market
share in recent years. Many people would say that their software tools are much better than
those of Xilinx which has likely been an important factor in their success.

1.2.3. Lattice Semiconductor

Lattice Semiconductor tackles the low-power and low-cost market for FPGAs. They
market their products as the “high-value FPGAs” of the industry, providing best performance
per cost. With the explosion in portable electronics, this has been a good strategy for Lattice.
Lattice claims to have the industry’s lowest power and price SERDES-capable FPGA:
LatticeECP3.

Dept. Of ECE, SCTIT Page 3

FPGA based wireless control system for Robotic applications 2017-2018

1.3. ARCHITECTURE AND WORKING

The most common FPGA architecture consists of an array of logic blocks called
Configurable Logic Block, CLB or Logic Array Block, LAB,(depending on vendor), I/O
pads, and routing channels.

Generally, all the routing channels have the same width(number of wires). Multiple I/O
pads may fit into the height of one row or the width of one column in the array.

An application circuit must be mapped into an FPGA with adequate resources. While
the number of CLBs/LABs and I/Os required is easily determined from the design, the
number of routing tracks needed may vary considerably even among designs with the same
amount of logic.

For example, a crossbar switch requires much more routing than a systolic array with
the same gate count. Since unused routing tracks increase the cost of the part without
providing any benefit, FPGA manufacturers try to provide just enough tracks so that most
designs that will fit in terms of lookup tables (LUTs) and IOs can be reduced. This is
determined by estimates such as those derived from Rent’s rule or by experiments with
existing designs.

Fig 1.3: Structure of FPGA

Dept. Of ECE, SCTIT Page 4

FPGA based wireless control system for Robotic applications 2017-2018

1.3.1. ARCHITECTURE

1.3.1.1. CLB: A CLB is used to implement custom combinational or sequential logic. It is

composed of a lookup table (LUT) controlled by 4 inputs to implement combinational logic
and a D-Flip-Flop for sequential logic. A MUX is used to select between using the output of
the combinational logic directly and using the output of the Flip-Flop.

Once the CLB slices have been configured to implement logical functions they have to
be connected to implement bigger logical function. This is realized by programmable
interconnect points (PIP) showed at the right side in figure 1. It is a pass through transistor.
The gate of the transistor is connected to the memory. If that memory bit is set to one the
ends of the transistor are logically connected, otherwise no connection is made. Therefore
different connection can be achieved by loading the memory.

Fig 1.3.1.1: Configurable Logic Block

1.3.1.2. IOB: The Input/output block makes it possible to connect the FPGA to the other
elements of the application. Input/output blocks are used to get the signals into the FPGA and
out of the FPGA. Each IOB can be used as an input and output depending on the state of the
output enable (OE). If output enable (OE) is set to one the IOB acts as an output, otherwise as
an input.

Dept. Of ECE, SCTIT Page 5

FPGA based wireless control system for Robotic applications 2017-2018

Fig 1.3.1.2: Input Output Block

1.3.1.3. Interconnect: Interconnect is essential for writing between CLBs and from IOBs to
CLBs. The CLBs are connected column-wise and row-wise. At the intersections of columns
and rows are programmable switch matrices (PSM). In this figure the output of one CLB is
connected with the inputs of two other CLBs.

Fig 1.3.1.3: Programmable Interconnect

Dept. Of ECE, SCTIT Page 6

FPGA based wireless control system for Robotic applications 2017-2018

The signal passes through three PIPs and two PSMs. While the PSMs make the FPGA
versatile, they slow down the signals. Therefore FPGA implementation becomes considerable
slower than their ASIC counterparts. Therefore FPGA designers added many other
interconnect in addition to PIPs and PSMs.

In general, a logic block (CLB or LAB) consists of a few logical cells (called ALM,
LE, Slice etc.). A typical cell consists of a 4-input LUT, a full adder (FA) and a D-type Flip-
flop, as shown below.

The LUTs are in this figure split into two 3-input LUTs. In normal mode those are
combined into a 4-input LUT through the left MUX. In arithmetic mode, their outputs are fed
to the full adder. The selection of mode is programmed into the middle multiplexer.

The output can be either synchronous or asynchronous, depending on the programming

of the MUX to the right, in the figure example. In practice, entire or parts of the full adder are
put as functions into the LUTs in order to save space.

Fig 1.4: Simplified Example

1.4. FPGA IMPLEMENTATION TECHNOLOGIES

FPGAs are not programmed directly. Synthesis tools translate the code into bit stream,
which is downloaded to the configuration memory of the FPGA. Commonly, hardware
description languages (HDL) are used to configure the device. But resent trends also offer the
possibility to high level languages. Furthermore, there are library based solutions which are
optimized for a specific device.

Dept. Of ECE, SCTIT Page 7

FPGA based wireless control system for Robotic applications 2017-2018

1.4.1. Programming Technologies

FPGAs can be considered to be building bricks which allow desired customization of
the hardware. The FPGA’s are available in various flavours based on the programming
technology used. These may be programmed using:
1.4.1.1. Antifuse Technology, which can be programmed only once. Devices
manufactured by Quicklogic are examples of this type. Configuration is done by burning a
set of fuses. These act as replacements for Application Specific ICs (ASIC) and used in
places where protection of intellectual property is top priority.
1.4.1.2. Flash Technology based programming, like devices from ACTEL. The FPGA
may be reprogrammed several thousand times, taking a few minutes in the field itself for
reprogramming and has non-volatile memory.
1.4.1.3. SRAM Technology based FPGAs, the currently dominating technology
offering unlimited reprogramming and very fast reconfiguration and even partial
reconfiguration during operation itself with little additional circuitry. Most companies like
ALTERA, ACTEL, ATMEL and XILINX manufacture such devices.

1.4.2 Hardware Description Language

Using a HDL is the most common approach to configure a FPGA. There are two
dominating languages, VHDL and Verilog. Both languages have the power of international
standards and working groups behind and are similar powerful. VHDL was developed in the
1980s.
Verilog was originally a C-like programming language to model hardware and late
became IEEE standard like VHDL. The language supports different levels of abstraction, but
most configurations are done at the register transfer level (RTL).
The design resembles soft development more than hardware development, but there are
big differences. Software programs have a sequential execution model and the correctness of
the program depends on the sequential executed commands. Decision points are very
common. Furthermore, programmer does not have to care about data flow between registers
and memory.
Hardware design consists of several block of hardware running in parallel. The designer
tries to avoid decision points, because of performance reasons. The wires for data movement
have to be explicitly written on the FPGA.

Dept. Of ECE, SCTIT Page 8

FPGA based wireless control system for Robotic applications 2017-2018

CHAPTER 2
BLOCK DIAGRAM

Fig 2: FPGA Based wireless control system

The main concept to build the system is to generate logic inside FPGA for proper
selection of address signal and data signal to control any kind of robots simultaneously in
robotic applications. Conceptual process flow is shown in the figure which contains the
required basic blocks. These blocks are generated in Verilog language to load the logic in
FPGA chip.

For ease of use, the data is sent from PC. For that, Serial interfacing is done which
receives the data serially and convert it to 8 bit binary numbers. Received 8 bit binary
numbers are stored in 8 bit latch. Here 8 bit latch is used to store the desired received data for
further use. From 8 bit latched output, all bits are separated to access more number of ports
using less control signal. From 8 bits of latch, 3 bits go into 3to8 decoder as a data and 4th bit
enables that decoder. Likewise, other 3 bits go into the other 3to8 decoder as a data and 8th
bit enables that decoder. Output of the decoder is used to enable PWM module for DC motor
and other signals are the input control signals to drive the DC motor. Other decoder's output
Dept. Of ECE, SCTIT Page 9
FPGA based wireless control system for Robotic applications 2017-2018

is used to enable the PWM module for Servo motor and other signals are the input control
signals. PWM modules have separate logic for DC motors and Servo motors. As per the user
input, it can change the values of respective signals.

Whenever any robot is to be remotely controlled through the PC via wireless module
then serial interfacing is very important to communicate between them. To control the robot
through PC, RS232 interfacing is done. For example, Spartan 3E FPGA kit has on-board
DTE and DCE DB9 port and RS232 voltage translator IC in the kit. The data signal is
transmitted from PC and received by the FPGA chip using pin 2 and pin 3 of the DB9
connector respectively.

2.1. WIRELESS INTERFACE USING ZIGBEE MODULE

To interface FPGA with robotic applications, wireless module ZigBee is used. Two
modules are used in experiment. From two, one is Coordinator which works as transmitter
and another is End device which works as Receiver. Coordinator is attached with PC and End
device is attached with robotic application. Signal is transmitted to robot from PC through
coordinator ZigBee and received by end device ZigBee. Robot is controlled as per the
command given from PC and logic developed inside the FPGA chip.

Every key pressing of PC represents particular ASCII values which are transmitted through
coordinator ZigBee and it is wirelessly received end device ZigBee. End device ZigBee sends
the RS232 IC of FPGA board and it sends the data to the FPGA chip through voltage
translator. FPGA has control logic of PWM signal generation module. So whenever
respectively key is sent through the PC, it will be received by FPGA chip and will be sent to
robot from the digital I/O port. Any action/movement can be given to robot by changing just
the logic in the FPGA. Using this concept, any robot can be controlled by FPGA through
wireless module.

Fig 2.1: ZigBee Module

Dept. Of ECE, SCTIT Page 10

FPGA based wireless control system for Robotic applications 2017-2018

2.2. PWM SIGNAL GENERATION MODULE

PWM is abbreviation of Pulse Width Modulation. It is also known as the duty-cycle
variation method. This method is commonly used in speed control of motors. "Pulse” is
meant by an electromagnetic wave or modulation. "Width Modulation” is meant by to adjust
to or keep in proper measure or proportion the width of the pulse with respect to the
frequency of the wave. The duty cycle is defined as the percentage of digital ‘high’ to digital
‘low’ plus digital ‘high’ pulse-width during a PWM period.

Fig 2.2: PWM block diagram

The block diagram of PWM module which is developed inside the FPGA to drive the
motor with the help of driver circuit. The architecture of the PWM part of the module
consists of two registers, an up counter and on board clock. One of the two registers is to hold
the PWM duty cycle value, which is the ratio of ON/OFF time determining the PWM
waveform. The other register is to hold the PWM period data, which controls the duration of
a complete ON/OFF cycle. The values in the two registers are accessible via serial interfacing
and can be updated.

Up and down counters are used to count only when enabled and the Toggle flip flop toggles
every time there is a final count from any of the enabled counters. When a data is loaded in
the duty cycle register, the down counter begins to count down from high value to zero.
When it crosses zero, the final count goes high, which toggles the PWM output to high.
Every time the final count goes high it triggers the duty cycle value to be re-loaded and the
Dept. Of ECE, SCTIT Page 11
 FPGA based wireless control system for Robotic applications 2017-2018

Up counter is enabled and the value is counted from zero to the high value. Once the Up-
counter reaches the final count, it again triggers the flip-flop to toggle the PWM output.
When a particular duty cycle value is loaded into the register, the PWM module will generate
the corresponding PWM signal and send it through the on-board General Purpose Input
Output (GPIO) pin. These PWM signals are then given to drive the motor.

2.3. TRANSMITTER AND RECEIVER MODULE

ROBOTIC
APPLICATIONS

TRANSMITTER MODULE

RECEIVER MODULE

FIG 2.3: Experimental set up

The overall system configuration of the experimental setup and Spartan 3E FPGA
board is the central piece with wireless end device module and robotic application with
required motor driver circuit attached. The board has a XC3s500E FPGA chip on it The
GPIO pins on the board are directly connected to the FPGA device.

PWM module is implemented inside the FPGA chip in such a way that it can directly
access the GPIO pins, and thus through the driver card, it drives robot. H-bridge circuit is

Dept. Of ECE, SCTIT Page 12

FPGA based wireless control system for Robotic applications 2017-2018

used as DC motor driver circuit. The PWM outputs from the GPIO pins are fed into the H-
bridge and then to drive a DC motor of robot.

Dept. Of ECE, SCTIT Page 13

FPGA based wireless control system for Robotic applications 2017-2018

CHAPTER 4

RESULTS AND DISCUSSIONS

The simulation waveforms are measured with the help of simulation tool and the results
show that as per the command given, signals can be properly selected and addressed to the
particular output port with 40ns delay. Here for DC motor selection, when '1' and '0' are
pressed then it gives forward output to respective output channel. Likewise for '0' and '1' ,
gives reverse output to respective channel.

Fig 4.1: Experimental Waveform of Dc Motor Logic

Output port of FPGA is connected to Digital Signal Oscilloscope before directly
applying to motor. As shown in the waveform first two channels are for one DC motor which
is in forward direction and last two are for second DC motor which is in reverse direction.
Here medium speed is selected by applying 50% duty cycle.

Two DC motors are simultaneously driven from a applied logic in FPGA. Here logic is
tested by applying different speed controls. Module is tested with DC motor to test the
control of the speed and direction. The speed of the motor is varied as per the command given
from the PC and the direction is also controlled.

Module is tested with the servo motor to test the angle control. The angle of the motor
is varied as per the command given from the PC and the direction is also controlled

Dept. Of ECE, SCTIT Page 14

FPGA based wireless control system for Robotic applications 2017-2018

Fig 4.2: Experimental waveform of DC motor control

Angle To Be Controlled Required PWM signal

0° 1 ms

45° 1.25 ms

90° 1.50 ms

135° 1.75 ms

180° 2.00 ms

Table 1: servo motor angles

Dept. Of ECE, SCTIT Page 15

FPGA based wireless control system for Robotic applications 2017-2018

CHAPTER 5
FPGA IN COMPARSION TO ASIC
Speed: ASIC rules out FPGA in terms of speed. As ASIC are designed for a specific
application they can be optimized to maximum, hence we can have high speed in ASIC
designs. ASIC can have high speed clocks.

Cost: FPGAs are cost effective for small applications. But when it comes to complex and
large volume designs (like 32-bit processors) ASIC products are cheaper.

Size/Area: FPGA are contains lots of LUTs, and routing channels which are connected
via bit streams (program). They are in-general larger designs than corresponding ASIC
design. For example, LUT gives you both registered and non-register output, but if we
require only non-registered output, then its a waste of having a extra circuitry. In this way
ASIC will be smaller in size.

Power: FPGA designs consume more power than ASIC designs. As explained above the
unwanted circuitry results wastage of power. FPGA won’t allow us to have better power
optimization. When it comes to ASIC designs we can optimize them to the fullest.

Type of Design: ASIC can have mixed-signal designs, or only analog designs. But it is
not possible to design them using FPGA chips.

Simpler Design cycle: due to software that handles much of the routing, placement, and
timing, FPGA designs have smaller designed cycle than ASICs

Re-Usability: A single FPGA can be used for various applications, by simply

reprogramming it(dumping new HDL code). By definition ASIC are application specific
cannot be reused.

Tools: Tools which are used for FPGA designs are relatively cheaper than ASIC designs.

Dept. Of ECE, SCTIT Page 16

FPGA based wireless control system for Robotic applications 2017-2018

CHAPTER 6

FUTURE SCOPE AND CONCLUSION

FUTURE SCOPE OF FPGA TECHNOLOGY

FPGAs, with their high-performance capabilities, low-energy footprint and easy

programmability (or re-programmability) will increasingly be an important component in
many devices, especially ones around computer security. This is something Intel understands
well. As noted above, the company has introduced hybrid devices that combine an Intel®
Xeon® processor with an FPGA, and has more hybrid devices scheduled. The idea is that the
combination of the multiple processors on the same silicon will enable designers to create
products with considerably higher performance than individual devices can achieve.
Additionally, Intel is simplifying the interfaces between FPGAs and other system
components, and developing programming libraries that will enable developers to more easily
program an FPGA, in turn accelerating the development of new devices.

As of today, we’ve only had a glimpse of this new data-driven world and the computing
capabilities it will require. Just about a tenth of executives believe that IoT or machine
learning are already here. They do, however, realize that they need to get their organizations
ready to handle the enormous amounts of data that will be generated by ubiquitous devices
and IoT. Already 65% of IT executives spend at least a quarter of their IT budgets on high-
performance computing capabilities. When making your investment decisions, consider:

Technologies will need to translate this enormous supply of data into intelligence.
Without the ability to gather and understand data, and use data-driven insights for smart
decision making or actions, there is no point in collecting it in the first place. Translating data
into intelligence will require various high-level processing capabilities, including pattern
recognition, encryption and decryption, big data compression, and big data analysis.

The tools that will enable high-performance computing are not yet up to speed.
Hardware, especially, is an issue. A majority of CTOs and system architects believe that
software currently exceeds the abilities of hardware, which can lead to bottlenecks in data
flows. Executives would like faster processing, and this includes CPUs and FPGAs. They are
also well aware of the challenges with hardware, such as difficulties with programming and

Dept. Of ECE, SCTIT Page 17

FPGA based wireless control system for Robotic applications 2017-2018

high development and implementation costs. To better handle these challenges, many
executives would like more support from their vendors.

CONCLUSION

FPGA based real time control system is developed for wirelessly control any type of motors
in robotic applications. Addressing of control signals and sending data to particular signal are
implemented. Hardware module is developed to generate PWM output pulses, which are the
basic building blocks to drive robots. With the use of communication interfaces provided, all
modules can be easily accessible. ZigBee and FPGA interfacing was also successfully
developed. Functional verifications are done by applying the logic on the robotic
applications. This work was the prototype of a big system. By applied logic, total 16 motors
can be controlled but by taking advantage of FPGA, more number of logics can be added into
the developed control system.

Dept. Of ECE, SCTIT Page 18

FPGA based wireless control system for Robotic applications 2017-2018

Dept. Of ECE, SCTIT Page 19