8 7 6 5 4 3 2 1

REV DATE PAGES DESCRIPTION

NOTES: A1 08/16/17 All Initial Release
1. Project Drawing Numbers: A1.1 10/12/17 Pg.4, 6 Delete comment which may confuse users
Raw PCB 100-0321321-A1
Gerber Files 110-0321321-A1
PCB Design Files 120-0321321-A1
Assembly Drawing 130-0321321-A1
Fab Drawing 140-0321321-A1
Schematic Drawing 150-0321321-A1
E PCB Film 160-0321321-A1 E
Bill of Materials 170-0321321-A1
Schematic Design Files 180-0321321-A1
Functional Specification 210-0321321-A1
PCB Layout Guidelines 220-0321321-A1
Assembly Rework 320-0321321-A1

D D

Arduino Analog
Arduino PMOD

PAGE DESCRIPTION
Arduino Digital
1 Title, Notes, Block Diagram, Rev. History
2 Power Diagram
SystemMAX ADC I2C
3 Clock Daigram
RGMII
On-Board Ethernet 4 Cyclone 10 Bank 1~4
Mini-USB USB Interface
C USB BlasterTM II 5 Cyclone 10 Bank 5~8 C
2.0 JTAG
6 Cyclone 10 Power
HyperBus
Cyclone 10 LP HyperRAM
x8
7 MAX10 - UBII-A
8 MAX10 - UBII-B
JTAG FPGA Button
9 MAX10 - ADC
Header
EPCQ64 U256 Package 10 HyperRAM
14x14mm Switch 11 Ethernet
12 Arduino Header
Clock LED
(50M + programmable)
13 PMOD, 2x20 GPIO
14 LED, PB, DIP SW
B B
15 Clock
2x20 GPIO Header 16 Power Input
17 1.2V, 1.8V, 2.5V, 3.3V

A A
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Title
Cyclone 10 LP FPGA Evaluation Kit Board
Copyright (c) 2016, Intel Corporation All Rights Reserved
Size Document Number Rev
B 150-0321321-A1 (6XX-44504R) A1
Date: Thursday, October 12, 2017 Sheet 1 of 17
8 7 6 5 4 3 2 1
 5 4 3 2 1

D D

EN5339QI (U23)
3A Max.
C10_VCCIO_3.3V

C
USB_5V C

(5V@1A)
EN5329QI (U25)
2A Max.
C10_VCCINT
5V_DCIN
C10_VCCD_PLL
( 5V,>1A )

EP5358HUI (U26)
0.6A Max.
B C10_VCCIO_1.8V B

EP5358HUI (U27) C10_VCCA

0.6A Max.

A A

Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Title
Cyclone 10 LP FPGA Evaluation Kit Board
Copyright (c) 2016, Intel Corporation All Rights Reserved
Size Document Number Rev
B 150-0321321-A1 (6XX-44504R) A1
Date: Tuesday, August 01, 2017 Sheet 2 of 17
5 4 3 2 1
 5 4 3 2 1

D D

Cypress
CY7C68013A
USB Controller On-Board
USB BlasterTM II

Default LVCMOS 125MHz

C C
Si5351
8 7
Default LVCMOS 50MHz

LVCMOS Adjustable

1 6

B 2 5 B

3 4

A A

Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Title
Cyclone 10 LP FPGA Evaluation Kit Board
Copyright (c) 2016, Intel Corporation All Rights Reserved
Size Document Number Rev
B 150-0321321-A1 (6XX-44504R) A1
Date: Tuesday, May 16, 2017 Sheet 3 of 17
5 4 3 2 1
 5 4 3 2 1

U1A
HyperRAM (HyperBUS)

10CL025YU256 <10> HBUS_DQ[7:0]

U1B
Bank 1 VCCIO1=3.3V 10CL025YU256 <10> HBUS_RWDS

ARDUINO_IO0 B1 Bank 2 VCCIO2=3.3V

ARDUINO_IO1 C2 IO_B1_0 M2 <10> HBUS_CKp
D C10_VCCIO_3.3V C10_AS_ASDO C1 IO, DIFFIO_L3P M1 CLK2, DIFFCLK_1P <10> HBUS_CKn D
ARDUINO_IO2 F3 IO, DIFFIO_L3N, DATA1, ASDO ARDUINO_IO6 J2 CLK3, DIFFCLK_1N
C10_AS_CSn D2 IO, VREFB1N0 ARDUINO_IO7 J1 IO, DIFFIO_L7P <10> HBUS_CS2n
ARDUINO_IO3 D1 IO, DIFFIO_L4P, FLASH_NCE, NCSO C10_VCCIO_3.3V ARDUINO_IO8 K2 IO, DIFFIO_L7N <10> HBUS_RSTn
R1 C10_NSTATUS F4 IO, DIFFIO_L4N ARDUINO_IO11 K1 IO, DIFFIO_L10P
10K
ARDUINO_IO4 G2 NSTATUS ARDUINO_IO12 L2 IO, DIFFIO_L10N
ARDUINO_IO5 G1 IO, DIFFIO_L6P ARDUINO_IO13 L1 IO, DIFFIO_L11P
C10_AS_DCLK H1 IO, DIFFIO_L6N R288 ARDUINO_RSTn L3 IO, DIFFIO_L11N <10> HBUS_CS1n
10K
C10_VCCA_FLT C10_AS_DATA0 H2 DCLK R276 2K ARDUINO_SDA N2 IO, VREFB2N0 <10> HBUS_RSTOn
R2 C10_NCONFIG H5 IO, DATA0 R277 2K ARDUINO_SCL N1 IO, DIFFIO_L13P <10> HBUS_INTn
10K
R4 C10_JTAG_TDI H4 NCONFIG ARDUINO_IO9 K5 IO, DIFFIO_L13N
10K
C10_JTAG_TCK H3 TDI ARDUINO_IO10 L4 IO, RUP1
R6 1K Reserved For MCP/Flash
R7 C10_JTAG_TMS J5 TCK GPIO35 R1 IO, RDN1
10K
C10_JTAG_TDO J4 TMS GPIO33 P2 IO_B2_0
R8 0 C10_NCE J3 TDO GPIO34 P1 IO, DIFFIO_L15P
E2 NCE IO, DIFFIO_L15N
C10_CLK50M E1 CLK0, DIFFCLK_0P
CLK1, DIFFCLK_0N
10CL025YU256I7G

10CL025YU256I7G
C10 JTAG
C
<8> C10_JTAG_TDO C
VCC_3.3V U2 <8> C10_JTAG_TDI
<8> C10_JTAG_TMS
R9 0 1 16 C10_AS_DCLK <8> C10_JTAG_TCK
C1 0.1uF 2 VCC/DATA3 DCLK 15 C10_AS_ASDO
3 VCC DATA0 14
4 NC1 NC8 13
5 NC2 NC7 12 <14> C10_NCONFIG
6 NC3 NC6 11 VCC_3.3V
C10_AS_CSn 7 NC4 NC5 10 <7> C10_NSTATUS
C10_AS_DATA0 R10 24.9 8 nCS GND 9 R11 0
DATA1 VCC/DATA2

EPCQ64 Arduino Digital IO

<12> ARDUINO_IO[13:0]
U1C
<12> ARDUINO_RSTn
10CL025YU256 U1D

Bank 3 VCCIO3=3.3V 10CL025YU256

GPIO28 N3
Arduino I2C
GPIO29 P3 IO, DIFFIO_B1P Bank 4 VCCIO4=1.8V <12> ARDUINO_SCL
GPIO30 R3 IO, DIFFIO_B1N R9 <12> ARDUINO_SDA
GPIO31 T3 IO, DIFFIO_B2P T9 CLK13, DIFFCLK_7P
B B
GPIO20 T2 IO, DIFFIO_B2N HBUS_RSTn N9 CLK12, DIFFCLK_7N
GPIO26 R4 IO_B3_0 HBUS_DQ3 R10 IO_B4_0
GPIO27 T4 IO, PLL1_CLKOUTP HBUS_DQ4 T10 IO, DIFFIO_B16P
GPIO24 N5 IO, PLL1_CLKOUTN HBUS_DQ5 R11 IO, DIFFIO_B16N Clocks
GPIO25 N6 IO, DIFFIO_B4P HBUS_DQ2 T11 IO, DIFFIO_B17P
GPIO21 M6 IO, DIFFIO_B4N HBUS_DQ6 R12 IO, DIFFIO_B17N <15> C10_CLK50M
GPIO32 P6 IO_B3_1 HBUS_DQ0 T12 IO, DIFFIO_B18P
GPIO17 M7 IO, VREFB3N0 HBUS_CS2n P9 IO, DIFFIO_B18N <15> ENET_CLK_125M
GPIO22 R5 IO_B3_2 HBUS_INTn P11 IO_B4_1
GPIO23 T5 IO, DIFFIO_B6P C10_VCCIO_1.8V HBUS_DQ7 R13 IO, VREFB4N0
GPIO18 R6 IO, DIFFIO_B6N HBUS_DQ1 T13 IO, DIFFIO_B20P
GPIO19 T6 IO, DIFFIO_B7P R12 49.9 RUP2 M10 IO, DIFFIO_B20N
GPIO16 L7 IO, DIFFIO_B7N R13 49.9 RDN2 N11 IO, RUP2 2x20 GPIO
GPIO14 R7 IO_B3_3 HBUS_RWDS T14 IO, RDN2
GPIO15 T7 IO, DIFFIO_B8P HBUS_RSTOn T15 IO, DIFFIO_B23P <5,13> GPIO[0:35]
GPIO13 L8 IO, DIFFIO_B8N HBUS_CS1n N12 IO, DIFFIO_B23N
GPIO12 M8 IO_B3_4 HBUS_CKp P14 IO_B4_2
GPIO10 N8 IO_B3_5 HBUS_CKn R14 IO, PLL4_CLKOUTP
GPIO11 P8 IO_B3_6 IO, PLL4_CLKOUTN
R8 IO_B3_7
ENET_CLK_125M T8 CLK15, DIFFCLK_6P
CLK14, DIFFCLK_6N 10CL025YU256I7G

A A
10CL025YU256I7G

Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Title
Cyclone 10 LP FPGA Evaluation Kit Board
Copyright (c) 2016, Intel Corporation All Rights Reserved
Size Document Number Rev
B 150-0321321-A1 (6XX-44504R) A1
Date: Thursday, October 12, 2017 Sheet 4 of 17
5 4 3 2 1
 5 4 3 2 1

C10_VCCA_FLT C10 M10 Interconnetion

U1E 2.5V
U1F <7> C10_M10_IO[3:0]
10CL025YU256 C10_MSEL2 R17 0
10CL025YU256 R18 DNI
Bank 5 VCCIO5=3.3V C10_VCCIO_3.3V C10_MSEL1 R19 DNI
D GPIO8 N14 Bank 6 VCCIO6=3.3V R20 0
C10 Misc. Signals D
GPIO9 P15 IO, RUP3 C10_CLK_ADJ E16 C10_MSEL0 R22 0 <14> C10_RESETn
GPIO4 P16 IO, RDN3 USER_PB0 E15 CLK5, DIFFCLK_2N R23 DNI <7> C10_CONF_DONE
GPIO5 R16 IO, DIFFIO_R15N R16 C10_CONF_DONE H14 CLK4, DIFFCLK_2P <7> C10_CRC_ERROR
10K
C10_VCCIO_3.3V GPIO6 N16 IO, DIFFIO_R15P C10_MSEL0 H13 CONF_DONE MSEL[2:0]=101: ASx1, Fast POR, 3.3V IO <7> C10_INIT_DONE
GPIO7 N15 IO, DIFFIO_R13N C10_MSEL1 H12 MSEL0
USER_LED0 L14 IO, DIFFIO_R13P C10_MSEL2 G12 MSEL1
GPIO0 L13 IO, VREFB5N0 R21 C10_INIT_DONE G16 MSEL2
GPIO1 L16 IO_B5_0 R246
10K
C10_CRC_ERROR G15 IO, DIFFIO_R5N, INIT_DONE Arduino ADC I2C
10K
GPIO2 L15 IO, DIFFIO_R11N PMOD_D1 F13 IO, DIFFIO_R5P, CRC_ERROR <8> ARDUINO_ADC_SCL
GPIO3 K16 IO, DIFFIO_R11P PMOD_D3 F16 IO_B6_0 <8> ARDUINO_ADC_SDA
USER_LED1 K15 IO, DIFFIO_R10N PMOD_D5 F15 IO, DIFFIO_R4N, NCEO
R207 C10_DEV_OE J16 IO, DIFFIO_R10P PMOD_D7 B16 IO, DIFFIO_R4P, CLKUSR
10K
R136 C10_RESETn J15 IO, DIFFIO_R9N, DEV_OE USER_PB1 F14 IO_B6_1
10K
USER_LED2 J14 IO, DIFFIO_R9P, DEV_CLRN PMOD_D0 D16 IO, VREFB6N0 Ethernet
USER_LED3 J13 IO_B5_1 PMOD_D2 D15 IO_B6_2 <11> ENET_RG_RXCLK
USER_DIP0 M16 IO_B5_2 PMOD_D4 C16 IO_B6_3 <11> ENET_RG_RXCTL
HBUS_CLK_50M M15 CLK7, DIFFCLK_3N PMOD_D6 C15 IO, DIFFIO_R1N
CLK6, DIFFCLK_3P IO, DIFFIO_R1P <11> ENET_RG_RXD0
<11> ENET_RG_RXD1
<11> ENET_RG_RXD2
10CL025YU256I7G 10CL025YU256I7G <11> ENET_RG_RXD3

C C

<11> ENET_RG_TXCLK
<11> ENET_RG_TXCTL

<11> ENET_RG_TXD0
<11> ENET_RG_TXD1
<11> ENET_RG_TXD2
<11> ENET_RG_TXD3
U1G
10CL025YU256
U1H <11> ENET_MDC
Bank 7 VCCIO7=3.3V 10CL025YU256 <11> ENET_MDIO
USB_SCL C14 <11> ENET_INT
USB_EMPTY D14 IO, DIFFIO_T24N C10_VCCIO_3.3V Bank 8 VCCIO8=3.3V <11> ENET_RSTn
USB_RDn D11 IO, DIFFIO_T24P USER_DIP1 A8
USB_FULL D12 IO, DIFFIO_T23N ENET_RG_RXCLK B8 CLK10, DIFFCLK_4N
USB_DATA4 A13 IO, DIFFIO_T23P R278 2K ARDUINO_ADC_SDA C8 CLK11, DIFFCLK_4P
USB_DATA3 B13 IO, DIFFIO_T22N R279 2K ARDUINO_ADC_SCL D8 IO_B8_0 MAX10 USB Interface
USB_DATA2 A14 IO, DIFFIO_T22P C10_M10_IO0 E8 IO_B8_1 <8> USB_DATA[7:0]
USB_DATA1 B14 IO, PLL2_CLKOUTN C10_M10_IO2 F8 IO, DIFFIO_T10N, DATA2
E11 IO, PLL2_CLKOUTP ENET_RG_RXD0 A7 IO, DIFFIO_T10P, DATA3 <8> USB_ADDR[1:0]
E10 IO, RUP4 ENET_RG_RXD1 B7 IO, DIFFIO_T9N
USB_DATA6 A12 IO, RDN4 ENET_RSTn C6 IO, DIFFIO_T9P, DATA4 <8> USB_FULL
USB_DATA5 B12 IO, DIFFIO_T21N ENET_RG_RXD2 A6 IO, VREFB8N0 <8> USB_EMPTY
B B
USB_ADDR1 A11 IO, DIFFIO_T21P ENET_RG_RXD3 B6 IO, DIFFIO_T7N <8> USB_SCL
USB_WRn B11 IO, DIFFIO_T20N C10_M10_IO1 E7 IO, DIFFIO_T7P <8> USB_SDA
USER_PB2 C11 IO, DIFFIO_T20P ENET_RG_TXD0 R306 33 C10_RG_TXD0 E6 IO, DATA5
USB_DATA0 A15 IO, VREFB7N0 ENET_RG_RXCTL A5 IO, DATA6 <8> USB_RESETn
USB_OEn F9 IO_B7_0 ENET_INT B5 IO, DIFFIO_T5N, DATA7 <8> USB_OEn
USB_ADDR0 A10 IO_B7_1 ENET_RG_TXCTL R301 33 C10_RG_TXCTL D6 IO, DIFFIO_T5P <8> USB_RDn
USB_DATA7 B10 IO, DIFFIO_T16N ENET_MDIO A4 IO_B8_2 <8> USB_WRn
USB_RESETn C9 IO, DIFFIO_T16P ENET_MDC B4 IO, DIFFIO_T3N
USER_PB3 D9 IO, DIFFIO_T15N ENET_RG_TXD3 R302 33 C10_RG_TXD3 A2 IO, DIFFIO_T3P
USB_SDA E9 IO, DIFFIO_T15P ENET_RG_TXD1 R303 33 C10_RG_TXD1 A3 IO, DIFFIO_T2N
USER_DIP2 A9 IO_B7_2 ENET_RG_TXD2 R304 33 C10_RG_TXD2 B3 IO, DIFFIO_T2P User PBs, LEDs, SWs
USB_CLK R248 0 C10_USB_CLK B9 CLK8, DIFFCLK_5N C10_M10_IO3 C3 IO_B8_3 <14> USER_LED[0:3]
CLK9, DIFFCLK_5P ENET_RG_TXCLK R305 33 C10_RG_TXCLK D3 IO, PLL3_CLKOUTN
IO, PLL3_CLKOUTP <14> USER_PB[0:3]
Clock
10CL025YU256I7G <15> C10_CLK_ADJ <14> USER_DIP[0:2]
10CL025YU256I7G
<15> HBUS_CLK_50M 2x20 GPIO
<7> USB_CLK <4,13> GPIO[0:35]

PMOD
A <13> PMOD_D[0:7] A

Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Title
Cyclone 10 LP FPGA Evaluation Kit Board
Copyright (c) 2016, Intel Corporation All Rights Reserved
Size Document Number Rev
B 150-0321321-A1 (6XX-44504R) A1
Date: Tuesday, May 16, 2017 Sheet 5 of 17
5 4 3 2 1
 5 4 3 2 1

U1I
D 1.2V U1J D
10CL025YU256
C10_VCCINT 10CL025YU256 C10_VCCIO_3.3V
VCCINT C10_VCCIO_3.3V
F7 VCCIO U1L
F11 VCCINT E3 K14
G6 VCCINT G3 VCCIO1 VCCIO5 M14
VCCINT VCCIO1 VCCIO5 10CL025YU256
G7 C10_VCCA C10_VCCA_FLT 2.5V
G8 VCCINT K3 E14 Misc. Power
G9 VCCINT M3 VCCIO2 VCCIO6 G14 L17 L5
G10 VCCINT VCCIO2 VCCIO6 1.5A, 180 Ohm FB F12 VCCA1 U1K
H6 VCCINT P4 A16 F5 VCCA2
H11 VCCINT P7 VCCIO3 VCCIO7 C10 L12 VCCA3
VCCINT VCCIO3 VCCIO7 VCCA4 10CL025YU256
J6 C10_VCCIO_1.8V T1 C13
K7 VCCINT VCCIO3 VCCIO7 C10_VCCD_PLL 1.2V N4 M5 GND
K11 VCCINT P10 A1 D13 VCCD_PLL1 GNDA1 E12 H7 D7
L6 VCCINT P13 VCCIO4 VCCIO8 C4 D4 VCCD_PLL2 GNDA2 E5 H8 GND GND D10
K9 VCCINT T16 VCCIO4 VCCIO8 C7 N13 VCCD_PLL3 GNDA3 M12 H9 GND GND E4
K10 VCCINT VCCIO4 VCCIO8 VCCD_PLL4 GNDA4 H10 GND GND E13
M9 VCCINT J7 GND GND G4
M11 VCCINT J8 GND GND G13
J12 VCCINT 10CL025YU256I7G J9 GND GND K4
VCCINT 10CL025YU256I7G J10 GND GND K13
F6 GND GND M4
F10 GND GND M13
C GND GND C
10CL025YU256I7G J11 N7
K8 GND GND N10
K6 GND GND P5
L9 GND GND P12
C10_VCCINT C10_VCCIO_3.3V C10_VCCA_FLT L10 GND GND R2
L11 GND GND R15
K12 GND GND H16
G11 GND GND H15
C138 C139 C120 C117 B2 GND GND D5
C134 C136 C124 C129 C195 C196
B15 GND GND F1
4700pF 4700pF 0.01uF 0.01uF 0.022uF 0.022uF 4.7uF 0.47uF 0.01uF 0.1uF C5 GND GND F2
C12 GND GND G5
GND GND

10CL025YU256I7G
TP27
VCC_1.8V C10_VCCIO_1.8V VCC_1.2V C10_VCCD_PLL
TP26
C141 C143 C142 C130 C194 C193
R236 0.2 TP25 L15 R237 0.2
0.047uF 0.1uF 0.22uF 1uF 4.7uF 47uF 1.5A, 180 Ohm FB
C197 C122 C115

B 1uF 0.01uF 1uF B

A A

Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Title
Cyclone 10 LP FPGA Evaluation Kit Board
Copyright (c) 2016, Intel Corporation All Rights Reserved
Size Document Number Rev
B 150-0321321-A1 (6XX-44504R) A1
Date: Thursday, October 12, 2017 Sheet 6 of 17
5 4 3 2 1
 5 4 3 2 1

VCC_3.3V U3C
USB_5V FX2_PA7 M3
J17 FX2_SLWRn L3 IO_2_M3/PLL_L_CLKOUTN/DIFFIO_RX_L27N
USB MINI-B IO_2_L3/PLL_L_CLKOUTP/DIFFIO_RX_L27P
1 USB: 90Ohm Differential Pair U4 C2 FX2_RESETn J1
VBUS
2 FX2_D_N 1 4 J2 IO_2_J1/DIFFIO_RX_L19N
D- GND VCC IO_2_J2/DIFFIO_RX_L19P
D+ 3 FX2_D_P 0.1uF C10_CRC_ERROR M1
D 4 R213 DNI C10_NSTATUS M2 IO_2_M1/DIFFIO_RX_L21N D
ID IO_2_M2/DIFFIO_RX_L21P
5 100K R27 FX2_RESETn 2 3 C10_CONF_DONE L2
RESET MR SYS_CONF_DONE K1 IO_2_L2
ADM811 C10_INIT_DONE K2 IO_2_K1/DIFFIO_RX_L28N
9
8
7
6
IO_2_K2/DIFFIO_RX_L28P
VCC_3.3V VCC_3.3V MAX10 10M08SA U169
U6
3 42 FX2_RESETn
U5 7 AVCC0 RESET 15 FX2_SCL R29 2K U3D
1 AVCC1 SCL 16 FX2_SDA R30 2K
3 D+ 2 11 SDA C10_M10_IO3 L5
GND D- 17 VCC0 44 FX2_WAKEUP FX2_PA6 M4 IO_3_L5/DIFFIO_TX_RX_B1N
R293 DNI TPD2EUSB30 27 VCC1 WAKEUP FX2_PD7 L4 IO_3_M4/DIFFIO_RX_B2N
32 VCC2 29 FX2_FLAGA FX2_PA4 M5 IO_3_L4/DIFFIO_TX_RX_B1P
43 VCC3 CTL0 30 FX2_FLAGB FX2_SLRDn K5 IO_3_M5/DIFFIO_RX_B2P
C202 VCC4 CTL1 FX2_FLAGC FX2_PA5 IO_3_K5/DIFFIO_TX_RX_B3N
55 31 N4
VCC5 CTL2 FX2_PD6 J5 IO_3_N4/DIFFIO_RX_B4N
Y1 9 1 FX2_SLRDn FX2_PA3 N5 IO_3_J5/DIFFIO_TX_RX_B3P
DMINUS RDY0 IO_3_N5/DIFFIO_RX_B4P
4

8 2 FX2_SLWRn FX2_PA2 N6
1nF/3kV 1 3 DPLUS RDY1 FX2_PA0 N7 IO_3_N6/DIFFIO_TX_RX_B5N
USB_CLK 13 54 FX2_PA1 M7 IO_3_N7/DIFFIO_RX_B6N C10 M10 Interconnetion
24.00MHz 24M_XTALIN 5 IFCLK CLKOUT FX2_FLAGB N8 IO_3_M7/DIFFIO_TX_RX_B5P <5> C10_M10_IO[3:0]
2

24M_XTALOUT 4 XTALIN FX2_SCL J6 IO_3_N8/DIFFIO_RX_B6P

XTALOUT FX2_FLAGC M8 IO_3_J6/DIFFIO_TX_RX_B7N
C C4 C5 C
FX2_PA0 33 18 FX2_PB0 FX2_SDA 0 R26 MAX_SDA K6 IO_3_M8/DIFFIO_RX_B8N
12pF 12pF FX2_PA1 34 PA0 PB0 19 FX2_PB1 FX2_FLAGA M9 IO_3_K6/DIFFIO_TX_RX_B7P C10 Misc. Signals
FX2_PA2 35 PA1 PB1 20 FX2_PB2 FX2_PD4 J7 IO_3_M9/DIFFIO_RX_B8P
FX2_PA3 36 PA2 PB2 21 FX2_PB3 FX2_PD5 K7 IO_3_J7/DIFFIO_TX_RX_B9N <4> C10_NSTATUS
FX2_PA4 37 PA3 PB3 22 FX2_PB4 FX2_PB2 N12 IO_3_K7/DIFFIO_TX_RX_B9P <5> C10_CONF_DONE
FX2_PA5 38 PA4 PB4 23 FX2_PB5 FX2_PB0 M13 IO_3_N12 <14> SYS_CONF_DONE
FX2_PA6 39 PA5 PB5 24 FX2_PB6 FX2_PB5 N10 IO_3_M13/DIFFIO_TX_RX_B10N <5> C10_CRC_ERROR
FX2_PA7 40 PA6 PB6 25 FX2_PB7 FX2_PB1 M12 IO_3_N10/DIFFIO_RX_B11N <5> C10_INIT_DONE
PA7 PB7 FX2_PB7 N9 IO_3_M12/DIFFIO_TX_RX_B10P
14 45 FX2_PD0 FX2_PB6 M10 IO_3_N9/DIFFIO_RX_B11P
RESERVED PD0 46 FX2_PD1 C10_M10_IO2 L10 IO_3_M10/DIFFIO_TX_RX_B16N
VCC_3.3V 6 PD1 47 FX2_PD2 C10_M10_IO0 K8 IO_3_L10/DIFFIO_TX_RX_B16P <5> USB_CLK
10 AGND0 PD2 48 FX2_PD3 C10_M10_IO1 J8 IO_3_K8/DIFFIO_TX_RX_B14P <15> M10_CLK50M
AGND1 PD3 49 FX2_PD4 FX2_PB4 L11 IO_3_J8/DIFFIO_TX_RX_B14N
12 PD4 50 FX2_PD5 FX2_PB3 M11 IO_3_L11/DIFFIO_TX_RX_B12P
C6 C7 C8 C9 C10 C11 C12 C13 26 GND0 PD5 51 FX2_PD6 IO_3_M11/DIFFIO_TX_RX_B12N
28 GND1 PD6 52 FX2_PD7
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 41 GND2 PD7
53 GND3
GND4 MAX10 10M08SA U169
56 57
GND5EXPOSED_PAD
USB_5V CY7C68013A_QFN U3H
USB_CLK 0 R247 M10_USB_CLK G5
R31 FX2_WAKEUP H6 IO_2_G5/CLK0N/DIFFIO_RX_L18N
B 10K B
M10_CLK50M H5 IO_2_H6/CLK0P/DIFFIO_RX_L18P
H4 IO_2_H5/CLK1N/DIFFIO_RX_L20N
R32 C14 N2 IO_2_H4/CLK1P/DIFFIO_RX_L20P
N3 IO_2_N2/DPCLK0/DIFFIO_RX_L22N
20K 0.1uF G9 IO_2_N3/DPCLK1/DIFFIO_RX_L22P
G10 IO_6_G9/CLK2P/DIFFIO_RX_R14P
F13 IO_6_G10/CLK2N/DIFFIO_RX_R14N
E13 IO_6_F13/CLK3P/DIFFIO_RX_R16P
VCC_3.3V F9 IO_6_E13/CLK3N/DIFFIO_RX_R16N
U3I F10 IO_6_F9/DPCLK3/DIFFIO_RX_R26P
R33 M10_JTAGEN E5 IO_6_F10/DPCLK2/DIFFIO_RX_R26N
10K
FX2_PD1 R34 0 M10_TMS G1 IO_1B_E5/JTAGEN H1
FX2_PD0 R35 0 M10_TCK G2 IO_1B_G1/TMS/DIFFIO_RX_L11N L1 IO_1B_H1/VREFB1N0
FX2_PD2 R36 0 M10_TDI F5 IO_1B_G2/TCK/DIFFIO_RX_L11P N11 IO_2_L1/VREFB2N0
FX2_PD3 R37 0 M10_TDO F6 IO_1B_F5/TDI/DIFFIO_RX_L12N K13 IO_3_N11/VREFB3N0
R38 M10_DEV_CLRn B9 IO_1B_F6/TDO/DIFFIO_RX_L12P D13 IO_5_K13/VREFB5N0
10K
R39 M10_DEV_OE D8 IO_8_B9/DEV_CLRN/DIFFIO_RX_T16N B7 IO_6_D13/VREFB6N0
10K
R40 M10_CONFIG_SEL D7 IO_8_D8/DEV_OE/DIFFIO_RX_T18P IO_8_B7/VREFB8N0
10K
R41 M10_NCONFIG E7 IO_8_D7/CONFIG_SEL
10K
D6 INPUT_ONLY_8_E7/NCONFIG
R42 M10_NSTATUS C4 IO_8_D6/CRC_ERROR/DIFFIO_RX_T22N
10K
VCC_3.3V DNI R43 M10_CONF_DONE C5 IO_8_C4/NSTATUS/DIFFIO_RX_T24P
10K
IO_8_C5/CONF_DONE/DIFFIO_RX_T24N MAX10 10M108SA U169
C15 R44 DNI J1 VCC_3.3V
A R45 1K M10_TCK 1 2 MAX10 10M08SA U169 A
M10_TDO 3 1 2 4
R46 M10_TMS 5 3 4 6 VCC_3.3V
10K
7 5 6 8 C16
7 8 Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
R47 10K M10_TDI 9 10 M10_CONFIG_SEL R50 DNI
9 10 0.1uF Title
DNI Cyclone 10 LP FPGA Evaluation Kit Board
Copyright (c) 2016, Intel Corporation All Rights Reserved
Size Document Number Rev
B 150-0321321-A1 (6XX-44504R) A1
Date: Tuesday, May 16, 2017 Sheet 7 of 17
5 4 3 2 1
 5 4 3 2 1

MAX10 USB Interface

VCC_3.3V
<5> USB_DATA[7:0]

U3G <5> USB_ADDR[1:0]

R53 1K USB_SDA C10
R51 1K USB_FULL C9 IO_8_C10/DIFFIO_RX_T14P VCCIO=2.5V U3F <5> USB_FULL
USB_RESETn A8 IO_8_C9/DIFFIO_RX_T14N F12 <5> USB_EMPTY
D USB_OEn A9 IO_8_A8/DIFFIO_RX_T15P E12 IO_6_F12/DIFFIO_RX_R18P <5> USB_SCL D
USB_RDn B10 IO_8_A9/DIFFIO_RX_T15N C13 IO_6_E12/DIFFIO_RX_R18N <5> USB_SDA
USB_ADDR1 A10 IO_8_B10/DIFFIO_RX_T16P F8 IO_6_C13
USB_WRn A11 IO_8_A10/DIFFIO_RX_T17P B12 IO_6_F8/DIFFIO_RX_R27P <5> USB_RESETn
R54 1K USB_SCL E8 IO_8_A11/DIFFIO_RX_T17N E9 IO_6_B12/DIFFIO_RX_R28P <5> USB_OEn
USB_ADDR0 A7 IO_8_E8/DIFFIO_RX_T18N B11 IO_6_E9/DIFFIO_RX_R27N <5> USB_RDn
USB_DATA6 A6 IO_8_A7/DIFFIO_RX_T19P C12 IO_6_B11/DIFFIO_RX_R28N <5> USB_WRn
USB_DATA7 B6 IO_8_A6/DIFFIO_RX_T19N B13 IO_6_C12/DIFFIO_RX_R29P
USB_DATA2 A4 IO_8_B6/DIFFIO_RX_T20P C11 IO_6_B13/DIFFIO_RX_R30P
USB_DATA5 B5 IO_8_A4/DIFFIO_RX_T21P C10_JTAG_TDI A12 IO_6_C11/DIFFIO_RX_R29N
USB_DATA0 A3 IO_8_B5/DIFFIO_RX_T20N C10_JTAG_TCK E10 IO_6_A12/DIFFIO_RX_R30N
R52 1K USB_EMPTY E6 IO_8_A3/DIFFIO_RX_T21N C10_JTAG_TMS D9 IO_6_E10/DIFFIO_RX_R31P
USB_DATA1 B3 IO_8_E6/DIFFIO_RX_T22P C10_JTAG_TDO D12 IO_6_D9/DIFFIO_RX_R31N
USB_DATA3 B4 IO_8_B3/DIFFIO_RX_T23P D11 IO_6_D12/DIFFIO_RX_R33P
USB_DATA4 A5 IO_8_B4/DIFFIO_RX_T23N IO_6_D11/DIFFIO_RX_R33N System I2C
A2 IO_8_A5 <15> SYS_I2C_SCL
IO_8_A2/DIFFIO_RX_T26P MAX10 10M08SA U169
B2 <15> SYS_I2C_SDA
IO_8_B2/DIFFIO_RX_T26N
MAX10 10M08SA U169

USB Blaster Programming Header C10 JTAG

C (uses JTAG mode only) C
<4> C10_JTAG_TDO
VCC_3.3V C17 VCC_3.3V <4> C10_JTAG_TDI
0.1uF R57 DNI J2 <4> C10_JTAG_TMS
EXT_JTAG_TCK 1 2 USB_DISABLEn 1K R59 <4> C10_JTAG_TCK
R58 1K EXT_JTAG_TDO 3 1 2 4
R60 EXT_JTAG_TMS 5 3 4 6 <14> VTAP_BYPASSn
10K
7 5 6 8 C18
R61 EXT_JTAG_TDI 9 7 8 10
10K
9 10 0.1uF
2X5_100mil
Arduino ADC I2C
<5> ARDUINO_ADC_SCL
<5> ARDUINO_ADC_SDA

VCC_3.3V M10_VCCIO1A
Power Good
U3A <17> VCC_1.2V_PG
L2 F2 U3K <17> VCC_3.3V_PG
1.5A, 180 Ohm FB VCC_3.3V G3 VCCIO1A__F2 A1
K3 VCCIO1B__G3 A13 GND__A1 <14> PWR_GD_LED
B C176 C156 B
J3 VCCIO2__K3 B8 GND__A13
10uF 0.22uF C155 C157 L8 VCCIO2__J3 C3 GND__B8
C190 VCCIO3__L8 GND__C3
L7 D5
4.7uF 0.01uF 0.01uF L6 VCCIO3__L7 E11 GND__D5 U3E
VCC_2.5V J11 VCCIO3__L6 F3 GND__E11 VTAP_BYPASSn K10
H11 VCCIO5__J11 G7 GND__F3 VCC_3.3V J10 IO_5_K10/DIFFIO_RX_R1P
G11 VCCIO5__H11 H12 GND__G7 IO_5_J10/DIFFIO_RX_R1N
F11 VCCIO6__G11 J4 GND__H12 R214 2K ARDUINO_ADC_SDA K11
C182 C8 VCCIO6__F11 L9 GND__J4 R215 2K ARDUINO_ADC_SCL L12 IO_5_K11/DIFFIO_RX_R2P
C189
VCC_3.3V M10_VCCA_3.3V C7 VCCIO8__C8 M6 GND__L9 EXT_JTAG_TDO K12 IO_5_L12/DIFFIO_RX_R2N
1uF 0.22uF C6 VCCIO8__C7 N1 GND__M6 EXT_JTAG_TMS L13 IO_5_K12/DIFFIO_RX_R7P
L3 K4 VCCIO8__C6 N13 GND__N1 EXT_JTAG_TCK J12 IO_5_L13
1.5A, 180 Ohm FB D10 VCCA1__K4 GND__N13 EXT_JTAG_TDI J9 IO_5_J12/DIFFIO_RX_R7N
D4 VCCA2__D10 USB_DISABLEn J13 IO_5_J9/DIFFIO_RX_R8P
VCCA3__D4 MAX10 10M08SA U169 IO_5_J13/DIFFIO_RX_R9P
C177 C178 C179 C180 C181 VCC_3.3V K9 VCC_1.2V_PG H10
VCCA4__K9 VCC_3.3V VCC_3.3V_PG H13 IO_5_H10/DIFFIO_RX_R8N
10uF 0.1uF 0.1uF 0.1uF 0.1uF H7 PWR_GD_LED H9 IO_5_H13/DIFFIO_RX_R9N
G8 VCC_ONE__H7 R55 2K SYS_I2C_SCL G13 IO_5_H9/DIFFIO_RX_R10P
C153 G6 VCC_ONE__G8 R56 2K SYS_I2C_SDA H8 IO_5_G13/DIFFIO_RX_R11P
C151 C146
F7 VCC_ONE__G6 G12 IO_5_H8/DIFFIO_RX_R10N
0.01uF 0.047uF 4.7uF VCC_ONE__F7 IO_5_G12/DIFFIO_RX_R11N
MAX10 10M08SA U169 MAX10 10M08SA U169
A A

Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Title
Cyclone 10 LP FPGA Evaluation Kit Board
Copyright (c) 2016, Intel Corporation All Rights Reserved
Size Document Number Rev
B 150-0321321-A1 (6XX-44504R) A1
Date: Monday, June 26, 2017 Sheet 8 of 17
5 4 3 2 1
 5 4 3 2 1

C10_VCCINT VCC_1.2V C10_VCCA VCC_2.5V C10_VCCIO_3.3V VCC_3.3V

R63 0.04 R64 0.2 R77 0.2

D R65 R66 R67 R68 R78 R79 D

100 100 100 100 100 100

M10_VCCA_3.3V U7
1 8 M10_VCCA_3.3V U8 M10_VCCA_3.3V U11
2 -IN +IN 7 1 8 1 8
3 V+ NC3 6 2 -IN +IN 7 2 -IN +IN 7
4 NC1 NC2 5 VCCINT_ISENSE 3 V+ NC3 6 3 V+ NC3 6
C19 V- VOUT 4 NC1 NC2 5 VCCA_ISENSE 4 NC1 NC2 5 VCCIO_3.3V_ISENSE
C20 C23 V- VOUT C26 V- VOUT
0.1uF LT6105IMS8 R71 C22 C28
4.99K DNI 0.1uF LT6105IMS8 R72 0.1uF LT6105IMS8 R81
4.99K DNI 4.99K DNI
A_GND
A_GND
A_GND
A_GND
A_GND A_GND
M10_VCCA_3.3V
M10_VCCA_3.3V

C173 Arduino Analog IO

C
C168 0.1uF C
0.1uF <12> ARDUINO_ANA[0:5]
A_GND A_GND
A_GND A_GND
U33

4
U32

VDD

VSS
ARDUINO_AMP2 2

VDD

VSS
ARDUINO_AMP0 2 VINA- 1 ARDUINO_AMP2
VINA- 1 ARDUINO_AMP0 ARDUINO_ANA2 R221 316 A2+ 3 VOUTA
ARDUINO_ANA0 R217 316 A0+ 3 VOUTA VINA+
VINA+ R220 ARDUINO_AMP3 6
R216 ARDUINO_AMP1 6 C171 VINB- 7 ARDUINO_AMP3
VINB- 316 VOUTB
316 C169 7 ARDUINO_AMP1 1nF A3+ 5
A1+ 5 VOUTB VINB+
1nF VINB+
A_GND MCP6242-E/MS
A_GND MCP6242-E/MS M10_VCCA_3.3V

ARDUINO_ANA1 R219 316 ARDUINO_ANA3 R223 316

R218 R222 C188

316 C170 316 C172 0.1uF
1nF 1nF
A_GND A_GND
B B
U34

4
A_GND A_GND

VDD

VSS
EXT_VREF ARDUINO_AMP4 2
VINA- 1 ARDUINO_AMP4
EXT_VREF_AR EXT_VREF ARDUINO_ANA4 R225 316 A4+ 3 VOUTA
U3J VINA+
A_GND E2 C212 C213 R224 ARDUINO_AMP5 6
DNI R228 EXT_VREF D3 REFGND__E2 C174 VINB- 7 ARDUINO_AMP5
ADC_VREF__D3 316 VOUTB
ANAIN1 D2 DNI DNI 1nF A5+ 5
ARDUINO_AMP1 R83 10 C29 1pF ANAIN1__D2 VINB+
ADC1IN1 MAX10 10M08SA U169
ARDUINO_AMP2 R84 10 C32 1pF A_GND MCP6242-E/MS
ADC1IN2 A_GND
VCCA_ISENSE R85 10 C33 1pF
ADC1IN3 U3B ARDUINO_ANA5 R227 316
VCCINT_ISENSE R86 10 C34 1pF D1
C2 IO_1A_D1/ADC1IN1/DIFFIO_RX_L1N R226
ARDUINO_AMP5 R87 10 C35 1pF E3 IO_1A_C2/ADC1IN2/DIFFIO_RX_L1P C175
IO_1A_E3/ADC1IN3/DIFFIO_RX_L3N 316
ADC1IN4 E4 1nF
ARDUINO_AMP0 R88 10 C36 1pF ADC1IN5 C1 IO_1A_E4/ADC1IN4/DIFFIO_RX_L3P
ADC1IN6 B1 IO_1A_C1/ADC1IN5/DIFFIO_RX_L5N
VCCIO_3.3V_ISENSE R89 10 C37 1pF ADC1IN7 F1 IO_1A_B1/ADC1IN6/DIFFIO_RX_L5P
ADC1IN8 E1 IO_1A_F1/ADC1IN7/DIFFIO_RX_L7N A_GND
A ARDUINO_AMP4 R90 10 C38 1pF IO_1A_E1/ADC1IN8/DIFFIO_RX_L7P A
F4
ARDUINO_AMP3 R91 10 C39 1pF G4 IO_1B_F4/DIFFIO_RX_L14N
H2 IO_1B_G4/DIFFIO_RX_L14P
IO_1B_H2/DIFFIO_RX_L16N Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
H3
L14 IO_1B_H3/DIFFIO_RX_L16P Title
1.5A, 180 Ohm FB A_GND Cyclone 10 LP FPGA Evaluation Kit Board
MAX10 10M08SA U169 Copyright (c) 2016, Intel Corporation All Rights Reserved
Size Document Number Rev
A_GND B A1
150-0321321-A1 (6XX-44504R)
Date: Thursday, June 29, 2017 Sheet 9 of 17
5 4 3 2 1
 5 4 3 2 1

D D

U13

HyperRAM
VCC_1.8V
HBUS_DQ0 R249 33 D3 1.8V I/O
HBUS_DQ1 R250 33 D2 DQ0 B4
HBUS_DQ2 R251 33 C4 DQ1 VCC
HBUS_DQ3 R252 33 D4 DQ2 C183 C185 C184 C41 C42 C43
HyperRAM (HyperBUS)
C40
HBUS_DQ4 R253 33 D5 DQ3 D1
HBUS_DQ5 R254 33 E3 DQ4 VCCQ1 E4 10uF 1uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF <4> HBUS_DQ[7:0]
HBUS_DQ6 R255 33 E2 DQ5 VCCQ2
HBUS_DQ7 R256 33 E1 DQ6
DQ7 A1 0 R92
HBUS_RWDS R257 33 C3 VSS1/DNP B3 <4> HBUS_RWDS
C RWDS VSS2 C

HBUS_CKp B2
HBUS_CKn B1 CK C1 <4> HBUS_CKp
CK# VSSQ1 E5 <4> HBUS_CKn
HBUS_CS2n A3 VSSQ2
CS#
HBUS_RSTn A4
RESET# <4> HBUS_CS2n
<4> HBUS_RSTn
B5
C5 RFU3
HBUS_RSTOn DNI R259 A2 RFU5
HBUS_INTn DNI R260 A5 RFU1
HBUS_CS1n DNI R258 C2 RFU2
RFU4
Reserved For MCP/Flash <4> HBUS_CS1n
<4> HBUS_RSTOn
IS66WVH16M8ALL-166B1LI <4> HBUS_INTn

Reserved For MCP/Flash

HBUS_CS1n: For Flash (Reserved)
HBUS_CS2n: For RAM

B B

VCC_1.8V

HBUS_CKp

R243
100 R245 R261 R262
10K DNI DNI
HBUS_CKn

HBUS_RSTn
In customer's design, please consult with HyperRAM vendor HBUS_RSTOn
to decide if need to assemble this parallel resister (R243) with HBUS_INTn
specified HyperRAM design

A A

Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Title
Cyclone 10 LP FPGA Evaluation Kit Board
Copyright (c) 2016, Intel Corporation All Rights Reserved
Size Document Number Rev
B 150-0321321-A1 (6XX-44504R) A1
Date: Monday, June 26, 2017 Sheet 10 of 17
5 4 3 2 1
 5 4 3 2 1

VCC_3.3V ENET_VDD_3.3V Ethernet RGMII

R307 0
<5> ENET_RG_TXCLK
<5> ENET_RG_TXCTL

<5> ENET_RG_TXD0
<5> ENET_RG_TXD1
D D
ENET_VDD_1V IND 4.7uH 850mA 310mOhm <5> ENET_RG_TXD2
C44 27pF <5> ENET_RG_TXD3
L9 1 2 ENET_REGO Y2
4.7uH ENET_VDD_1V
25.00MHz

3
ENET_XTAL1
C45 C46 ENET_XTAL2 2 4 <5> ENET_RG_RXCLK
ENET_VDD_3.3V 22uF 330pF ENET_VDD_3.3V <5> ENET_RG_RXCTL
C47 5.1 R95 C48 C49 C50 C51 C52

1
330pF C53 27pF <5> ENET_RG_RXD0
10uF 10uF 0.1uF 0.1uF 0.1uF <5> ENET_RG_RXD1
R96 <5> ENET_RG_RXD2
R97 R98 R297 <5> ENET_RG_RXD3

39

17

40
13
U14 1K

8
1K 1K DNI

REGO

VDDL

VDDC1
VDDC2
VDDC3
ENET_MDC 41 16 ENET_RSTn
ENET_MDIO 42 MDC RSTn <5> ENET_MDC
ENET_INT 47 MDIO 36 ENET_XTAL1 C54 ENET_VDD_3.3V <5> ENET_MDIO
MDINT XTAL1 37 ENET_XTAL2 <5> ENET_INT
ENET_LED0 24 XTAL2 DNI <5> ENET_RSTn
ENET_LED1 23 LED0 46
ENET_LED2 22 LED1 CLKOUT R99
ENET_VDD_3.3V LED2 21 ENET_TDO TP5
TDO 1K U28
R100 499 43 18 ENET_TDI TP6
R101 44 SCL TDI 20 ENET_TMS TP7 PHY Cable
C 10K C
SDA TMS 19 ENET_TCK C163 68pF 1 24
TCK 2 TCT1 MCT1 23
ENET_RG_TXCLK 9 3 TD1+ MX1+ 22
TX_CLK TD1- MX1- 615008140121
ENET_RG_TXCTL 15 34 TPIDN
ENET_RG_TXD0 14 TX_CTL TPIDN 33 TPIDP C162 68pF 4 21
ENET_RG_TXD1 12 TXD0 TPIDP 32 TPICN 5 TCT2 MCT2 20
ENET_RG_TXD2 11 TXD1 TPICN 31 TPICP 6 TD2+ MX2+ 19
ENET_RG_TXD3 10 TXD2 TPICP 29 TPIBN TD2- MX2- MX4- 8 14
TXD3 TPIBN 28 TPIBP C161 68pF 7 18 MX4+ 7 4- CGND2 13
ENET_RG_RXCLK R102 33 RG_RXCLK 6 TPIBP 27 TPIAN 8 TCT3 MCT3 17 MX2- 6 4+ CGND1
ENET_RG_RXCTL R103 33 RG_RXCTL 48 RX_CLK TPIAN 26 TPIAP 9 TD3+ MX3+ 16 MX3- 5 2-
ENET_RG_RXD0 R104 33 RG_RXD0 5 RX_CTL TPIAP TD3- MX3- MX3+ 4 3-
ENET_RG_RXD1 R105 33 RG_RXD1 4 RXD0 C160 68pF 10 15 MX2+ 3 3+
ENET_RG_RXD2 R106 33 RG_RXD2 3 RXD1 49 11 TCT4 MCT4 14 MX1- 2 2+
ENET_RG_RXD3 R107 33 RG_RXD3 1 RXD2 EPAD 12 TD4+ MX4+ 13 MX1+ 1 1-
RXD3 TD4- MX4- 1+

VDDH1
VDDH2
VDDH3

VDDP1
VDDP2
VDDP3
VDDR
749020010A
PEF7071 J16

2
7
25
30
35

38

45

75
75
75
75
16K R108
ENET_LED0 11K R109 ENET_VDD_3.3V 16K R110
B C55 DNI ENET_VDD_3.3V B

R208
R209
R210
R211
GREEN_LED D10
R240 390 Rcal for calibration
ENET_LED1 11K R112 C57 C58 C59 C60 C61 C62
C56 DNI R28 DNI C159
GREEN_LED D11 0.1uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF
R241 390 1nF/3kV
C164
ENET_LED2 3.92K R114
C65 DNI ENET_VDD_3.3V
GREEN_LED D12
R242 390 1nF/3kV

C63 C64

10uF 0.1uF

CBV[3] CBV[2] CBV[1] CBV[0] Rcfg + Ccfg

NET ON OFF Blink
LED0 ADR[3] 0 ADR[2] 0 ADR[1] 0 ADR[0] 0 11K+DNI
A NET_LED0 Link-up Link-down Traffc A
LED1 ADR[4] 0 MODE[1] 0 MODE[0] 0 FLOW 0 11K+DNI
NET_LED1 100Mbps Other Status N/A
LED2 CONF[1] 0 CONF[0] 1 ANEG[1] 0 ANEG[0] 0 3.92K+DNI Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
NET_LED2 1000Mbps Other Status N/A
Title
Cyclone 10 LP FPGA Evaluation Kit Board
Copyright (c) 2016, Intel Corporation All Rights Reserved
Size Document Number Rev
B 150-0321321-A1 (6XX-44504R) A1
Date: Tuesday, May 16, 2017 Sheet 11 of 17
5 4 3 2 1
 5 4 3 2 1

VCC_5V VCC_5V_AR1
F2 1A

ARDUINO_SCL
ARDUINO_SDA
D D
61301011821
61300811821 VCC_5V_AR1 J5
EXT_VREF_AR ANA_VREF Arduino Digital IO
VCC_3.3V 10
8 R275 DNI 9 10 <4> ARDUINO_IO[13:0]
8 7 DNI R308 8 9
7 6 7 8 <4> ARDUINO_RSTn
Arduino Power Output Capability 6 5 ARDUINO_IO13 6 7
3.3V: J4.2, J4.4 100mA Max. total 5 4 ARDUINO_IO12 5 6
5V: J4.5, J18.2 500mA Max. total 4 3 ARDUINO_RSTn ARDUINO_IO11 4 5
3 2 ARDUINO_IO10 3 4 Arduino Analog IO
Using external adaptor power input (J12) 2
IOREF R280
ARDUINO_IO9 3
1 0 2
1 ARDUINO_IO8 1 2 <9> ARDUINO_ANA[0:5]
1
J4
Arduino I2C
<4> ARDUINO_SCL
<4> ARDUINO_SDA

61300811821
61300611821

ARDUINO_IO7 8
C 8 C
6 ARDUINO_ANA5 ARDUINO_IO6 7
6 5 ARDUINO_ANA4 ARDUINO_IO5 6 7
5 4 ARDUINO_ANA3 ARDUINO_IO4 5 6
4 3 ARDUINO_ANA2 ARDUINO_IO3 4 5
3 2 ARDUINO_ANA1 ARDUINO_IO2 3 4
2 1 ARDUINO_ANA0 ARDUINO_IO1 2 3
1 ARDUINO_IO0 1 2
1
J6
J7

J18 VCC_5V_AR2 VCC_5V

1A F3
ARDUINO_IO12 1 2 ARDUINO_SCL
ARDUINO_SDA
ARDUINO_IO13 3 4 ARDUINO_IO11 ANA_VREF
GND
ARDUINO_RSTn 5 6 NC
ARDUINO_IO13
IOREF(3.3V)
ARDUINO_IO12
B ARDUINO_RSTn B
ARDUINO_IO11
61300621121 VCC_3.3V
ARDUINO_IO10
VCC_5V_AR1
ARDUINO_IO9
J5
GND
ARDUINO_IO8
GND
VCC_5V (Reserved)
4
J Arduino ARDUINO_IO7
ARDUINO_IO6
VCC_5V EXT_VREF
ARDUINO_ANA0 ARDUINO_IO5
ARDUINO_ANA1 ARDUINO_IO4
U12
L5 1 2 R295 DNI ARDUINO_ANA2 ARDUINO_IO3
DNI VIN VOUT ARDUINO_ANA3 ARDUINO_IO2
ARDUINO_ANA4 J18 ARDUINO_IO1
J6
C30
3 C31 ARDUINO_ANA5 J7 ARDUINO_IO0
DNI GND
DNI
REF3130/DNI

A_GND

A_GND

A A

Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Title
Cyclone 10 LP FPGA Evaluation Kit Board
Copyright (c) 2016, Intel Corporation All Rights Reserved
Size Document Number Rev
B 150-0321321-A1 (6XX-44504R) A1
Date: Tuesday, May 16, 2017 Sheet 12 of 17
5 4 3 2 1
 5 4 3 2 1

VCC_3.3V VCC_3.3V

U15 U16
PMOD PMOD_IO0
PMOD_IO1
1
3 IO1 VDD
5 PMOD_IO4
PMOD_IO5
1
3 IO1 VDD
5

PMOD_IO2 4 IO2 PMOD_IO6 4 IO2

D PMOD_IO3 6 IO3 2 PMOD_IO7 6 IO3 2 D
IO4 GND IO4 GND
VCC_3.3V 824013 824013 VCC_3.3V

DNI R270 R266 DNI

DNI R269 R265 DNI
J8
PMOD_D0 R116 200 PMOD_IO0 1 7 PMOD_IO4 R117 200 PMOD_D4
PMOD_D1 R118 200 PMOD_IO1 2 1 7 8 PMOD_IO5 R119 200 PMOD_D5
PMOD_D2 R120 200 PMOD_IO2 3 2 8 9 PMOD_IO6 R121 200 PMOD_D6
PMOD_D3 R122 200 PMOD_IO3 4 3 9 10 PMOD_IO7 R123 200 PMOD_D7
5 4 10 11
VCC_3.3V 6 5 11 12 VCC_3.3V
6 12
2x6 PMOD Connector

PMOD Specification not specified module power consumption but assumed no more than approximately 100mA. PMOD
<5> PMOD_D[0:7]

C C
2x20 GPIO

<4,5> GPIO[0:35]

2x20pin GPIO Header

J10
GPIO0 1 2 GPIO1
GPIO2 3 1 2 4 GPIO3
GPIO4 5 3 4 6 GPIO5
VCC_5V VCC_5V_GPIO GPIO6 7 5 6 8 GPIO7
F1 1A GPIO8 9 7 8 10 GPIO9
11 9 10 12
GPIO10 13 11 12 14 GPIO11
GPIO12 15 13 14 16 GPIO13
GPIO14 17 15 16 18 GPIO15
GPIO16 19 17 18 20 GPIO17
GPIO18 21 19 20 22 GPIO19
B B
GPIO20 23 21 22 24 GPIO21
VCC_3.3V GPIO22 25 23 24 26 GPIO23
GPIO24 27 25 26 28 GPIO25
29 27 28 30
GPIO26 31 29 30 32 GPIO27
GPIO28 33 31 32 34 GPIO29
GPIO30 35 33 34 36 GPIO31
GPIO32 37 35 36 38 GPIO33
GPIO34 39 37 38 40 GPIO35
39 40
Header 2x20 Shrouded

A A

Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Title
Cyclone 10 LP FPGA Evaluation Kit Board
Copyright (c) 2016, Intel Corporation All Rights Reserved
Size Document Number Rev
B 150-0321321-A1 (6XX-44504R) A1
Date: Monday, July 24, 2017 Sheet 13 of 17
5 4 3 2 1
 5 4 3 2 1

D D

POWER LED
VCC_5V

D4 BLUE LED
REG_PG_LED_R R235 1K

Q5 R309
Push Buttons
PWR_GD_LED DNI VCC_3.3V
FDV305N

S1 PB Switch
1 2 C10_NCONFIG
C205 0.1uF
Configuration LED VCC_3.3V PB Switch
S2
1 2 C10_RESETn
C204 0.1uF
D5 YELLOW_LED <4> C10_NCONFIG
SYS_CONF_DONE SYS_CONF_DONE_R R135 390
C C

<5> C10_RESETn

<7> SYS_CONF_DONE

User LED VCC_3.3V S3 PB Switch <8> VTAP_BYPASSn

1 2 USER_PB0 R137 10K
C206 0.1uF
D6 GREEN_LED
USER_LED0 USER_LED0_R R138 390 S4 PB Switch <5> USER_LED[0:3]
1 2 USER_PB1 R139 10K
D7 GREEN_LED C207 0.1uF <5> USER_PB[0:3]
USER_LED1 USER_LED1_R R140 390
S5 PB Switch <5> USER_DIP[0:2]
D8 GREEN_LED 1 2 USER_PB2 R141 10K
USER_LED2 USER_LED2_R R142 390 C208 0.1uF
<8> PWR_GD_LED
D9 GREEN_LED S6 PB Switch
USER_LED3 USER_LED3_R R143 390 1 2 USER_PB3 R144 10K
C209 0.1uF
B B

DIP Switches
VCC_3.3V
SW1
1 8 USER_DIP2 R145 10K
2 7 USER_DIP1 R146 10K
OPEN

3 6 USER_DIP0 R147 10K

4 5 VTAP_BYPASSn R148 10K

DIPSWITCH4

ON = 0 Logic 0 = Vitual JTAG Bypass

OFF = 1 Logic 1 = Vitual JTAG Enable
A A

Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Title
Cyclone 10 LP FPGA Evaluation Kit Board
Copyright (c) 2016, Intel Corporation All Rights Reserved
Size Document Number Rev
B 150-0321321-A1 (6XX-44504R) A1
Date: Monday, July 24, 2017 Sheet 14 of 17
5 4 3 2 1
 5 4 3 2 1

D D

Si5351A

VCC_3.3V VCC_3.3V

L10 L16
1.5A, 180 Ohm FB C72 1.5A, 180 Ohm FB
C67
C66 DNI 0.1uF
0.1uF U31
Y3
3 25.00MHz 1 10 R152 0 ENET_CLK_125M 3.3V CMOS
4 2 XA 2 VDD CLK0 9 R155 0 C10_CLK_ADJ 3.3V CMOS
XB 3 XA CLK1 8
System I2C
R263 0 4 XB GND 7
1

C73 DNI R264 0 5 SCL VDDO 6 R157 0 HBUS_CLK_50M 3.3V CMOS <8> SYS_I2C_SCL
SDA CLK2 <8> SYS_I2C_SDA
C C

SYS_I2C_SCL
Si5351A-B07321-GT
SYS_I2C_SDA

Use Clock GUI to Program Si5351A

Default Prequency:
CLK0: 125MHz Clocks
CLK1: 100MHz <4> C10_CLK50M
CLK2: 50MHz <4> ENET_CLK_125M
I2C Address: 0x60
<5> HBUS_CLK_50M

<5> C10_CLK_ADJ

<7> M10_CLK50M
50MHz Oscillator

VCC_3.3V
U20
B B
L12 3.3V_SI510 6
1.5A, 180 Ohm FB VDD 4 M10_CLK50M_R R160 33 M10_CLK50M 3.3V CMOS
C74 2 CLKp/1 5 C10_CLK50M_R R162 33 C10_CLK50M 3.3V CMOS
OE CLKn/2
0.1uF
3 1
GND NC

510MCA50M0000AAGR

A A

Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Title
Cyclone 10 LP FPGA Evaluation Kit Board
Copyright (c) 2016, Intel Corporation All Rights Reserved
Size Document Number Rev
B 150-0321321-A1 (6XX-44504R) A1
Date: Tuesday, May 16, 2017 Sheet 15 of 17
5 4 3 2 1
 5 4 3 2 1

D D

5V Input Selection, Protection and Control

R296 DNI
5V_DCIN VCC_5V_IN
5V DC Input C203 DNI
ID=2.1mm,OD=5.5mm VCC_5V

J12
1 D41 PMEG3050EP S D
2
C C
3 R164 DNI
R289 Q29 Q15 C200 R173
DC Input Jack 300 C201 R292 DMG2305UX C76 TP18
R290 1K G DNI 1K
10K
0.47uF 47uF
MMST3906-7-F R294
SOT-323 10
R300
DNI R165 DNI
D28
2 1
D20 DFLS240 BZX84C5V1 5.1V-ZENER
USB_5V R291
10K
D S

Q30
DNI
C210
G
DNI
R299 C211
B DNI B
DNI

R298
DNI

TP12 TP13 TP14 TP15 TP16 TP17

A A

Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Title
Cyclone 10 LP FPGA Evaluation Kit Board
Copyright (c) 2016, Intel Corporation All Rights Reserved
Size Document Number Rev
B 150-0321321-A1 (6XX-44504R) A1
Date: Tuesday, August 01, 2017 Sheet 16 of 17
5 4 3 2 1
 5 4 3 2 1

1.8V_VSENSE
VCC_1.2V (1.2V@2A Max.) VCC_1.8V (1.8V@0.6A Max.)
D VCC_5V D
VCC_3.3V C104 R197
VCC_5V U26
U25 VCC_1.2V 5 DNI 0 VCC_1.8V
C96 17 VCC_1.2V_PG 100K R189 14 VSENSE 7
R190 19 POK TP20 PVIN VOUT 8 TP22
22uF 20 PVIN 4 VOUT
10K PVIN VOUT 5 C97 R191 C98 C99 C100 C105 C166
VOUT 6 C107 C108 C112
VCC_1.2V_EN 18 VOUT 7 8.2pF 348K 22uF 22uF DNI R199 4.7uF DNI 13
ENABLE VOUT AVIN 10uF 10uF DNI
10K
VCC_5V 14 VCC_1.2V_FB
C101 VFB 4
16 VCC_1.8V_EN 12 VFB/NC4
DNI AVIN R192 ENABLE
10 2 C114 11
C102 11 TST2 PGND 3 340K 10 VS0
12 TST1 PGND 8 DNI 9 VS1
1uF TST0 PGND 9 VS2

NC(SW)0
NC(SW)1
NC(SW)2
NC(SW)3
NC(SW)4
PGND 1 6
NC1 AGND

PGND
PGND
15 R201 15 2
AGND 16 NC15 PGND 3
NC
0 NC16 PGND
EN5329QI EP5358HUI
1
13

21
22
23
24

25
26
C C

VCC_2.5V (2.5V@0.6A Max.) 2.5V_VSENSE

VCC_3.3V (3.3V@3A Max.)
C103 R198
VCC_5V VCC_5V U27
VCC_3.3V 5 DNI 0 VCC_2.5V
14 VSENSE 7
U23 VCC_3.3V PVIN VOUT 8 TP21
C83 17 VCC_3.3V_PG 100K R178 VOUT
R179 19 POK TP19
PVIN C106 C165
10K 22uF 20 4 C109 C110 C111
PVIN VOUT 5 R180 C87 R200 4.7uF DNI 13
C84 C85 C86
VOUT 6 AVIN 10uF 10uF DNI
VOUT 10K
VCC_3.3V_EN 18 7 8.2pF 348K 47uF 47uF DNI
ENABLE VOUT 4
B B
VCC_5V 14 VCC_3.3V_FB VCC_2.5V_EN 12 VFB/NC4
C88 VFB ENABLE
16 C113 11
DNI AVIN R181 10 VS0
10 2 DNI 9 VS1
C89 11 TST2 PGND 3 76.8K VS2
12 TST1 PGND 8 1 6
1uF TST0 PGND 9 15 NC1 AGND 2
NC(SW)0
NC(SW)1
NC(SW)2
NC(SW)3
NC(SW)4

PGND 16 NC15 PGND 3

NC16 PGND
PGND
PGND

15
AGND
NC

EP5358HUI
EN5339QI
1
13

21
22
23
24

25
26

<8> VCC_3.3V_PG

<8> VCC_1.2V_PG

A A

Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Title
Cyclone 10 LP FPGA Evaluation Kit Board
Copyright (c) 2016, Intel Corporation All Rights Reserved
Size Document Number Rev
B 150-0321321-A1 (6XX-44504R) A1
Date: Tuesday, May 16, 2017 Sheet 17 of 17
5 4 3 2 1