Sir Karimi - Microwind course-FSG PRESENTATION 5 NOV 2016 PDF

5 NOV 2016
INTRODUCTION TO
DIGITAL IC DESIGN USING
DSCH AND MICROWIND
EDITED BY:
ABDUL KARIMI HALIM
FKE,UITM
Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-0

OVERVIEW

The number of transistor will double in every 18 months

i.. Feature size scaling will help to improve speed, area and power
ii. Now at 22nm and 16nm technologies
iii. Use FinFET and UTB-SOI transistors

Design Abstraction Levels
SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
S D
n+ n+
[Rabaey,2002]
Fabrication and Layout Slide 4

DEVICES

nMOS Transistor
 Four terminals: gate, source, drain, body
 Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS)
capacitor
Source Gate Drain
– Even though gate is Polysilicon
no longer made of metal SiO2
n+ n+
Body
p bulk Si
0: Introduction CMOS VLSI Design 4th Ed. 7

pMOS Transistor
 Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO2
p+ p+
n bulk Si

Power Supply Voltage
 GND = 0 V
 In 1980’s, VDD = 5V
 VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
 VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
 FOLLOW TECHNOLOGY’S FEATURE SIZE
SCALING:
0.35 um,0.25 um,0.18 um,0.13 um, 90 nm,65 nm ….

FABRICATION
PROCESS

Fabrication Process of an INVERTER
Copyright © 2006 by Nelson, a division of Thomson Canada Limited 2-17
DESIGN RULES
Design For
Manufacturing

SOFTWARE

SOFTWARE
DSCH
SCHEMATIC DESIGN
AND SIMULATION
Open the Dsch Software!!

EXERCISE 1:
Drag some of the components

and connect the logics

SOFTWARE
MICROWIND
LAYOUT DESIGN
AND SIMULATION
Open the Microwind Software!!

EXERCISE 2:
Drag some of the components

Draw some boxes

CIRCUIT DESIGN

DESIGN FLOW
1.Design Statements
2.Specifications
3.Behaviors
4.Truth table
5.Simplified Expressions
6.Logic Gates
7.Circuits/Schematics
8.Layouts
9.Implimentation –DRC,LVS,GDS2/CIF
Transistors as Switches
• We can view MOS transistors as electrically

controlled switches
• Voltage at gate controls path from source to
g=0 g=1
drain
d d d
nMOS g OFF
ON
s s s
d d d
pMOS g OFF
ON
s s s
0: Introduction 52
Series and Parallel
a a a a a
0 0 1 1
•
g1
nMOS: 1 = ON g2
0 1 0 1
b
•
b b b b
pMOS: 0 = ON (a) OFF OFF OFF ON
• Series: both must be ON a

0
a
0
a
1
a
1
a
g1
• Parallel: either can be ON g2

b
0 1 0 1
b b b b
(b) ON OFF OFF OFF
a a a a a
g1 g2 0 0 0 1 1 0 1 1
b b b b b
(c) OFF ON ON ON
a a a a a
g1 g2 0 0 0 1 1 0 1 1
b b b b b
(d) ON ON ON OFF
1: Circuits & Layout 53

Complementary CMOS
• Complementary CMOS logic gates

– nMOS pull-down network pMOS
pull-up
– pMOS pull-up network

network
inputs
– a.k.a. static CMOS

output
nMOS
pull-down
network
• nMOS: pass good 0’s, so connect source to GND

• pMOS: pass good 1’s, so connect source to VDD
1: Circuits & Layout 54

Static CMOS Circuit Design
1. Static CMOS = 1 input connects to 1 NMOS and 1
PMOS
2. Use simplified expression to draw the transistor
connections (series/parallel).
3. Construct the circuit for pull down NMOS block based
on the rules below:
+ = parallel
* = series
4. Construct the circuit for pull up PMOS block based on the
rules below:
* = parallel
+ = series
5.Use boxes to represent transistors!!
CMOS Inverter
A INV Y VDD
A Y
A Y
0 1
GND
1 0
Y = A’
A Y
0: Introduction 56
CMOS NAND Gate
A
NAND Y
B Y
A
A B Y
B
0 0 1
0 1 1
1 0 1
1 1 0
Y = (A * B)’
0: Introduction 57
CMOS NOR Gate
A
A
NOR Y
B B
Y
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
Y = (A + B)’
0: Introduction 58
LAYOUT
TECHNIQUES

Gate Layout
• Layout can be very time consuming

– Design gates to fit together nicely
– Build a library of standard cells
• Standard cell design methodology
– VDD and GND should abut (standard height)
– Adjacent gates should satisfy design rules
– nMOS at bottom and pMOS at top
– All gates include well and substrate contacts
METHOD FOR LAYOUT
• BASIC GATES CKT TO LAYOUT

• SERIES/PARALLEL
• UYEMURA’S METHOD
• EULER PATH
Copyright © 2006 by Nelson, a division of Thomson Canada Limited
NMOS/PMOS
Circuit to Layout
• NMOS
• PMOS

Copyright © 2006 by Nelson, a division of Thomson Canada Limited
MULTI-FINGERED (FOLDED
TRANSISTOR)
• STEPS AND RULES(HANDOUT)
• TOO LONG
• REDUCE THE SIZES
ADVANCED CIRCUIT
DESIGN AND LAYOUT
• FLOORPLANNING
• PLACEMENT
• ROUTING

LAB TIME!!

1. BASIC NMOS CIRCUIT
AND LAYOUT: DESIGN AND
SIMULATION

2. BASIC PMOS CIRCUIT AND
LAYOUT: DESIGN AND
SIMULATION

3. INVERTER CIRCUIT AND
LAYOUT: DESIGN AND
SIMULATION

4. NAND CIRCUIT AND
LAYOUT: DESIGN AND
SIMULATION

5. NOR CIRCUIT AND
LAYOUT: DESIGN AND
SIMULATION

5. XOR CIRCUIT AND
LAYOUT: DESIGN AND
SIMULATION

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5 NOV 2016

Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-0

Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-1

Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-2

Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-3

Fabrication and Layout Slide 4

Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-6

no longer made of metal SiO2

0: Introduction CMOS VLSI Design 4th Ed. 7

0: Introduction CMOS VLSI Design 4th Ed. 8

0: Introduction CMOS VLSI Design 4th Ed. 9

Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-10

Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-21

Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-33

Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-34

Drag some of the components

Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-38

Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-40

Drag some of the components

Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-48

Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-50

• We can view MOS transistors as electrically

• Series: both must be ON a

• Parallel: either can be ON g2

1: Circuits & Layout 53

• Complementary CMOS logic gates

– pMOS pull-up network

– a.k.a. static CMOS

• nMOS: pass good 0’s, so connect source to GND

1: Circuits & Layout 54

Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-59

• Layout can be very time consuming

• BASIC GATES CKT TO LAYOUT

Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-65

Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-76

Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-83

Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-84

Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-87

Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-88

Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-89

Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-90

Copyright © 2006 by Nelson, a division of Thomson Canada Limited A-91

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