Physical Structure

1
of CMOS ICs - 2
Lecture# 07
VLSI Design
2 Electrical Conduction in Silicon
 Charge Carriers

 mass-action law (number of electrons and holes in equilibrium)

 𝑛𝑝 𝑛
 n is number of electrons
 p is number of holes

 So if doping concentration is high, and, each atom donates

one electron
 # of electrons (𝑛 ) in n-type material, will be 𝒏𝒏 𝑵𝒅
 # of holes (𝑝 ) in n-type material, will be given by mass-action
𝒏𝟐𝒊
law, 𝒑𝒏
𝑵𝒅

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

3 Example 3.1
 Suppose that the donor doping density is 𝑁 2 10 cm .
The intrinsic carrier density is 𝑛 1.45 10 cm . Which
material is this (n or p type). Find electron and hole
concentration.

Please note that this is an n-type semiconductor, where

 𝑛 ≫𝑝 electrons are majority carriers & holes are minority
carriers
 𝑝 𝑛 hole density is even less than that of intrinsic material

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

4 Electrical Conduction in Silicon
 Doped Semiconductor

 The conductivity 𝜎 of a semiconductor having carrier

densities 𝑛 and 𝑝
𝜎 𝑞 𝜇 𝑛 𝜇 𝑝
 𝑞 is charge on an electron
 𝜇 and 𝜇 are electron and hole mobilities, respectively.
 Mobility have units of cm /V−sec, depicts how mobile a particle
is.

Large value of 𝝁 implies ?

relatively free motion

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

5 Electrical Conduction in Silicon
 Mobility Values

 For intrinsic silicon, at room temperature

 𝜇 1360 cm /V−sec and 𝜇 480 cm /V−sec
What this implies ?
 electrons can move freely compared to holes
 For the above value of mobilities
 𝜎 4.27 10 Ω 𝑐𝑚 𝜌 2.34 10 Ω−cm
 Comparing with quartz glass which has resistivity of 𝜌 10 Ω−cm
What this high value indicate ?
 Approximating 𝜎 𝑞 𝜇 𝑛 𝜇 𝑝
 𝜎 𝑞𝜇 𝑛 (nn >> pn)
 𝜎 𝑞𝜇 𝑝 (pn >> nn)

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

6 Class Exercise 1

 Consider a sample of silicon that is doped p-type with boron

added at a density of 𝑁 10 cm .
 The majority charge carriers are holes, with density
 𝑝 10 cm

 Find density of minority charge carriers (𝑛 )

 Find conductivity (𝜎) and resistivity 𝜌 of material

Consider
𝑛 1.45 10 cm
𝜇 1350 cm /V−sec
𝜇 450 cm /V−sec
𝑞 1.6 10 𝐶

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

7 Solution to Class Exercise 1

 Consider a sample of silicon that is doped p-type with boron

added at a density of 𝑁 10 cm .
 The majority charge carriers are holes, with density
 𝑝 10 cm

 The minority charge carriers are electrons, with density

.
 𝑛 2.2 10 cm

 Conductivity of the doped semiconductor is

 𝜎 𝑞 𝜇 𝑛 𝜇 𝑝 1.6 10 1350 2.2 10 450 10
 𝜎 1.6 10 2.97 10 4.5 10 0.072 Ω−cm

Resistivity
1
𝜌 13.9 Ω−cm
0.072 Ω−cm

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

8 Physical Structure of MOSFETs
 Doped Regions

 We have now build bases towards understanding the

 physical structure of MOSFETs
 The polarity of nMOS or pMOS is defined by
 Polarity of source and drain regions
 nMOS has n+ source and drain, while pMOS has p+ source and
drain regions
 The devices are designed so that the channel has
 Same polarity as of source and drain, only when device is
conducting

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

9 Physical Structure of MOSFETs
 Doped Regions

Gate Gate

Source Drain Source Drain

nMOS pMOS

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

10 Physical Structure of MOSFETs
 nMOS

 An nMOS has its drain and source

regions labeled as “n+” Gat e

 Indicating they are heavily doped,

Source Drain
around 𝑁 10 cm
 p-substrate region is p-type, with normal
doping 𝑁 10 cm
 PN junctions are formed between
substrate and n+ regions
 So any current flow is blocked

nMOS

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

11 Physical Structure of MOSFETs
 pMOS

 A pMOS has its drain and source

regions labeled as “p+” Gat e

 Indicating they are heavily doped, Source Drain

Large 𝑁
 In order to create PN junction to block
current flow
 n-well is form within p-substrate
 n-well region is n-type, with normal
doping, medium-low 𝑁 pMOS
 nMOS and pMOS have opposite
electrical characteristics

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

12 Physical Structure of MOSFETs
 Current Flow in nMOS

 The dashed-line shows capacitor in a

MOS
 MOSFET gate, per unit area capacitance
MOSFET is derived from
is defined as
• M (Metal used in earlier gates)
 Oxide Capacitance 𝐶 , has units • O (Oxide, Gate oxide)
F/cm • S (Semiconductor, Substrate)
 So, gate capacitance (for a gate with
area 𝐴 ) 𝑉

 𝐶 𝐴 𝐶 𝑊𝐿𝐶 Gate
Oxide Gate
 We have permittivity for free space
𝑡

  
 𝑆𝑖𝑂 permittivity 𝜖 3.9 𝜖
n n
 𝜖 8.854 10 F⁄cm
 Thinner gate oxide (small 𝑡 ) is desirable p-substrate
 Nowadays 𝑡 10 nm 100 Å

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

13 Class Exercise 2

 Consider a gate oxide that has thickness of 𝑡 50 Å, 𝑊 1 μm

and 𝐿 0.4 μm. Find gate capacitance 𝑉

Gate
 Oxide capacitance Oxide Gate
. . / 𝑡

  
 𝐶 6.91 10 F/cm n n

 Gate Area p-substrate

 𝐴 1 10 cm 0.4 10 cm 4 10 cm
 Gate capacitance 𝐶 𝐶 𝐴
 𝐶 6.91 10 F/cm 4 10 cm 𝐶 𝜖 ⁄𝑡 3.9 𝜖 ⁄𝑡
 𝐶 2.76 10 F 2.76 fF 𝜖 8.854 10 F/cm
𝐴 𝑊 𝐿

Please be careful with units, all variables must have same units like m or
cm
• 1 𝑚 100 𝑐𝑚, 1 𝑐𝑚 0.01 𝑚 1 10 𝑚,
• 1 𝑐𝑚 1 10 𝑚 , 1 𝑐𝑚 1 10 𝑚

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

14 Physical Structure of MOSFETs
 Current Flow in nMOS

 When gate voltage (𝑉 ) increase beyond threshold voltage (𝑉 )

 An electron inversion layer (channel) is formed between drain and source
 𝑉 is defined by fabrication sequence.
 The channel charge (in substrate between drain and source) is given
by
 𝑄 𝐶 𝑉 𝑉 from 𝑄 𝐶𝑉
 -ive sign due to the fact that electronic (negative) charge is being
measured
 We know current is rate of charge flow
 𝐼 ;units C/sec

 𝜏 is channel transit time

 Physically, 𝜏 is average time for an electron to go from source to
drain.
 𝜏 ;where 𝐿 is channel length, 𝑣 is particle velocity

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

15 Assignment No 2, Question No 1

 Derive following equation of pMOS device resistance and show

how voltage is applied between source and drain terminals, hole
mobility and gate capacitance contribute to the resistance.

1
𝑅
𝛽 𝑉 𝑉

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

16 CMOS Layers

 We have understood, nMOS and pMOS

 Let us now examine them combined as CMOS ICs
 We choose a simple process of understanding CMOS ICs
 That is n-well process
 CMOS fabrication process is the sequence of steps
 To convert a bare wafer of silicon in to an electronic integrated circuit.
 Let us concentrate (for now) on the final structure
 Which results from CMOS fabrication process

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 17 CMOS Layers
 MOSFET Layers
 The n-well process starts with p-substrate
 Base layer for all the transistors
 nMOS can be directly fabricated into p-type substrate
 N-well regions are added to accommodate pMOS
 Layers implies region with
 distinct electrical characteristics which may be at same geometrical
level

Layers in the
nMOS nMOS
FOX
pMOS pMOS drawing
Gate  1. p-substrate
Gate  2. n-well
+
n
+
n n
+
n
+ +
p
+
p p
+ +
p oxide 3. n+ (drain/source)
n‐well 4. p+ (drain/source)
p-substrate 5. gate oxide
6. gate (polysilicon)

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 18 CMOS Layers
 MOSFET Layers
 The region labeled as FOX is field oxide, which is
 Recessed insulating glass to provide electrical isolation between
MOSFETs

Layers in the
nMOS nMOS
FOX
pMOS pMOS drawing
Gate  1. p-substrate
Gate  2. n-well
+
n
+
n n
+
n
+ +
p
+
p p
+ +
p oxide 3. n+ (drain/source)
n‐well 4. p+ (drain/source)
p-substrate 5. gate oxide
6. gate (polysilicon)

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

19 CMOS Layers
 MOSFET Layers

 Consider the top view, showing pattern of layers

 n+, p+, polysilicon and n-well
 p-substrate and oxide layers
 are implied

 Every unoccupied region is

 Inserted with FOX, for isolation

nMOS nMOS pMOS pMOS

n+ n+ n+ n+ p+ p+ p+ p+

n‐well

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 20 CMOS Layers
 Interconnects

 Once the transistor layers are defined,

 Conductive layers are added (separated by glass from each other)
 Modern fabrication processes allow ten or more metal interconnect
layers
 To allow complex wiring Oxide layers are added one by one to
provide insulation between
 Consider the figure
interconnect layers
 With two metal layers
 Active contact (metal), connects Ox3
Metal2
 Active layer to metal1 Via 1
Ox2
 Via1 connects Metal1
 Metal1 to metal2
Active Contact Ox1
 Active contacts and Vias are added + + + +
n n n n
 By creating holes in oxide layers

p‐substrate

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 21 CMOS Layers
 Interconnects

 Metal Layers are Electrically isolated from each other

 Transistors are separated by glass.
 Electrical contact between adjacent conducting layers need
contact cuts and vias.

Ox3
Metal2
Via 1
Ox2
Metal1
Active Contact Ox1
+ + + +
n n n n

p‐substrate

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

22 CMOS Layers
 Interconnects Top View

 Top view of an interconnect layout example

 Is shown in figure
 Gate Contact is used to connect
 Polysilicon gate to metal1 layer
 Active Contacts are used to connect Gate Gate

 Connection b/w metal1 and drain/source

Contact Metal1

Metal2
 Via is used to connect Metal1
 Metal1 layer to Metal 2 layer
 All metal layers are isolated Active
 Except when connected to other layers Contacts
 Using vias and contacts Via 1

Metal1

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

23 Designing MOSFET Arrays

 CMOS logic gates are switching networks

 Containing MOSFETs connected together in series and parallel
 To achieve desired functionality
 It is time to see the gates we designed using static CMOS logic
 At actual layout level
 Consider a simple n-stack, where two nMOS are in series
 note shared n+ region to reduce size

A B A B

A B
n +
n +
n + n+ n+ n+

P‐substrate

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 24 Series connected MOSFETs

 Consider a 3-nMOS chain, connected serially

 Shows width of the transistors, along with the pattern
 Metal lines added to connect 𝑥 and 𝑦 to other parts of the IC
 Using Active Contacts

A B C

W y
A B C

x y x

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad