Session T2G
Work in Progress – A Rapid Design Methodology for
FPGA-based Processor Platform Design Education
Yong-Kyu Jung
IEEE Senior Member, Texas A&M University-College Station, jung@entc.tamu.edu
Abstract –A rapid register-transfer level (RTL) embedded
processor platform design methodology that is included an
educational tool for a special topic is introduced. In the
special topic, rapid digital system design from digital
fundamentals to processor platforms is practiced using a
top-down design methodology with both Verilog hardware
description language (HDL) and VHDL. In addition, all of
the RTL design and verification processes can be rapidly
and systematically performed through the methodology.
Furthermore, a hierarchical RTL post-simulation
verification methodology and a supporting tool can
provide a rapid, flexible, and affordable verification
environment for the field-programmable gate array
(FPGA)-based embedded processor platform developed in
the classroom. This methodology will lead to the rapid
development of embedded processor platforms for use in
academia.
Index Terms –FPGA-based embedded processor design
education, HDLs, RTL post-simulation verification
methodology, top-down/bottom-up design methodology.
INTRODUCTION
In general, students take a series of digital design courses to
learn microprocessor system design. For instance, courses on
Digital Fundamentals, Logic Circuits and Computer
Architectures are typically taught sequentially. To accelerate
the practical learning process, digital system designs using
FPGAs are often added to existing curricula. For instance,
FPGA-based platforms along with configurable processor
cores have been successfully used for various large classroom
projects [1] within a semester.
We are continuously challenged, however, not only to
reduce the time spent teaching these topics, but also to adapt a
rapid digital system design process for smoother migration
toward the next level of courses. To achieve more efficient
teaching and smoother migration, I started to develop a
customized rapid processor platform design environment
based on a top-down design methodology for classroom
instruction.
Since a soft RTL processor core can be considered similar
to a chip, a rapid RTL embedded processor platform design
(EP2D) methodology was developed using both VHDL and
Verilog HDL-based reusable, hierarchical, modular design
libraries to accelerate the design process in classroom projects.
Section 1 introduces the rapid EP2D methodology used
for a special topic. In particular, a rapid RTL post-simulation
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35th ASEE/IEEE Frontiers in Education Conference
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verification process which bridges the gap between research
and education in rapid embedded processor platform design is
presented in Section 2. Conclusions and future direction are
addressed in Section 3.
AN EMBEDDED PROCESSOR PLATFORM DESIGN
METHODOLOGY FOR RAPID DIGITAL DESIGN EDUCATION
In order to teach rapid embedded processor design using a top-
down design methodology, selective contemporary computer
architectures were reviewed prior to design instruction set
architecture (ISA) followed by behavioral implementation.
Finally, an RTL embedded processor platform was developed
within a single semester using FPGAs and associated tool sets
under a bottom-up approach.
In the special topic, RTL design and verification are
highly emphasized. To achieve digital system design from
fundamentals to processor platforms within a semester using
the EP2D methodology, ‘rapid design accomplishment’ was
considered one of the key aspects. Two others - ‘continuous
design improvement’ and ‘various design diversity’ - were
considered necessary in order to leverage this course
continuously, as well as to allow smooth migration to higher
level courses.
I. Rapid Design Accomplishment
HDL-based design and reuse constitute one viable approach to
achieve rapid digital system design in RTL. Since every
design must be verified, we used both simulation and
emulation. The combined use of electronics design automation
(EDA) tools for simulation and the fast, flexible post-
simulation tool developed for the EP2D methodology for
emulation, respectively, can be preferred for FPGA-based
classroom projects. In particular, both intensive and extensive
verification can also be rapidly done applying several
benchmarks to the emulation tool, which can automatically
execute the benchmarks. Finally, systematic design evaluation
can perform in terms of design accuracy and performance.
II. Continuous Design Improvement
To enhance a digital design course continuously, HDL codes
have been developed with the existing codes and for the future
reuse. A hierarchical, modular HDL design library can provide
efficient dissemination as well as rapid, accurate reuse.
According to the hierarchical, modular library structure,
adding advanced design can be done systematically for future
rapid design. For instance, instruction in digital fundamentals
such as combinational and sequential logic design is directly
October 19 – 22, 2005, Indianapolis, IN

applied for component level design. Block level design can be
rapidly done using the components developed with glue logic.
Eventually, the blocks can be interfaced with one another to
build a system in RTL quickly. As expected, continuous
design upgrades and changes can also be accomplished
systematically and rapidly. Just as examples are to teach, so
various hardware models in the library can contribute
effectively to student learning digital system design.
III. Various Design Diversity
Since students do not always possess equal design capability,
various design tasks can motivate them to higher achievement.
In the EP2D methodology different kinds of embedded
processor design tasks can be used for different levels of
students. For example, a single pipelined reduced instruction
set computer (RISC) and a superscalar RISC processor are
used for preliminary and advanced design tasks, respectively.
In addition, students’ design experience using the EP2D
methodology can facilitate advancement to the next level of
digital system design courses. As a result, students can acquire
knowledge and enrich their design experience while designing
different architectures through multiple design abstracts.
A RAPID RTL POST-SIMULATION VERIFICATION
METHODOLOGY USING FAST, FLEXIBLE EMULATION TOOL
In the EP2D methodology developed for FPGA-based rapid
and accurate verification, three verification levels -
component-, block-, and system-level - are typically
performed in order from the component-level to the system-
level. To perform in each verification level efficiently, an RTL
post-simulation verification tool has been developed and used
as shown in Figure 1.
FIGURE 1
A FAST, FLEXIBLE RTL EMULATION TOOL.
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35th ASEE/IEEE Frontiers in Education Conference
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Session T2G
I. A Rapid, Flexible RTL Post-simulation Verification
At the top level, each new component can be verified using
RTL simulations. Depending on the complexity and scale of
the component, further RTL emulation may be recommended.
Once components are all verified, a block can usually be
implemented by integrating the components with glue logics.
At this level of verification, most of the primary interface
verification between the components can be efficiently and
rapidly done under a manual, off-chip clock synchronized
RTL emulation. As it is with block-level verification,
intensive system-level RTL emulation is required prior to
performing exhaustive, extensive system-level emulation. At
the beginning of the system-level verification, a group of tests
can be performed either manually or automatically. These tests
can represent the same or similar types of operations or
instructions for screening errors. A full-scale extensive
verification using entire benchmarks can finally be undertaken
after screening and debugging trivial errors.
II. An Emulation Tool for Fast, Flexible RTL Verification
Verifying an embedded processor platform in RTL requires
running enormous numbers of instructions designed in the
processor. Tracing all of the tested instructions is a daunting
task. Fast RTL emulation for instruction testing contributes to
the speed of the overall RTL verification process. To achieve
this goal, an RTL post-simulation verification tool was used
throughout the design process.
There are three modules to support flexible emulation: the
signal generation, storage, and I/O modules. Using these
modules, the processor platform operations can be verified
through multiple levels depending on the emulation mode
configured. There are two major emulation modes, a manual,
off-chip clock mode and an automated, on-chip clock mode.
For instance, manual tracing using more detail tracing modes
followed by automated high-speed on-chip extensive testing
can be performed.
CONCLUSIONS
The rapid processor platform design methodology was
successfully used throughout the design project. In particular,
the rapid RTL verification methodology and the fast, flexible
emulation tool can leverage the FPGA-based embedded
processor platform design education. Consequently, the entire
digital design process, from the digital fundamentals to
processor platforms, was performed within a single semester.
As technologies evolve, this course will be continuously
supplemented with new technologies and educational
materials. As an extended effort, I plan to develop a set of the
graphical user interface (GUI)-based tools to assist to design
industry quality of processor platforms in the classroom.
REFERENCES
[1] T. Hall and J. Hamblen, “System-on-a-Programmable-Chip
Development Platforms in the Classroom”, IEEE Trans. on Education,
2004.
October 19 – 22, 2005, Indianapolis, IN