PCS-978

PCS-978
Transformer Relay
Instruction Manual
NR Electric Co., Ltd.

Preface
Preface
Introduction
This guide and the relevant operating or service manual documentation for the equipment provide
full information on safe handling, commissioning and testing of this equipment.
Documentation for equipment ordered from NR is dispatched separately from manufactured goods
and may not be received at the same time. Therefore, this guide is provided to ensure that printed
information normally present on equipment is fully understood by the recipient.
Before carrying out any work on the equipment, the user should be familiar with the contents of
this manual, and read relevant chapter carefully.
This chapter describes the safety precautions recommended when using the equipment. Before
installing and using the equipment, this chapter must be thoroughly read and understood.
Health and Safety

The information in this chapter of the equipment documentation is intended to ensure that
equipment is properly installed and handled in order to maintain it in a safe condition.
When electrical equipment is in operation, dangerous voltages will be present in certain parts of
the equipment. Failure to observe warning notices, incorrect use, or improper use may endanger
personnel and equipment and cause personal injury or physical damage.
Before working in the terminal strip area, the equipment must be isolated.
Proper and safe operation of the equipment depends on appropriate shipping and handling,
proper storage, installation and commissioning, and on careful operation, maintenance and
servicing. For this reason, only qualified personnel may work on or operate the equipment.
Qualified personnel are individuals who:
 Are familiar with the installation, commissioning, and operation of the equipment and of the
system to which it is being connected;
 Are able to safely perform switching operations in accordance with accepted safety
engineering practices and are authorized to energize and de-energize equipment and to
isolate, ground, and label it;
 Are trained in the care and use of safety apparatus in accordance with safety engineering
practices;
 Are trained in emergency procedures (first aid).
Instructions and Warnings

The following indicators and standard definitions are used:
PCS-978 Transformer Relay i

Date: 2016-06-22
Preface
DANGER! means that death, severe personal injury and considerable equipment damage
will occur if safety precautions are disregarded.
WARNING! means that death, severe personal and considerable equipment damage
could occur if safety precautions are disregarded.
CAUTION! means that light personal injury or equipment damage may occur if safety
precautions are disregarded.
NOTICE! is particularly applies to damage to device and to resulting damage of the protected
equipment.
DANGER!
NEVER allow a open current transformer (CT) secondary circuit connected to this
device while the primary system is live. Open CT circuit will produce a dangerously high
voltage that cause death.
WARNING!
ONLY qualified personnel should work on or in the vicinity of this device. This personnel
MUST be familiar with all safety regulations and service procedures described in this
manual. During operating of electrical device, certain part of the device is under high
voltage. Severe personal injury and significant device damage could result from
improper behavior.
WARNING!
Do NOT touch the exposed terminals of this device while the power supply is on. The
generated high voltage causes death, injury, and device damage.
WARNING!
Thirty seconds is NECESSARY for discharging the voltage. Hazardous voltage can be
present in the DC circuit just after switching off the DC power supply.
CAUTION!
 Earthing
Securely earthed the earthing terminal of the device.
 Operating environment
ONLY use the device within the range of ambient environment and in an
ii PCS-978 Transformer Relay

Date: 2016-06-22
Preface
environment free of abnormal vibration.
 Ratings
Check the input ratings BEFORE applying AC voltage/current and power supply to
the device.
 Printed circuit board
Do NOT attach or remove printed circuit board if the device is powered on.
 External circuit
Check the supply voltage used when connecting the device output contacts to
external circuits, in order to prevent overheating.
 Connection cable
Carefully handle connection cables without applying excessive force.
NOTICE!
The firmware may be upgraded to add new features or enhance/modify existing

features, please MAKE SURE that the version of this manual is compatible with the
product in your hand.
Copyright © 2016 NR. All rights reserved.
We reserve all rights to this document and to the information contained herein. Improper use in particular reproduction and dissemination
to third parties is strictly forbidden except where expressly authorized.
The information in this manual is carefully checked periodically, and necessary corrections will be included in future editions. If
nevertheless any errors are detected, suggestions for correction or improvement are greatly appreciated.
We reserve the rights to make technical improvements without notice.
NR ELECTRIC CO., LTD. Tel: +86-25-87178888

Headquarters: 69, Suyuan Avenue, Jiangning, Nanjing 211102, China Fax: +86-25-87178999
Manufactory: 18, Xinfeng Road, Jiangning, Nanjing 211111, China Website: www.nrelect.com, www.nrec.com
P/N: ZL_PCS-978_X_Instruction Manual_EN_Overseas General_X Version: R2.10
PCS-978 Transformer Relay iii

Date: 2016-06-22
Preface
Documentation Structure
The manual provides a functional and technical description of this relay and a comprehensive set
of instructions for the relay’s use and application.
All contents provided by this manual are summarized as below:
1 Introduction
Briefly introduce the application, functions and features about this device.
2 Technical Data
Introduce the technical data about this relay, such as electrical specifications, mechanical
specifications, ambient temperature and humidity range, communication port parameters, type
tests, setting ranges and accuracy limits and the certifications that our products have passed.
3 Operation Theory
Introduce a comprehensive and detailed functional description of all protective elements.
4 Supervision
Introduce the automatic self-supervision function of this device.
5 Management
Introduce the management function (measurement and recording) of this device.
6 Hardware
Introduce the main function carried out by each plug-in module of this device and providing the
definition of pins of each plug-in module.
7 Settings
List settings including system settings, communication settings, label settings, logic links and etc.,
and some notes about the setting application.
8 Human Machine Interface

Introduce the hardware of the human machine interface (HMI) module and a detailed guide for the
user how to use this relay through HMI. It also lists all the information which can be view through
HMI, such as settings, measurements, all kinds of reports etc.
9 Configurable Function
Introduce configurable function of the device and all configurable signals are listed.
10 Communication
Introduce the communication port and protocol which this relay can support, IEC60970-5-103,
IEC61850 and DNP3.0 protocols are introduced in details.
11 Installation
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Date: 2016-06-22
Preface
Introduce the recommendations on unpacking, handling, inspection and storage of this relay. A
guide to the mechanical and electrical installation of this relay is also provided, incorporating
earthing recommendations. A typical wiring connection to this relay is indicated.
12 Commissioning
Introduce how to commission this relay, comprising checks on the calibration and functionality of
this relay.
13 Maintenance
A general maintenance policy for this relay is outlined.
14 Decommissioning and Disposal

A general decommissioning and disposal policy for this relay is outlined.
15 Manual Version History

List the instruction manual version and the modification history records.
Typographic and Graphical Conventions
Deviations may be permitted in drawings and tables when the type of designator can be obviously
derived from the illustration.
The following symbols are used in drawings:
&
AND gate
≥1
OR gate
Comparator
BI Binary signal via opto-coupler
SET I> Input signal from comparator with setting
EN Input signal of logic setting for function enabling
SIG Input of binary signal except those signals via opto-coupler
Input of other signal

OTH
PCS-978 Transformer Relay v

Date: 2016-06-22
Preface
XXX Output signal
Timer
t
Timer (optional definite-time or inverse-time characteristic)
t
xxms xxms
Timer [delay pickup (xxms), delay dropoff (xxms), non-settable]
[t1] 0ms
Timer (t1: delay pickup, settable)
0ms [t2]
Timer (t2: delay dropoff, settable)
[t1] [t2]
Timer (t1: delay pickup, t2: delay dropoff, settable)
IDMT Timer (inverse-time characteristic)

*
Instrument current transformer

*
Instrument voltage transformer
---xxx is the symbol
Symbol Corresponding Relationship
Basic
A, B, C L1, L2, L3 R, Y, B
AN, BN, CN L1N, L2N, L3N RN,YN, BN
ABC L123 RYB
U (voltage) V U
Example
Ia, Ib, Ic, I0 IL1, IL2, IL3, IN IR, IY, IB, IN
Ua, Ub, Uc VL1, VL2, VL3 UR, UY, UB
Uab, Ubc, Uca VL12, VL23, VL31 URY, UYB, UBR
U0, U1, U2 VN, V1, V2 UN, U1, U2
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Date: 2016-06-22
1 Introduction
1 Introduction
Table of Contents
1 Introduction 1-a
1.1 Application ....................................................................................................... 1-1
1.2 Functions ......................................................................................................... 1-5
1.2.1 Protection Functions ............................................................................................................ 1-5
1.2.2 Measurements ...................................................................................................................... 1-9
1.2.3 Configurable Functions ........................................................................................................ 1-9
1.2.4 Miscellaneous Functions ...................................................................................................... 1-9
1.2.5 Communication .................................................................................................................. 1-10
1.2.6 User Interface ..................................................................................................................... 1-10
1.3 Features ......................................................................................................... 1-10
List of Figures
Figure 1.1-1 2-winding transformer ........................................................................................... 1-1
Figure 1.1-2 3-winding transformer ........................................................................................... 1-1
Figure 1.1-3 autotransformer with two sides ........................................................................... 1-2
Figure 1.1-4 autotransformer with three sides ......................................................................... 1-2
Figure 1.1-5 Typical application of a 3-windings transformer................................................ 1-3
Figure 1.1-6 Typical application of an auto-transformer......................................................... 1-3
Figure 1.1-7 Typical application of a shunt reactor ................................................................. 1-4
PCS-978 Transformer Relay 1-a

Date: 2015-01-12
1 Introduction
1-b PCS-978 Transformer Relay
Date: 2015-01-12
1 Introduction
1.1 Application
PCS-978 can be applied for a two-winding transformer, three-winding transformer or

auto-transformer in any voltage level, or a shunt reactor. PCS-978 provides full transformer
protections which are configurable by user. Ancillary functions of fault diagnostic, disturbance
records, event records and communication function are integrated in the device.
PCS-978 is adaptive to the following 2/3-windings transformers or autotransformer.
Figure 1.1-1 2-winding transformer
Figure 1.1-2 3-winding transformer
PCS-978 Transformer Relay 1-1

Date: 2012-10-08
1 Introduction
Figure 1.1-3 autotransformer with two sides
Figure 1.1-4 autotransformer with three sides
The function diagrams for protecting a 3-windings transformer, an auto-transformer and a reactor
are respectively shown below.
1-2 PCS-978 Transformer Relay

Date: 2012-12-08
1 Introduction
3I0
HVS
49 62PD 50BF 50/51G
87T 50/51Q 51PAlm 21

*
50/51P
LVS
*
*
MR
Mechanical signals or transducer
* * signals from transformer
26
24 59P 81U
MVS
59G 27P 81O 59GAlm 64REF

3U0
Figure 1.1-5 Typical application of a 3-windings transformer

3I0
HVS
49 62PD 50/51Q 50BF

*
87W 51PAlm 87T 64REF 50/51G

*
*
* MR 21
*
Mechanical signals or transducer

signals from transformer
26
*
MVS
81O 81U 24 50/51P
* 59G 27P 59P 59GAlm

3U0
LVS
Figure 1.1-6 Typical application of an auto-transformer

Date: 2012-10-08
1 Introduction
52 Bus1
3U0
Line
* * *
3I0
50/51P 21IT 87R
52
49 50/51G
Shunt reactor
Mechanical signals or
MR
transducer signals from reactor
52
3I0
Bus2 * * *
Neutral earthing reactor
Figure 1.1-7 Typical application of a shunt reactor
NOTICE!
DPFC is the abbreviation of “Deviation of Power Frequency Component”. In case of a

fault occurred in the power system, the fault component could be analyzed into three
parts: the power frequency components before the fault, the power frequency variables
during the fault and the transient variables during the fault. DPFC is the power frequency
variable during the fault.
1. Transformer
No. Function ANSI

1 Transformer differential protection 87T
2 Restricted earth-fault protection 64REF
3 Winding differential protection 87W
4 Phase overcurrent protection 50/51P
5 Earth fault protection 50/51G
6 Negative-sequence overcurrent protection 50/51Q
7 Overfrequency protection 81O
8 Underfrequency protection 81U

Date: 2012-12-08
1 Introduction
9 Overexcitation protection 24
10 Impedance protection 21
11 Overvoltage protection 59P
12 Undervoltage protection 27P
13 Residual overvoltage protection 59G
14 Residual overvoltage alarm 59GAlm
15 Thermal overload protection 49
16 Breaker failure protection 50BF
17 Pole disagreement protection 62PD
18 Phase overcurrent alarm 51PAlm
19 Mechanical protection MR
20 Temperature protection 26
21 VT circuit failure supervision VTS
22 CT circuit failure supervision CTS
2. Reactor
No. Function ANSI

1 Reactor biased current differential protection 87R
2 Inter-turn fault protection 21IT
3 Phase overcurrent protection 50/51P
4 Earth fault protection 50/51G
5 Thermal overload protection 49
6 Mechanical protection MR
7 VT circuit failure supervision VTS
8 CT circuit failure supervision CTS
1.2 Functions
1.2.1 Protection Functions

1. Transformer
 Transformer differential protection
 Biased DPFC differential protection
 Biased differential protection with three slopes
 Unrestrained instantaneous differential protection
 Optional inrush current distinguished principles: harmonic criterion or waveform distortion
 Optional harmonic blocking modes: self-adaptive blocking mode and phase-to-phase

cross blocking mode
 Overexciation detection: fifth harmonic or third harmonic criterion

Date: 2012-10-08
1 Introduction
 Optional transfer methods: △ →Y or Y→△
 Independent CT saturation criterion
 Differential CT circuit failure supervision
 Restricted earth-fault protection (REF)
 CT transient detection
 CT saturation detection based on 2nd and 3rd harmonics
 Winding differential protection
 CT transient detection
 CT saturation detection based on 2nd and 3rd harmonics
 Phase Overcurrent Protection
 Four stages phase overcurrent protection with independent logic, voltage control element
and directionality (forward direction, reverse direction or non-directional)
 Stage 1, 2 and 3 are definite-time characteristic.
 Stage 4 can be selected as definite-time or inverse-time characteristic.
 Second harmonic blocking
 Earth fault protection
 Four stages earth fault protection with independent logic and directionality (forward
direction, reverse direction or non-directional)
 Negative-sequence overcurrent protection
 Two stages negative-sequence overcurrent protection with independent logic
 Stage 1 is definite-time characteristic.
 Phase overvoltage protection
 Two stages phase overvoltage protection with independent logic
 Optional phase voltage or phase-to-phase voltage

Date: 2012-12-08
1 Introduction
 Optional “1-out-of-3” or “3-out-of-3” logic
 Residual overvoltage protection
 Two-stage residual overvoltage protection with independent logic
 Undervoltage protection
 Four stages definite-time undervoltage protection with independent logic
 du/dt blocking
 Thermal overload protection
 Two stages thermal overload protection, and one stage for alarm purpose and the other
stage for trip purpose.
 Impedance protection
 Two stages phase-to-phase impedance elements
 Two stages phase-to-ground impedance elements
 Power swing blocking releasing
 Frequency protection
 Four stages overfrequency protection
 Four stages underfrequency protection
 df/dt block criterion for underfrequency protection
 Overexcitation protection
 Two stages definite-time overexcitation protection
 Stage 1 of definite-time overexcitation protection for trip purpose
 Stage 2 of definite-time overexcitation protection for alarm purpose
 One stage inverse-time overexcitation protection for both alarm purpose and trip purpose
 Residual overvoltage alarm
 One stage residual overvoltage alarm
 Optional definite-time or inverse-time characteristic
 Phase overcurrent alarm
 Two stages definite-time phase overcurrent alarm function with independent logic
 Breaker failure protection

Date: 2012-10-08
1 Introduction
 Pole discrepancy protection
 Mechanical Protection
 4 mechanical signal input channels for tripping instantaneously or with time delay
 Temperature Protection
 6 DC signals (4~20mA or 0~5V) from external temperature transducers
2. Reactor
 Reactor differential protection
 Biased DPFC differential protection
 Biased current differential protection
 Independent CT saturation criterion
 Harmonic blocking criterion
 Differential CT circuit failure supervision
 Inter-turn fault protection
 Zero-sequence power directional element and zero-sequence impedance element
 CT and VT circuit failure blocking
 Phase Overcurrent Protection
 Four stages phase overcurrent protection with independent logic and voltage control
element
 Earth fault protection
 Four stages earth fault protection with independent logic
 Thermal overload protection
 Two stages thermal overload protection, and one stage for alarm purpose and the other
stage for trip purpose.
 Mechanical Protection

Date: 2012-12-08
1 Introduction
 4 mechanical signal input channels for tripping instantaneously or with time delay
1.2.2 Measurements
 24 samples per cycle for current and voltage measurement
 Power metering (active and reactive power are calculated)
1.2.3 Configurable Functions

 User programmable logic
 Programmable tripping output matrix
 Programmable binary input
 Programmable binary output
 Programmable LED indicators
1.2.4 Miscellaneous Functions

 VT circuit supervision
 CT circuit supervision
 Frequency supervision
 Self diagnostic
 DC power supply supervision
 Event Recorder including 1024 disturbance records, 1024 binary events, 1024 supervision
events, 256 control logs and 1024 device logs.
 Disturbance recorder including 32 disturbance records with waveforms (The file format of
disturbance recorder is compatible with international COMTRADE file.), triggering by
protection element pickup, manual trigger on keypad and remote trigger through
PCS-Explorer
 Four kinds of clock synchronization methods
 Conventional
 PPS (RS-485): Pulse per second (PPS) via RS-485 differential level
 IRIG-B (RS-485): IRIG-B via RS-485 differential level
 PPM (DIN): Pulse per minute (PPM) via the optical coupler
 PPS (DIN): Pulse per second (PPS) via the optical coupler
 SAS
 SNTP (PTP): Unicast (point-to-point) SNTP mode via Ethernet network
 SNTP (BC): Broadcast SNTP mode via Ethernet network

Date: 2012-10-08
1 Introduction
 Message (IEC103): Clock messages through IEC103 protocol
 Advanced
 IEEE1588: Clock message via IEEE1588
 IRIG-B (Fiber): IRIG-B via optical-fibre interface
 PPS (Fiber): Pulse per second (PPS) via optical-fibre interface
 NoTimeSync
1.2.5 Communication
 Optional 2 RS-485 communication rear ports conform to IEC 60870-5-103 protocol
 1 RS-485 communication rear ports for clock synchronization
 Optional 2 or 4 Ethernet ports (depend on the chosen type of MON plug-in module) conform
to IEC 61850 protocol, DNP3.0 protocol or IEC 60870-5-103 protocol over TCP/IP
 Optional 2 Ethernet ports via optic fiber (ST interface) conform to IEC 61850 protocol, DNP3.0
protocol or IEC 60870-5-103 protocol over TCP/IP
1.2.6 User Interface
 Friendly HMI interface with LCD and 9-button keypad on the front panel.
 1 front multiplex RJ45 port for testing and setting
 1 RS-232 or RS-485 rear ports for printer
 Language switchover—English+ selected language
 Auxiliary software—PCS-Explorer
1.3 Features
 PCS-978 adopts intelligent design, and the amount of AC input module, binary input module
and binary output module are configurable, and terminals of those modules can be defined
according to actual requirement. Besides, protection elements not used can be hided and
new protection elements can be added not in standard configuration.
 The hardware comprises a32-bit microprocessor and two 32-bit digital signal processors
(DSP). Those processor can operate in parallel companied by fast A/D converter. The 32-bit
microprocessor performs logic calculation and DSP performs the protection calculation. High
performance hardware ensures real time calculation of all protection relays within a sampling
interval.
 High-performance hardware platform and modularized design, fault detector DSP＋protection

DSP. Fault detector DSP manages fault detector and protection DSP manages protection
calucation. Their data acquisition system is completely independent in electronic circuit. DC

Date: 2012-12-08
1 Introduction
power supply of output relay is controlled by the operation of fault detector element, which
prevents maloperation due to error from ADC or damage of any apparatus.
 On the premise of 24 samples per cycle, all data measurement, calculation and logic
discrimination could be done within one sampling period. The event recording and protection
logic calculation are completed simultaneously.
 Biased DPFC differential protection is regardless of load current and is sensitive to small
internal fault current within the transformer. Its performance against CT saturation is also
good.
 The tripping output contacts can be configured by tripping matrix and suitable to any mode of
tripping.
 Self-adaptive floating threshold which only reflects deviation of power frequency component
improves the protection sensitivity and stability under the condition of load fluctuation and
system disturbance.
 Advanced and reliable power swing blocking releasing feature which ensure impedance
protection operate correctly for internal fault during power swing and prevent impedance
protection from maloperation during power swing
 Multiple setting groups with password protection and setting value saved permanently before
modification
 Powerful PC tool software can fulfill protection function configuration, modify setting and
waveform analysis.

Date: 2012-10-08
1 Introduction

Date: 2012-12-08
2 Technical Data
2 Technical Data
Table of Contents
2 Technical Data .................................................................................... 2-a
2.1 Electrical Specifications ................................................................................. 2-1
2.1.1 AC Current Input................................................................................................................... 2-1
2.1.2 AC Voltage Input................................................................................................................... 2-1
2.1.3 Power Supply ....................................................................................................................... 2-1
2.1.4 Transducer Input .................................................................................................................. 2-2
2.1.5 Binary Input .......................................................................................................................... 2-2
2.1.6 Binary Output ....................................................................................................................... 2-2
2.2 Mechanical Specifications .............................................................................. 2-4

2.3 Ambient Temperature and Humidity Range .................................................. 2-4
2.4 Communication Port ....................................................................................... 2-5
2.4.1 EIA-485 Port ......................................................................................................................... 2-5
2.4.2 Ethernet Port ........................................................................................................................ 2-5
2.4.3 Optical Fibre Port ................................................................................................................. 2-5
2.4.4 Print Port .............................................................................................................................. 2-5
2.4.5 Clock Synchronization Port .................................................................................................. 2-6
2.5 Type Tests ........................................................................................................ 2-6

2.5.1 Environmental Tests ............................................................................................................. 2-6
2.5.2 Mechanical Tests .................................................................................................................. 2-6
2.5.3 Electrical Tests ..................................................................................................................... 2-6
2.5.4 Electromagnetic Compatibility .............................................................................................. 2-6
2.6 Certifications.................................................................................................... 2-7

2.7 Terminals .......................................................................................................... 2-7
2.8 Measurement Scope and Accuracy ............................................................... 2-8
2.9 Management Function .................................................................................... 2-8

Date: 2016-06-22
2 Technical Data
2.9.1 Clock Performance............................................................................................................... 2-8
2.9.2 Fault and Disturbance Recording ........................................................................................ 2-8
2.9.3 Binary Input Signal ............................................................................................................... 2-8
2.10 Protective Functions ..................................................................................... 2-8

2.10.1 Transformer Current Differential Protection ....................................................................... 2-9
2.10.2 Restricted Earth Fault Protection ..................................................................................... 2-10
2.10.3 Winding Differential Protection ......................................................................................... 2-10
2.10.4 Reactor Differential Protection ..........................................................................................2-11
2.10.5 Inter-turn Fault Protection .................................................................................................2-11
2.10.6 Overexcitation Protection ..................................................................................................2-11
2.10.7 Impedance Protection ...................................................................................................... 2-12
2.10.8 Phase Overcurrent protection .......................................................................................... 2-12
2.10.9 Earth Fault Protection ...................................................................................................... 2-13
2.10.10 Negative-sequence Overcurrent Protection................................................................... 2-14
2.10.11 Phase Overvoltage Protection........................................................................................ 2-15
2.10.12 Residual Overvoltage Protection ................................................................................... 2-15
2.10.13 Undervoltage Protection................................................................................................. 2-16
2.10.14 Overfrequency Protection .............................................................................................. 2-16
2.10.15 Underfrequency Protection ............................................................................................ 2-16
2.10.16 Thermal Overload Protection ......................................................................................... 2-17
2.10.17 Breaker Failure Initiation ................................................................................................ 2-17
2.10.18 Pole Disagreement Protection ....................................................................................... 2-17
2.10.19 Phase Overcurrent Alarm Element ................................................................................ 2-17
2.10.20 Residual Overvoltage Alarm Element ............................................................................ 2-18
2.10.21 Mechanical Protection .................................................................................................... 2-18
2.10.22 Temperature Protection .................................................................................................. 2-18

Date: 2016-06-22
2 Technical Data
2.1 Electrical Specifications
NOTICE!
“System phase sequence”, which can be set by PCS-Explorer, this setting informs the
device of the actual system phase sequence, either ABC or ACB. CT and VT inputs on
the device, labeled as A, B and C, must be connected to system phase A, B and C for
correct operation.
2.1.1 AC Current Input

Phase rotation ABC
Nominal frequency 50Hz, 60Hz
Rated Current (In) 1A 5A
Linear to 0.05In~40In
Thermal withstand
-continuously 4In
-for 10s 30In
-for 1s 100In
-for half a cycle 250In
Burden <0.15VA/phase @In <0.25VA/phase @In
Current input channel Maximum 36
2.1.2 AC Voltage Input

Phase rotation ABC
Nominal frequency 50Hz, 60Hz
Rated Voltage (Un) 100V~130V 200V (residual voltage input)
Linear to 1~170V 1-233V
Thermal withstand
-continuously 200V 220
-10s 260V 380
-1s 300V 420
Burden at rated <0.20VA/phase @Un <0.80VA/phase @Un
Voltage input channel Maximum 18 Maximum 9
2.1.3 Power Supply

Standard IEC 60255-11:2008
Rated Voltage 110Vdc/125Vdc/220Vdc/250Vdc 110Vac/220Vac
Variation 88~300Vdc 88~264Vac
Permissible AC ripple voltage ≤15% of the nominal auxiliary voltage
Burden
Quiescent condition <25W
Operation condition <35W

Date: 2016-06-22
2 Technical Data
2.1.4 Transducer Input

Standard IEC 60255-1: 2009
Input range 0-20mA 0-5V
Input resistance 235Ω 20kΩ
Accuracy 0.5% 0.5%
Transducer input channel Maximum 6
2.1.5 Binary Input

1. Settable pickup voltage and dropoff voltage
Rated voltage 110Vdc 220Vdc

Rated current drain 1.1mA 2.2mA
On value 85-132Vdc (default set) 170-264Vdc (default set)
Off value <66Vdc <132Vdc
Maximum permissible voltage 300Vdc
Withstand voltage 2000Vac, 2800Vdc (continuously )
Response time for logic input ≤1ms
Number Maximum 36
2. Fixed pickup voltage and dropoff voltage
Rated voltage 110Vdc 125Vdc 220Vdc 220Vdc

Rated current drain 1.1mA 1.25mA 2.2mA 2.85mA
On value 77-132Vdc 87.5-150Vdc 154-264Vdc 176-264Vdc
Off value <55Vdc <62.5Vdc <110Vdc <140Vdc
Maximum permissible voltage 300Vdc
Withstand voltage 2000Vac, 2800Vdc (continuously )
Response time for logic input ≤1ms
Number Maximum 36
2.1.6 Binary Output

1. Tripping/signaling contact
Output mode Potential free contact

Maximal system voltage 380Vac, 250Vdc
Continuous carry 8A
Pickup time (Typical Value) <5ms
Dropoff time <5ms
0.65A@48Vdc
0.35A@110Vdc
Breaking capacity (L/R=40ms) 0.30A@125Vdc
0.20A@220Vdc
0.15A@250Vdc
12A@3s
Short duration current
18A@1s

Date: 2015-01-13
2 Technical Data
24A@0.5s
40A@0.2s
Durability (Loaded contact) 10000 operations
Number Maximum 55
2. Heavy-capacity tripping contact

Maximal system voltage 250Vdc
Continuous carry 10A
Pickup time <1ms
Dropoff time <10ms
Breaking capacity (L/R=40ms) 10A
15A@3s
30A@1s
Number Maximum 12
3. Signaling contact
Output mode Potential free contact Potential free contact

Maximal system voltage 380Vac, 250Vdc 380Vac, 250Vdc
Continuous carry 8A 8A
Pickup time <10ms <10ms
Dropoff time <6ms <10ms
0.7A@48Vdc 1.00A@48Vdc
0.4A@110Vdc 0.50A@110Vdc
Breaking capacity (L/R=40ms) 0.3A@125Vdc 0.40A@125Vdc
0.2A@220Vdc 0.25A@220Vdc
0.15A@250Vdc 0.20A@250Vdc
12A@3s 12A@3s
15A@1s 15A@1s
20A@0.5s 20A@0.5s
30A@0.2s 30A@0.2s
Durability (Loaded contact) 10000 operations 10000 operations
Number Maximum 8 Maximum 3
4. Fast signaling contact

Maximal system voltage 380Vac, 250Vdc
Continuous carry 5A
Pickup time <1ms
Dropoff time <5ms
0.65A@48Vdc
Breaking capacity (L/R=0ms)
0.35A@110Vdc

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2 Technical Data
0.30A@125Vdc
0.20A@220Vdc
0.15A@250Vdc
8A@3s
12A@1s
16A@0.5s
30A@0.2s
Number Maximum 8
NOTICE!
Except heavy-capacity tripping contact, common tripping output contacts are not
connected to trip circuit breakers directly. They are connected to interposing relays or
lockout relays contacts which are connected to trip circuit breakers.
2.2 Mechanical Specifications
Mounting Way Flush mounted

Chassis color Silver grey
Weight per device Approx. 19kg
Chassis material Aluminum alloy
Location of terminal Rear panel of the device
Device structure Plug-in modular type @ rear side, integrated frontplate
Protection class
Front side IP51
Other sides IP30
Rear side, connection terminals IP20
2.3 Ambient Temperature and Humidity Range
Standard IEC 60225-1: 2009

Operating temperature -40°C to +70°C (Readability of display may be impaired below -20°C)
Transport and storage
-40°C to +70°C
temperature range
Permissible humidity 5%-95%, without condensation
Pollution degree Ⅱ
Altitude <3000m

Date: 2015-01-13
2 Technical Data
2.4 Communication Port
2.4.1 EIA-485 Port

Baud rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s
Protocol IEC 60870-5-103:1997
Maximal capacity 32
Max. transmission distance 500m
Safety level Isolation to ELV level
Twisted pair Screened twisted pair cable
2.4.2 Ethernet Port

Connector type RJ-45 ST, SC (Multi mode)
Transmission rate 100Mbits/s
Transmission standard 10Base-T/100Base-TX 100Base-FX
Max. transmission distance 100m 2km (1310nm)
Protocol IEC 60870-5-103:1997, DNP 3.0 or IEC 61850
2.4.3 Optical Fibre Port

2.4.3.1 For Station Level
Characteristic Glass optical fiber

Connector type ST
Fibre type Multi mode
Max. transmission distance 2km
Wave length 1310nm
Transmission power Min. -20.0dBm
Minimum receiving power Min. -30.0dBm
Margin Min +3.0dB
2.4.3.2 For Process Level
Characteristic Glass optical fiber

Connector type LC
Fibre type Multi mode
Max. transmission distance 2km
Wave length 1310nm
Transmission power Min. -20.0dBm
Minimum receiving power Min. -30.0dBm
Margin Min +3.0dB
2.4.4 Print Port

Type RS-232

Date: 2016-06-22
2 Technical Data
Baud Rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s

®
Printer type EPSON 300K printer
2.4.5 Clock Synchronization Port

Type RS-485
Max. transmission distance 500m
Maximal capacity 32
Timing standard PPS, IRIG-B
2.5 Type Tests
2.5.1 Environmental Tests

Dry cold test IEC60068-2-1:2007
Dry heat test IEC60068-2-2:2007
Damp heat test, cyclic IEC60068-2-30:2005
2.5.2 Mechanical Tests

Vibration IEC 60255-21-1:1988 ClassⅠ
Shock and bump IEC 60255-21-2:1988 ClassⅠ
2.5.3 Electrical Tests

Dielectric tests Test voltage 2kV, 50Hz, 1min
Impulse voltage tests Test voltage 5kV
Overvoltage category Ⅲ
Insulation resistance
Isolation resistance >100MΩ@500VDC
measurements
2.5.4 Electromagnetic Compatibility

IEC 60255-26:2013
1MHz burst disturbance test Common mode: class Ⅲ 2.5kV
Differential mode: class Ⅲ 1.0kV
IEC 60255-26:2013 class Ⅳ
Electrostatic discharge test For contact discharge: 8kV
For air discharge: 15kV
IEC 60255-26:2013 class Ⅲ
Frequency sweep
Radio frequency interference
Radiated amplitude-modulated
tests
10V/m (rms), f=80~1000MHz
Spot frequency

Date: 2015-01-13
2 Technical Data
Radiated amplitude-modulated
10V/m (rms), f=80MHz/160MHz/450MHz/900MHz
Radiated pulse-modulated
10V/m (rms), f=900MHz
IEC 60255-26:2013
Fast transient disturbance tests Power supply, I/O, Earth: class Ⅳ, 4kV, 2.5kHz, 5/50ns
Communication terminals: class Ⅳ, 2kV, 5kHz, 5/50ns
IEC 60255-26:2013
Power supply, AC input, I/O port: class Ⅳ, 1.2/50us
Surge immunity test
Common mode: 4kV
Differential mode: 2kV
IEC 60255-26:2013
Conducted RF Electromagnetic
Power supply, AC, I/O, Comm. Terminal: Class Ⅲ , 10Vrms, 150
Disturbance
kHz~80MHz
Power Frequency Magnetic IEC 61000-4-8:2001
Field Immunity class Ⅴ, 100A/m for 1min, 1000A/m for 3s
IEC 61000-4-9:2001
Pulse Magnetic Field Immunity
class Ⅴ, 6.4/16μs, 1000A/m for 3s
Damped oscillatory magnetic IEC 61000-4-10:2001
field immunity class Ⅴ, 100kHz & 1MHz–100A/m
Auxiliary power supply

IEC 60255-26:2013
performance
Up to 200ms for dips to 40% of rated voltage without reset
- Voltage dips
100ms for interruption without rebooting
-Voltage short interruptions
2.6 Certifications
 ISO9001:2008
 ISO14001:2004
 OHSAS18001:2007
 ISO10012:2003
 CMMI L5
 EMC: 2014/30/EU, EN60255-26:2013
 Products safety (LVD): 2014/35/EU, EN60255-27:2014
2.7 Terminals
Connection Type Wire Size

2
AC current Screw terminals, 2.5mm lead

Date: 2016-06-22
2 Technical Data
2
AC voltage Screw terminals, 1.5mm lead
Power supply Screw terminals, 1.0mm2~2.5mm2 lead
2 2
Contact I/O Screw terminals, 1.0mm ~2.5mm lead
Grounding (Earthing) Connection BVR type, 2.5mm²~6.0mm2 lead
2.8 Measurement Scope and Accuracy
Item Range Accuracy

Phase range 0°~ 360° ≤±3°
Frequency fn±3 Hz ≤ 0.02Hz
Currents from protection measurement current transformers
≤ 2.0% of rating (0.05~1.00In)
Current 0.05~5.00In
≤ 2.0% of applied quantities (1.00~5.00In)
≤ 1.0% of rating (0.05~1.00Un)
Voltage 0.05~1.50Un
≤ 1.0% of applied quantities (1.00~1.50Un)
0.05~1.50Un ≤ 3.0% of rating (0.05~1.00In, 0.05~1.00Un)
Active power (W)
0.05~5.00In ≤ 3.0% of applied quantities (1.00~5.00In, 1.00~1.50Un)
0.05~1.50Un ≤ 3.0% of rating (0.05~1.00In, 0.05~1.00Un)
Reactive power (VAr)
0.05~1.50Un ≤ 3.0% of rating (0.05~1.00In, 0.05~1.00Un)
Apparent power (VA)
2.9 Management Function
2.9.1 Clock Performance
Real time clock accuracy ≤ 3s/day

Accuracy of GPS synchronization ≤ 1ms
External time synchronization IRIG-B (200-98), PPS, IEEE1588 or SNTP protocol
2.9.2 Fault and Disturbance Recording

Maximum duration 10000 sampled points (24 sampled points per cycle)
Recording position 10 cycles before pickup of trigger element
2.9.3 Binary Input Signal

Resolution of binary input signal ≤ 1ms
Binary input mode Potential-free contact
Resolution of SOE ≤ 2ms
2.10 Protective Functions
There are some symbols mentioned in the following sections and the meaning of them is given

Date: 2015-01-13
2 Technical Data
here.
Un——VT rated secondary voltage
In——CT rated secondary current
p.u.——per unit value of settings and currents for current differential protection
Id——differential current
3I0d——residual differential current
Iwd——winding differential current
ΔId——DPFC differential current
U*/f*——the overexcitation multiple
2.10.1 Transformer Current Differential Protection

2.10.1.1 Biased Differential Protection
Current setting of knee point 1 0.1~1p.u.
Current setting of knee point 2 4~8p.u.
Pickup up setting 0.05~5p.u.
Slope 1 setting 0.1~0.9
2nd harmonic setting for inrush current 0.05~0.3
3rd harmonic setting for inrush current 0.05~0.3

rd th
3 or 5 harmonic setting for overexcitation 0.05~0.3
nd rd
Tolerance of 2 and 3 harmonic settings 0.01
th
Tolerance of 5 harmonic settings 0.02
Tolerance of operating current ≤5% of operating current or 0.02p.u., whichever is greater
Drop-off to pickup ratio ≥95%
50Hz: ≤ 30ms (Id>2 times current setting)

Operating time (without blocking criteria)
60Hz: ≤ 25ms (Id>2 times current setting)
Drop-off time ≤30ms
2.10.1.2 Instantaneous Differential Protection
Current setting 0.05~20p.u.
Tolerance of current setting ≤2.5% of setting or 0.02p.u., whichever is greater
50Hz: ≤ 20ms (Id>1.5 times current setting)

Operating time
60Hz: ≤ 20ms (Id>1.5 times current setting)

Date: 2016-06-22
2 Technical Data
2.10.1.3 DPFC Current Differential Protection
Pickup current value 0.2p.u.
Tolerance of operating current ≤10%
Fixed value of slope 1 0.6
Fixed value of slope 2 0.75
50Hz: ≤30ms (ΔId >2x0.2p.u.)

Operating time
60Hz: ≤25ms (ΔId >2x0.2p.u.)
2.10.2 Restricted Earth Fault Protection
Current setting of knee point 0.1~4In (A)
Pickup up setting 0.05~5In (A)
Time delay setting 0~20 (s)
Restraint slope setting 0.20~0.75
Tolerance of operating current ≤5% of operating current or 0.02×In, whichever is greater
Operating time (without time delay, without 50Hz: ≤30ms (3I0d>2 times current setting)
blocking criterion) 60Hz: ≤25ms (3I0d>2 times current setting)
Tolerance of time setting ≤1% of setting +30ms (3I0d>2 times current setting)
2.10.3 Winding Differential Protection
Current setting of knee point 0.1~4In (A)
Pickup up setting 0.05~5In (A)
Restraint slope setting 0.20~0.75
Tolerance of operating current ≤5% or 0.02×In, whichever is greater
50Hz: ≤30ms (Iwd>2 times current setting)

Operating time (without blocking criterion)
60Hz: ≤25ms (Iwd>2 times current setting)
Tolerance of time setting ≤1% of setting +30ms (Iwd>2 times current setting)

Date: 2015-01-13
2 Technical Data
2.10.4 Reactor Differential Protection

2.10.4.1 Biased Differential Protection
Pickup up setting 0.05~5p.u.
Slope setting 0.1~0.9
Tolerance of operating current ≤5% of operating current or 0.02p.u., whichever is greater
50Hz: ≤30ms( Id>2 times current setting)

Operating time (without blocking criterion)
60Hz: ≤25ms( Id>2 times current setting)
2.10.4.2 Instantaneous Differential Protection
Current setting 0.05~20p.u.
Tolerance of current setting ≤2.5% of setting or 0.02p.u., whichever is greater
50Hz: ≤ 20ms( Id>1.5 times current setting)

Operating time
60Hz: ≤ 20ms( Id>1.5 times current setting)
2.10.5 Inter-turn Fault Protection
Operating time without delay ≤60ms
2.10.6 Overexcitation Protection
Definite time U*/f* setting 1.0~1.7 p.u.
Definite time delay setting 0.1 s~9999 (s)
Inverse time U*/f* setting 1.0~1.7 p.u.
Inverse time delay setting 0.1 s~9999 (s)
Tolerance of U*/f* setting ≤2.5% of setting or 0.01 whichever is greater
Cooling time setting 0.1~9999 (s)
Drop-off to pickup ratio of definite-time

≥97%
overexcitation protection
Tolerance of operating time of definite-time

≤1% of setting +100ms (at 1.5 times U*/f* setting)
overexciation protection
Tolerance of operating time of inverse-time

≤2.5% of operating time or 30ms, whichever is greater
Drop-off time of definite-time overexcitation

≤30ms
protection

Date: 2016-06-22
2 Technical Data
2.10.7 Impedance Protection
Relay characeristic angle 1~89 (deg)
Impedance setting 0.05~200 (Ω)
Time setting 0.05~20 (s)
Tolerance of impedance setting ≤2.5%xSetting or 0.5Ω/In, whichever is greater
Tolerance of time setting ≤1%xsetting + 40ms (at 1.5 times impedance setting)
Current setting of fault detector for PSBR 0.04~150 (A)
Tolerance of current setting ≤2.5% of setting or 0.02In, whichever is greater
2.10.8 Phase Overcurrent protection

2.10.8.1 Definte-time Characteristic
Current setting 0.04In~30In (A)
50Hz: ≤25 ms (at 2 times current setting)

Operating time
Time delay setting 0.00~3600 (s)
Tolerance of time setting ≤1% of setting +30ms (at 2 times current setting)
2.10.8.2 Inverse-time Characteristic
Pickup current setting 0.04In~30In (A)
Multiple of the maximum operating current to

10~40
pickup setting
Time multiplier setting 0.05~3.2
Minimum delay setting 0.0~20 (s)
Constant K 0.0~120
Constant C 0.0~20
Exponent alpha 0.02~5
≤2.5% of operating time or 30ms, whichever is greater (for

Operating time
current between 1.2 and 20 multiples of pickup)

Date: 2015-01-13
2 Technical Data
2.10.8.3 Control and Blocking Element
Phase-to-phase undervoltage setting 2~200 (V)
Negative-sequence voltage setting 2~200 (V)
Tolerance of voltage setting ≤2.5% of setting or 0.01Un, whichever is greater
Drop-off to pickup ratio of voltage element ≥95%
Relay characteristic angle 0~360 (deg)
Tolerance of relay characteristic angle ≤3deg
Minimum polarizing voltage 2% of VT rated voltage

nd
2 harmonic for inrush 0.05~1.0
Current setting of releasing inrush blocking 0.04~30In (A)
Tolerance of current setting of releasing inrush

≤2.5% of setting or 0.02In, whichever is greater
blocking
2.10.9 Earth Fault Protection

50Hz: ≤25ms (at 2 times current setting)

Operating time
Multiple of the maximum operating current to the

10~40
pickup setting
Constant K 0.0~120
Constant C 0.0~20

Operating time
residual current between 1.2 and 20 multiples of pickup)

Date: 2016-06-22
2 Technical Data
2.10.9.3 Control and Blocking Element
Relay characteristic angle 0~360 (deg)
Tolerance of relay characteristic angle ≤3deg
Minimum polarizing voltage 2% of VT rated voltage

nd
2 harmonic for inrush 0.05~1.0
Current setting of releasing inrush blocking 0.04~150 (A)
Tolerance of current setting of releasing inrush

≤2.5% of setting or 0.02In, whichever is greater
blocking
2.10.10 Negative-sequence Overcurrent Protection


Operating time

10~40
pickup setting
Constant K 0.0~120
Constant C 0.0~20

Operating time of IDMT NegOC negative-sequence current between 1.2 and 20 multiples of
pickup)

Date: 2015-01-13
2 Technical Data
2.10.11 Phase Overvoltage Protection

Voltage setting 2~200 (V)
Tolerance of voltage setting ≤2.5% of setting or 0.1V, whichever is greater
50Hz: ≤35ms (at 1.2 times voltage setting)

Operating time
Tolerance of time setting ≤1% of setting +30ms (at 1.2 times voltage setting)
Pickup voltage setting 2~200 (V)
Multiple of the maximum operating voltage to the

10~40
pickup setting
Constant K 0.0~120
Constant C 0.0~20

Operating time
voltage between 1.2 and 2 multiples of pickup)
2.10.12 Residual Overvoltage Protection


Operating time
Time delay setting 0s~3600 (s)

Date: 2016-06-22
2 Technical Data
Pickup voltage setting 2~200 (V)

10~40
pickup setting
Constant K 0.0~120
Constant C 0.0~20

Operating time
residual voltage between 1.2 and 2 multiples of pickup)
2.10.13 Undervoltage Protection
Lowest voltage threshold of voltage recovery 10~100 (V)
Drop-off to pickup ratio ≤102%
50Hz ≤20ms (at 0.8 times voltage setting)

Operating time
60Hz:≤20ms (at 0.8 times voltage setting)
Time setting of fault recovery 0~100 (s)
du/dt setting 0~100 (V/s)
2.10.14 Overfrequency Protection

Frequency setting 50~65 (Hz)
Tolerance of frequency setting ≤ 0.02Hz
Time setting 0~100 (s)
Tolerance of time setting ≤1%Setting+100ms (at 1.2 times frequency setting)
2.10.15 Underfrequency Protection

Frequency setting 45~60 (Hz)
Tolerance of frequency setting ≤ 0.02Hz

Date: 2015-01-13
2 Technical Data
Time setting of fault recovery ≤1%Setting+100ms (at 0.8 times frequency setting)
df/dt setting 0.2~20 (Hz/s)
Tolerance of df/dt setting ≤ 0.02Hz/s
2.10.16 Thermal Overload Protection
Base current setting range 0.04In~30In (A)
Transformer thermal time constant 0~100 (s)
Thermal overload coefficient for trip 1~3
Thermal overload coefficient for alarm 1~3

Operating time
current between 1.2 and 20 multiples of pickup)
2.10.17 Breaker Failure Initiation
Range of phase current setting 0.04In~30In (A)
Range of residual current setting 0.04In~30In (A)
Range of negative sequence current setting 0.04In~30In (A)
Current setting tolerance ≤2.5% of setting or 0.02×In, whichever is greater
Time setting range 0~20 (s)
Time setting tolerance ≤1% of setting+30ms (at 2 times current setting)
2.10.18 Pole Disagreement Protection
Range of residual current setting 0.04In~30In (A)
Range of negative sequence current setting 0.04In~30In (A)
Current setting tolerance ≤2.5% of setting or 0.02×In, whichever is greater
Range of time setting 0~20 (s)
Time setting tolerance ≤1% of setting+30ms (at 2 times current setting)
2.10.19 Phase Overcurrent Alarm Element

Operating time without time delay

Date: 2016-06-22
2 Technical Data
2.10.20 Residual Overvoltage Alarm Element
Time delay setting 0~3600 (s)
Tolerance of time setting ≤1% of setting+30ms (at 1.2 times voltage setting)
2.10.21 Mechanical Protection
Delay pickup up time setting 0~3600 (s)
Pulse width setting 0~10 (s)
Time setting tolerance ≤1% of setting+30ms
2.10.22 Temperature Protection
Temperature setting 0~200 (°C)
Tolerance of temperature setting ≤0.5%x([26.Tmax]-[26.Tmin])
Drop-off to pickup ratio ≥99%x([26.T_Trp]-[26.Tmin])
Tolerance of time setting ≤1% of setting+40ms (at 1.5 times temperature setting)

Date: 2015-01-13
3 Operation Theory
3 Operation Theory
Table of Contents
3 Operation Theory............................................................................... 3-a
3.1 Overview .......................................................................................................... 3-1
3.2 Three-phase Current Element (Curr3P) ......................................................... 3-1
3.2.1 Application ............................................................................................................................ 3-1
3.2.2 Function Description ............................................................................................................ 3-1
3.2.3 Function Block Diagram ....................................................................................................... 3-2
3.2.4 I/O Signals ............................................................................................................................ 3-2
3.2.5 Logic ..................................................................................................................................... 3-3
3.2.6 Settings................................................................................................................................. 3-3
3.3 Three-phase Voltage Element (Volt3P) .......................................................... 3-3

3.3.1 Application ............................................................................................................................ 3-3
3.3.4 I/O Signals ............................................................................................................................ 3-4
3.3.5 Logic ..................................................................................................................................... 3-5
3.3.6 Settings................................................................................................................................. 3-5
3.4 Residual Current Element (Curr1P) ............................................................... 3-5

3.4.1 Application ............................................................................................................................ 3-5
3.4.4 I/O Signals ............................................................................................................................ 3-6
3.4.5 Settings................................................................................................................................. 3-6
3.5 Residual Voltage Element (Volt1P) ................................................................. 3-6

3.5.1 Application ............................................................................................................................ 3-6
3.5.4 I/O Signals ............................................................................................................................ 3-7
3.5.5 Settings................................................................................................................................. 3-7
3.6 Transformer Current Differential Protection (87T) ........................................ 3-7

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3 Operation Theory
3.6.1 Application ............................................................................................................................ 3-7

3.6.3 Function Block Diagram ..................................................................................................... 3-30
3.6.4 I/O Signals .......................................................................................................................... 3-30
3.6.5 Logic ................................................................................................................................... 3-31
3.6.6 Settings............................................................................................................................... 3-34
3.7 Reactor Current Differential Protection (87R) ............................................. 3-35

3.7.1 Application .......................................................................................................................... 3-35
3.7.2 Function Description .......................................................................................................... 3-35
3.7.4 I/O Signals .......................................................................................................................... 3-48
3.7.5 Logic ................................................................................................................................... 3-49
3.7.6 Settings............................................................................................................................... 3-52
3.8 Restricted Earth Fault Protection (64REF) .................................................. 3-52

3.8.1 Application .......................................................................................................................... 3-52
3.8.4 I/O Signals .......................................................................................................................... 3-59
3.8.5 Logic ................................................................................................................................... 3-60
3.8.6 Settings............................................................................................................................... 3-61
3.9 Winding Differential Protection (87W) ......................................................... 3-61

3.9.1 Application .......................................................................................................................... 3-61
3.9.4 I/O Signals .......................................................................................................................... 3-66
3.9.5 Logic ................................................................................................................................... 3-68
3.9.6 Settings............................................................................................................................... 3-69
3.10 Inter-turn Fault Protection (21IT) ................................................................ 3-69
3.10.1 Application ........................................................................................................................ 3-69
3.10.2 Function Description ........................................................................................................ 3-69
3.10.3 I/O Signals ........................................................................................................................ 3-74
3.10.4 Logic ................................................................................................................................. 3-74
3.10.5 Settings ............................................................................................................................ 3-75
3.11 Overexcitation Protection (24) .................................................................... 3-75
3.11.1 Application ........................................................................................................................ 3-75

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3 Operation Theory
3.11.2 Function Description ......................................................................................................... 3-75

3.11.3 Function Block Diagram ................................................................................................... 3-77
3.11.4 I/O Signals ........................................................................................................................ 3-77
3.11.5 Logic ................................................................................................................................. 3-78
3.11.6 Settings ............................................................................................................................. 3-79
3.12 Frequency Protection (81) .......................................................................... 3-81

3.12.1 Application ........................................................................................................................ 3-81
3.12.4 I/O Signals ........................................................................................................................ 3-84
3.12.5 Logic ................................................................................................................................. 3-86
3.12.6 Settings ............................................................................................................................ 3-87
3.13 Impedance Protection (21) .......................................................................... 3-88

3.13.1 Application ........................................................................................................................ 3-88
3.13.4 I/O Signals ........................................................................................................................ 3-93
3.13.5 Logic ................................................................................................................................. 3-94
3.13.6 Settings ............................................................................................................................ 3-95
3.14 Phase Overcurrent Protection (50/51P) ..................................................... 3-97

3.14.1 Application ........................................................................................................................ 3-97
3.14.3 Function Block Diagram ................................................................................................. 3-101
3.14.4 I/O Signals ...................................................................................................................... 3-101
3.14.5 Logic ............................................................................................................................... 3-102
3.14.6 Settings .......................................................................................................................... 3-104
3.15 Earth Fault Protection (50/51G) ................................................................ 3-107

3.15.1 Application ...................................................................................................................... 3-107
3.15.2 Function Description ...................................................................................................... 3-107
3.15.3 Function Block Diagram .................................................................................................. 3-111
3.15.4 I/O Signals ....................................................................................................................... 3-111
3.15.5 Logic ................................................................................................................................3-112
3.15.6 Settings ...........................................................................................................................3-113
3.16 Negative-Sequence Overcurrent Protection (50/51Q) ............................. 3-116
3.16.1 Application .......................................................................................................................3-116
PCS-978 Transformer Relay 3-c

Date: 2016-06-22
3 Operation Theory
3.16.2 Function Description .......................................................................................................3-116

3.16.3 Function Block Diagram ..................................................................................................3-117
3.16.4 I/O Signals .......................................................................................................................3-117
3.16.5 Logic ................................................................................................................................3-118
3.16.6 Settings ...........................................................................................................................3-119
3.17 Phase Overvoltage Protection (59P) ........................................................ 3-120

3.17.1 Application ...................................................................................................................... 3-120
3.17.4 I/O Signals ...................................................................................................................... 3-123
3.17.5 Logic ............................................................................................................................... 3-124
3.17.6 Settings .......................................................................................................................... 3-124
3.18 Residual Overvoltage Protection (59G) ................................................... 3-126

3.18.1 Application ...................................................................................................................... 3-126
3.18.4 I/O Signals ...................................................................................................................... 3-128
3.18.5 Logic ............................................................................................................................... 3-129
3.18.6 Settings .......................................................................................................................... 3-129
3.19 Undervoltage Protection (27P) ................................................................. 3-131

3.19.1 Application ...................................................................................................................... 3-131
3.19.4 I/O Signals ...................................................................................................................... 3-132
3.19.5 Logic ............................................................................................................................... 3-133
3.19.6 Settings .......................................................................................................................... 3-134
3.20 Thermal Overload Protection (49) ............................................................ 3-135

3.20.1 Application ...................................................................................................................... 3-135
3.20.4 I/O Signals ...................................................................................................................... 3-138
3.20.5 Logic ............................................................................................................................... 3-139
3.20.6 Settings .......................................................................................................................... 3-139
3.21 Breaker Failure Protection (50BF) ............................................................ 3-140
3.21.1 Application ...................................................................................................................... 3-140
3-d PCS-978 Transformer Relay

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3 Operation Theory

3.21.4 I/O Signals ...................................................................................................................... 3-141
3.21.5 Logic ............................................................................................................................... 3-143
3.21.6 Settings .......................................................................................................................... 3-143
3.22 Pole Disagreement Protection (62PD) ..................................................... 3-144

3.22.1 Application ...................................................................................................................... 3-144
3.22.4 I/O Signals ...................................................................................................................... 3-145
3.22.5 Logic ............................................................................................................................... 3-146
3.22.6 Settings .......................................................................................................................... 3-146
3.23 Phase Overcurrent Alarm (51PAlm) ......................................................... 3-147

3.23.1 Application ...................................................................................................................... 3-147
3.23.4 I/O Signals ...................................................................................................................... 3-148
3.23.5 Logic ............................................................................................................................... 3-148
3.23.6 Settings .......................................................................................................................... 3-149
3.24 Residual Overvoltage Alarm (59GAlm) .................................................... 3-149

3.24.1 Application ...................................................................................................................... 3-149
3.24.4 I/O Signals ...................................................................................................................... 3-151
3.24.5 Logic ............................................................................................................................... 3-151
3.24.6 Settings .......................................................................................................................... 3-152
3.25 Mechanical Protection (MR)...................................................................... 3-152

3.25.1 Application ...................................................................................................................... 3-152
3.25.4 I/O Signals ...................................................................................................................... 3-154
3.25.5 Logic ............................................................................................................................... 3-154
3.25.6 Settings .......................................................................................................................... 3-155
3.26 Temperature Protection (26) ..................................................................... 3-156
3.26.1 Application ...................................................................................................................... 3-156
PCS-978 Transformer Relay 3-e

Date: 2016-06-22
3 Operation Theory

3.26.4 I/O Signals ...................................................................................................................... 3-158
3.26.5 Logic ............................................................................................................................... 3-158
3.26.6 Settings .......................................................................................................................... 3-159
3.27 Output Map (OutMap) ................................................................................ 3-159

3.27.1 Application ...................................................................................................................... 3-159
3.27.3 I/O Signals ...................................................................................................................... 3-161
3.27.4 Settings .......................................................................................................................... 3-161
3.28 Intermediate Variable Element.................................................................. 3-162

3.28.2 I/O Signals ...................................................................................................................... 3-162
List of Figures
Figure 3.2-1 Logic diagram of current pre-processing ........................................................... 3-3
Figure 3.3-1 Logic diagram of voltage pre-processing ........................................................... 3-5
Figure 3.6-1 Current compensation calculation process...................................................... 3-13
Figure 3.6-2 Operation characteristic of sensitive biased differential element ................. 3-16
Figure 3.6-3 Operation characteristic of conventional biased differential element ........... 3-17
Figure 3.6-4 Operation characteristic of biased/instantaneous differential elements ...... 3-18
Figure 3.6-5 Operation characteristic of DPFC biased differential protection ................... 3-21
Figure 3.6-6 Schematic of waveform symmetry principle .................................................... 3-23
Figure 3.6-7 Logic of inrush current blocking current differential protection.................... 3-26
Figure 3.6-8 Logic diagram of transformer differential protection start ............................. 3-31
Figure 3.6-9 Logic diagram of instantaneous differential element ...................................... 3-31
Figure 3.6-10 Logic diagram of biased differential element ................................................. 3-32
Figure 3.6-11 Logic diagram of DPFC biased differential element ...................................... 3-33
Figure 3.6-12 Logic diagram of CT circuit failure alarm........................................................ 3-33
Figure 3.7-1 Current compensation calculation process...................................................... 3-39
Figure 3.7-2 Operation characteristic of sensitive biased differential element ................. 3-41
Figure 3.7-3 Operation characteristic of conventional biased differential element ........... 3-42
3-f PCS-978 Transformer Relay

Date: 2016-06-22
3 Operation Theory
Figure 3.7-4 Operation characteristic of biased and Instantaneous differential element . 3-43
Figure 3.7-5 Operation characteristic of DPFC biased differential element ....................... 3-46
Figure 3.7-6 Operation characteristic of zero-sequence differential element .................... 3-47
Figure 3.7-6 Logic diagram of reactor differential protection start ..................................... 3-49
Figure 3.7-7 Logic diagram of instantaneous differential element ...................................... 3-50
Figure 3.7-8 Logic diagram of biased differential element ................................................... 3-50
Figure 3.7-9 Logic diagram of DPFC biased differential element ........................................ 3-50
Figure 3.7-11 Logic diagram of zero-sequence differential element ................................... 3-51
Figure 3.8-1 Application for two-windings transformer with one CB at one side .............. 3-53
Figure 3.8-2 Application for two-windings transformer with two CBs at one side ............ 3-54
Figure 3.8-3 Application for auto-transformer ....................................................................... 3-54
Figure 3.8-4 REF principle ........................................................................................................ 3-56
Figure 3.8-5 Operation characteristic of REF ......................................................................... 3-58
Figure 3.8-6 Logic diagram of restricted earth fault protection ........................................... 3-60
Figure 3.9-1 Winding differential protection applied to auto-transformer .......................... 3-62
Figure 3.9-2 Winding differential protection applied to stub differential protection ......... 3-62
Figure 3.9-3 Operating characteristic of winding differential protection ............................ 3-65
Figure 3.9-4 Logic diagram of winding differential protection ............................................. 3-68
Figure 3.10-1 Wiring diagram of shunt reactors in power system....................................... 3-70
Figure 3.10-2 Equivalent zero-sequence network for F1 ...................................................... 3-71
Figure 3.10-3 Vector relation for F1 ......................................................................................... 3-71
Figure 3.10-4 Equivalent zero-sequence network for F2 ...................................................... 3-72
Figure 3.10-5 Vector relation for F2 ......................................................................................... 3-72
Figure 3.10-6 Logic diagram of inter-turn fault protection ................................................... 3-74
Figure 3.11-1 Inverse-time characteristic of overexcitation protection .............................. 3-76
Figure 3.11-2 Logic diagram of definite-time overexcitation protection ............................. 3-78
Figure 3.11-3 Logic diagram of inverse-time overexcitation protection ............................. 3-79
Figure 3.12-1 Logic diagram of underfrequency protection ................................................. 3-86
Figure 3.12-2 Logic diagram of overfrequency protection ................................................... 3-87
Figure 3.13-1 Operating characteristic of phase-to-phase impedance element ................ 3-90
PCS-978 Transformer Relay 3-g

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3 Operation Theory
Figure 3.13-2 Operating characteristic of phase-to-ground impedance element .............. 3-90
Figure 3.13-3 Logic diagram of impedance protection (n=1, 2) ........................................... 3-94
Figure 3.14-1 VT and CT connection of direction element ................................................. 3-100
Figure 3.14-2 Directional characteristic ................................................................................ 3-100
Figure 3.14-3 Logic diagram of voltage control element (n=1, 2, 3, 4) .............................. 3-102
Figure 3.14-4 Logic diagram of direction element (n=1, 2, 3, 4) ......................................... 3-103
Figure 3.14-5 Logic Diagram of phase overcurrent protection (n=1, 2, 3) ..................... 3-103
Figure 3.14-6 Logic Diagram of phase overcurrent protection (stage 4) ....................... 3-104
Figure 3.15-1 VT and CT connection of direction element ................................................. 3-109
Figure 3.15-2 Directional characteristic ................................................................................ 3-110
Figure 3.15-3 Logic diagram of direction element (n=1, 2, 3, 4) ......................................... 3-112
Figure 3.15-4 Logic diagram of earth fault protection (n=1, 2, 3) ....................................... 3-112
Figure 3.15-5 Logic diagram of earth fault protection (stage 4) ......................................... 3-113
Figure 3.16-1 Logic diagram of negative-sequence overcurrent protection .................... 3-118
Figure 3.17-1 Logic diagram of residual overvoltage protection ....................................... 3-124
Figure 3.18-1 Logic diagram of residual overvoltage protection ....................................... 3-129
Figure 3.19-1 Logic diagram of undervoltage protection ................................................... 3-133
Figure 3.20-1 Characteristic curve of thermal overload protection ................................... 3-136
Figure 3.20-2 Logic diagram of thermal overload protection (method 1) ......................... 3-139
Figure 3.21-1 Logic diagram of breaker failure protection ................................................. 3-143
Figure 3.22-1 Logical diagram of pole disagreement protection ....................................... 3-146
Figure 3.23-1 Logic diagram of phase overcurrent alarm (n=1, 2) ..................................... 3-148
Figure 3.24-1 Logic diagram of residual overvoltage alarm ............................................... 3-151
Figure 3.25-1 Logic diagram of mechanical protection ...................................................... 3-155
Figure 3.26-1 Logic diagram of temperature protection ..................................................... 3-158
Figure 3.28-1 An example of programmable logic............................................................... 3-162
List of Tables
Table 3.2-1 I/O signals of three-phase currents element ........................................................ 3-2
Table 3.2-2 Settings of three-phase currents element ............................................................ 3-3
3-h PCS-978 Transformer Relay

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3 Operation Theory
Table 3.3-1 I/O signals of three-phase voltages element ........................................................ 3-4
Table 3.3-2 Settings of three-phase voltages element ............................................................ 3-5
Table 3.4-1 I/O signals of residual current element ................................................................. 3-6
Table 3.4-2 Settings of residual current element ..................................................................... 3-6
Table 3.5-1 I/O signals of residual voltage element ................................................................. 3-7
Table 3.5-2 Settings of residual voltage element ..................................................................... 3-7
Table 3.6-1 Matrix of phase compensation............................................................................. 3-11
Table 3.6-2 Comparison of different blocking modes ........................................................... 3-24
Table 3.6-3 I/O signals of transformer differential protection .............................................. 3-30
Table 3.6-4 Settings of transformer differential protection .................................................. 3-34
Table 3.7-1 I/O signals of reactor differential protection ...................................................... 3-48
Table 3.7-2 Settings of reactor current differential protection ............................................. 3-52
Table 3.8-1 I/O signals of restricted earth-fault protection ................................................... 3-59
Table 3.8-2 Settings of restricted earth fault protection ....................................................... 3-61
Table 3.9-1 I/O signals of winding differential protection ..................................................... 3-66
Table 3.9-2 Settings of winding differential protection ......................................................... 3-69
Table 3.10-1 I/O signals of inter-turn protection .................................................................... 3-74
Table 3.10-2 Settings of inter-turn fault protection ............................................................... 3-75
Table 3.11-1 I/O signals of overexcitation protection............................................................ 3-77
Table 3.11-2 Settings of overexcitation protection ................................................................ 3-79
Table 3.12-1 I/O signals of frequency protection ................................................................... 3-84
Table 3.12-2 Settings of frequency protection ....................................................................... 3-87
Table 3.13-1 I/O signals of impedance protection ................................................................. 3-93
Table 3.13-2 Settings of impedance protection ..................................................................... 3-95
Table 3.14-1 Inverse-time curve parameters .......................................................................... 3-98
Table 3.14-2 I/O signals of phase overcurrent protection................................................... 3-101
Table 3.14-3 Settings of phase overcurrent protection....................................................... 3-104
Table 3.15-1 Inverse-time curve parameters ........................................................................ 3-108
Table 3.15-2 I/O signals of earth fault protection ................................................................. 3-111
Table 3.15-3 Settings of earth fault protection ..................................................................... 3-113
PCS-978 Transformer Relay 3-i

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3 Operation Theory
Table 3.16-2 I/O signals of negative-sequence overcurrent protection ............................ 3-117
Table 3.16-3 Settings of negative-sequence overcurrent protection ................................ 3-119
Table 3.17-2 I/O signals of phase overvoltage protection .................................................. 3-123
Table 3.17-3 Settings of residual overvoltage protection ................................................... 3-124
Table 3.18-2 I/O signals of residual overvoltage protection ............................................... 3-128
Table 3.18-3 Settings of residual overvoltage protection ................................................... 3-129
Table 3.19-1 I/O signals of undervoltage protection ........................................................... 3-132
Table 3.19-2 Settings of undervoltage protection................................................................ 3-134
Table 3.20-1 I/O signals of thermal overload protection ..................................................... 3-138
Table 3.20-2 Settings of thermal overload protection ......................................................... 3-139
Table 3.21-1 I/O signals of breaker failure protection ......................................................... 3-141
Table 3.21-2 Settings of breaker failure protection ............................................................. 3-143
Table 3.22-1 I/O signals of pole disagreement protection .................................................. 3-145
Table 3.22-2 Settings of pole disagreement protection ...................................................... 3-146
Table 3.23-1 I/O signals of phase overcurrent alarm ........................................................... 3-148
Table 3.23-2 Settings of phase overcurrent alarm ............................................................... 3-149
Table 3.24-2 I/O signals of residual overvoltage alarm ....................................................... 3-151
Table 3.24-3 Settings of residual overvoltage alarm ........................................................... 3-152
Table 3.25-1 I/O signals of mechanical protection .............................................................. 3-154
Table 3.25-2 Settings of mechanical protection................................................................... 3-155
Table 3.26-1 I/O signals of temperature protection ............................................................. 3-158
Table 3.26-2 Settings of temperature protection ................................................................. 3-159
Table 3.27-1 I/O signals of programmable trip output......................................................... 3-161
Table 3.27-2 Settings of programmable trip output ............................................................. 3-161
Table 3.28-1 Signals of intermediate variable element ....................................................... 3-162
3-j PCS-978 Transformer Relay

Date: 2016-06-22
3 Operation Theory
3.1 Overview
The device consists of current differential protection, restricted earth fault protection,
overexcitation protection, winding differential protection, phase overcurrent protection, earth fault
protection, negative-sequence overcurrent protection, phase overcurrent alarm, phase
overvoltage protection, undervoltage protection, residual overvoltage protection, residual
overvoltage alarm, thermal overload protection, pole discrepancy protection, breaker failure
protection, impedance protection, inter-turn protection, mechanical protection and temperature
protection.
The device equips 2 DSP plug-in modules (i.e. protection DSP plug-in module and fault detector
DSP plug-in module). Protection DSP plug-in module is responsible for protection logic calculation,
and fault detector DSP plug-in module is responsible for fault detector. Fault detector element
operates to provide positive supply to output relays. The output relays can only operate when both
a protection element and the corresponding fault detector element operate simultaneously. An
alarm message will be issued with blocking output if a protection element operates while the
corresponding fault detector element does not operate.
3.2 Three-phase Current Element (Curr3P)
3.2.1 Application
Three-phase current element is responsible for pre-processing three phase currents and
calculates sequence components, amplitudes and phases of three phase currents, etc. All
calculated information of three-phase current element is used by the protection logic calculation.
NOTICE!
The symbol “x” represents some side of transformer defined by user through
PCS-Explorer software, which may be “HVS”, “MVS”, “LVS”, “CWS” by default.
3.2.2 Function Description

Three-phase current element has following functions:
1. Pre-process three phase currents
2. Calculate information related to three-phase current
3. Monitor CT secondary circuit
3.2.2.1 CT Circuit Abnormality Supervision
If any of the following two criteria is met, the corresponding alarm signal [x.AlmL_CTS] will be
issued after 10s, and it will be reset after 10s if the device returns to normal condition.
1. Calculated residual current is greater than 0.06In or greater than 0.2 times maximum phase
current.

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3 Operation Theory
2. Negative-sequence current is greater than 0.1In or greater than 0.4 times maximum phase
current.
3.2.2.2 CT Circuit Failure Supervision
When three phase currents are engaged in the calculation of transformer differential protection,
restricted earth fault protection or winding differential protection, CT circuit failure supervision of
each protection is carried out in the corresponding protection element, which can refer to
corresponding sections for details.
3.2.2.3 Current Detection
When any phase current is greater than 0.04In, inputted current signals are decided valid and the
valid signal is outputted for programmable logic application.
3.2.3 Function Block Diagram
Curr3P
x.ia x.I3P
x.ib x.Ang(Ia)
x.ic x.Ang(Ib)
x.CTS.En_Alm x.Ang(Ic)
x.Ang(3I0_Cal)
x.AlmL_CTS
x.AlmH_CTS
x.Flg_OnLoad
3.2.4 I/O Signals

Table 3.2-1 I/O signals of three-phase currents element
No. Input Signal Description

1 x.ia Sampled value of phase-A current at x side of transformer
2 x.ib Sampled value of phase-B current at x side of transformer
3 x.ic Sampled value of phase-C current at x side of transformer
The enabling input of CT circuit abnormality alarm, it is triggered from binary input or
4 x.CTS.En_Alm
programmable logic etc.
No. Output Signal Description
1 x.I3P Three-phase currents at x side of transformer
2 x.Ang(Ia) Phase angle of phase-A current at x side of transformer
3 x.Ang(Ib) Phase angle of phase-B current at x side of transformer
4 x.Ang(Ic) Phase angle of phase-C current at x side of transformer
5 x.Ang(3I0_Cal) Phase angle of calculated residual current at x side of transformer
6 x.AlmL_CTS CT secondary circuit abnormality at x side of transformer

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3 Operation Theory
7 x.AlmH_CTS CT secondary circuit failure at x side of transformer

8 x.Flg_OnLoad A flag indicating there is load current detected at x side of transformer
3.2.5 Logic
SIG x.3I0>0.06In >=1
SIG x.I2>0.1In
&
10s 10s x.AlmL_CTS
SIG x.CTS.En_Alm
SIG x.Ia>0.04In
>=1
SIG x.Ib>0.04In x.Flg_OnLoad
SIG x.Ic>0.04In
Figure 3.2-1 Logic diagram of current pre-processing
3.2.6 Settings
Table 3.2-2 Settings of three-phase currents element
No. Item Range Step Unit Description

Rated value of primary current at x side of
1 x.I1n 0~60000 1 A
transformer
Rated value of secondary current at x side of
2 x.I2n 1 or 5 A
transformer
3.3 Three-phase Voltage Element (Volt3P)
3.3.1 Application
Three-phase voltage element is responsible for pre-processing three phase voltages and
calculates sequence components, amplitudes and phases of three phase voltages, etc. All
calculated information of three-phase voltage element is used for the protection logic calculation.
NOTICE!
Three-phase voltage element has following functions:
1. Pre-process three phase voltages
2. Calculate information related to three phase voltages
3. Monitor VT secondary circuit

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3 Operation Theory
If any of two criteria is met and there is no operation of any fault detectors VT circuit abnormality
alarm will be issued after 10s. The abnormality alarm will be reset after 10s if the device returns to
normal condition.
1. Positive-sequence voltage is less than 0.3Unn and any phase current is greater than 0.04In.
2. Positive-sequence voltage is less than 0.3Unn and the circuit breaker is in closed position.
3. Negative-sequence voltage is greater than 0.08Unn.
4. The third harmonic magnitude of phase voltage is greater than 0.1Unn.
Volt3P
x.ua x.U3P
x.ub x.Ang(Ua)
x.uc x.Ang(Ub)
x.52b x.Ang(Uc)
x.In_VT x.Ang(3U0_Cal)
x.Flg_OnLoad x.Alm_VTS
3.3.4 I/O Signals

Table 3.3-1 I/O signals of three-phase voltages element
No. Input signal Description

1 x.ua Sampled value of phase-A voltage at x side of transformer
2 x.ub Sampled value of phase-B voltage at x side of transformer
3 x.uc Sampled value of phase-C voltage at x side of transformer
Binary input of auxiliary normally closed contact of a circuit breaker at x side of
4 x.52b
transformer
5 x.In_VT Input signal of indicating VT in service at x side of transformer
No. Output signal Description
1 x.U3P A voltage data set at x side of transformer
2 x.Ang(Ua) Phase angle of phase-A voltage at x side of transformer
3 x.Ang(Ub) Phase angle of phase-B voltage at x side of transformer
4 x.Ang(Uc) Phase angle of phase-C voltage at x side of transformer
5 x.Ang(3U0_Cal) Phase angle of calculated residual voltage at x side of transformer
6 x.Alm_VTS VT secondary circuit abnormality at x side of transformer

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3 Operation Theory
3.3.5 Logic
SIG x.Up_3rd>10V
>=1
SIG x.U2>8V 10s 10s x.Alm_VTS
SIG x.U1<30V
SIG x.52bx. >=1 &
SIG x.Flg_OnLoad
SIG x.In_VT
Figure 3.3-1 Logic diagram of voltage pre-processing
Where:
Up_3rd is third harmonic of phase voltage
U2 is negative-sequence voltage
U1 is positive-sequence voltage
3.3.6 Settings
Table 3.3-2 Settings of three-phase voltages element

Rated value of primary voltage at x side of
1 x.U1n 1~2000 0.001 kV
transformer
Rated value of secondary voltage at x side of
2 x.U2n 100~130 0.001 V
transformer
3.4 Residual Current Element (Curr1P)
3.4.1 Application
Residual current element is responsible for pre-processing measured residual current and
calculates the magnitude and the phase angle of residual current, etc. All calculated information of
residual current element is used for the protection logic calculation.
NOTICE!
Residual current element has following functions:
1. Pre-process measured residual current

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3 Operation Theory
2. Calculate information related to residual current
Curr1P
x.3i0 x.I1P
x.Ang(3I0_Ext)
3.4.4 I/O Signals

Table 3.4-1 I/O signals of residual current element

1 x.3i0 Measured residual current at x side of transformer
1 x.I1P A current data set at x side of transformer
2 x.Ang(3I0_Ext) Phase angle of measured residual current at x side of transformer
3.4.5 Settings
Table 3.4-2 Settings of residual current element

Primary rated current of neutral CT at x side of
1 x.I1n_NP 0~60000 1 A
transformer
Secondary rated current of neutral CT at x side of
2 x.I2n_NP 1 or 5 A
transformer
3.5 Residual Voltage Element (Volt1P)
3.5.1 Application
Residual voltage element is responsible for pre-processing residual voltage and calculates the
magnitude and the phase angle of residual voltage, etc. All calculated information of residual
voltage element is used for the protection logic calculation.
NOTICE!
Residual voltage element has following functions:
1. Pre-process measured residual voltage
2. Calculate information related to residual voltage

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3 Operation Theory
Volt1P
x.3u0 x.U1P
x.Ang(3U0_Ext)
3.5.4 I/O Signals

Table 3.5-1 I/O signals of residual voltage element

1 x.3u0 Measured residual voltage at x side of transformer
2 x.Ang(3U0_Ext) Phase angle of measured residual voltage at x side of transformer
NOTICE!
PCS-978 provides a phase calculation module (PhaseDif1P1) which is used to

calculate the phase of among residual current and residual voltage. Three input
quantities are available for this module x.AngRef, x.Ang(Ch01) and x.Ang(Ch02).
x.Ang(3I0_Cal), x.Ang(3U0_Cal), x.Ang(3I0_Ext) and x.Ang(3U0_Ext) can be
configured as input quantity of the module.
This module provides two outputs, x.Ang(Ch01-Ref) and x.Ang(Ch02-Ref), which mean
the phase between, x.Ang(Ch01) and x.AngRef and the phase between, x.Ang(Ch02)
and x.AngRef respectively.
3.5.5 Settings
Table 3.5-2 Settings of residual voltage element

Primary rated voltage of broken-delta VT at x side
1 x.U1n_Delt 1~2000 1000 kV
of transformer
Secondary rated voltage of broken-delta VT at x
2 x.U2n_Delt 10~200 100 V
side of transformer
3.6 Transformer Current Differential Protection (87T)
3.6.1 Application
In power system, the power transformer is one of most valuable and expensive equipment. If a
fault occurs in the protection zone of a transformer, current differential protection operates quickly
to clear the fault to avoid the transformer from damages or reduce the maintenance cost as low as
possible.

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3 Operation Theory

Transformer differential protection supports up to 6 group CT inputs, and can be used for
2-windings, 3-windings transformer and auto-transformer. There are 24 vector groups available for
two-winding transformer and 288 vector groups available for 3-winding transformer.
Transformer differential protection includes biased differential element, instantaneous differential

element, DPFC biased differential element. Biased differential element is biased characteristic
with three slopes Instantaneous differential element is without biased characteristic and blocking
logic and can accelerate to operate for transformer's severe internal faults. DPFC biased
differential element calculated by current variation has high sensitivity to inter-turn faults and
high-impedance fault under heavy load. Three differential elements mentioned above work
coordinately to form the high-speed current differential protection with high sensitivity.
3.6.2.1 Fault Detector
 Fault detector based on biased differential current
The fault detector can initiate biased differential element, and its operation equation is as follows.
Id>[87T.I_Biased] Equation 3.6-1
Where:
Id is the differential current of any phase.
 Fault detector based on instantaneous differential current
The fault detector can initiate instantaneous differential element, and its operation equation is as
follows.
Id>0.9x[87T.I_Inst] Equation 3.6-2
Where:
 Fault Detector based on DPFC differential current
The fault detector can initiate DPFC biased differential element, and its operation equation is as
follows.
Equation 3.6-3
Where:
ΔIdt is the floating threshold varied with the change of load current from time to time. The change of
load current is small and gradually under normal or even power swing condition, the adaptive
floating threshold (ΔIdt) is higher than the change of current under these conditions and hence the

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3 Operation Theory
element maintains stability.
Idth is fixed threshold in program. The sum value of ΔIdt and Idth is equal to 0.2p.u..
…… are DPFC current of each side of transformer representatively.
ΔId is DPFC differential current.
This fault detector, regardless of direction of power flow and very sensitive, is used to guard DPFC
biased differential protection. The setting is fixed in factory and thus site setting is not required.
3.6.2.2 Amplitude Compensation
During the normal operation, the magnitudes of secondary current of each side of transformer are
different due to the mismatch between the CT ratios and the power transformer ratio. The current
value difference between each side shall be eliminated before calculation for current differential
protection by amplitude compensation.
 Calculate rated primary current at each side
Equation 3.6-4
Where:
Sn is the maximum rated capacity (i.e., the setting [Sn]).
U1n is rated primary voltage.
U1nBrm is rated primary voltage of side m (i.e., the settings [HVS.U1n_Tr], [MVS.U1n_Tr] or
[LVS.U1n_Tr]).
I1bBrm is rated primary current of side m.
 Calculate rated secondary current at each side
Equation 3.6-5
Where:
I2bBrm is rated secondary current of side m.
CTBrm is the CT ratio of side m.
 Limitation of secondary current
For all differential protections, the secondary currents of each side must follow below criterion.
Equation 3.6-6

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3 Operation Theory
When selecting CT, the ratio between maximum value and minimum value should be considered.
It is recommended that the ratio is smaller than 16. Theoretically, the ratio is preferred to be as
small as it can be.
For DPFC biased differential element, the secondary currents of each side must follow Equation
3.6-7 in addition to Equation 3.6-6. Otherwise, alarm signals [ProtBrd.Fail_Settings] and
[FDBrd.Fail_Settings] are issued and the device will be blocked at the same time unless DPFC
biased differential element is disabled.
Max(I2bBr1/I2nBr1, I2bBr2/I2nBr2, ……, I2bBrm/I2nBrm)>0.4

Equation 3.6-7
Min(I2bBr1/I2nBr1, I2bBr2/I2nBr2, ……, I2bBrm/I2nBrm)>0.1
Where:
I2bBr1, I2bBr2… I2bBrm are rated secondary current of branch 1, 2 … m of transformer.
I2nBr1, I2nBr2…I2nBrm are CT rated secondary current of branch 1, 2 … m of transformer.
NOTICE!
If Equation 3.6-6 is not met, alarm signals [ProtBrd.Fail_Settings] and

[FDBrd.Fail_Settings] are issued and the device will be blocked at the same time.
When viewing settings and values of conventional current differential protection in the
device, p.u. (per unit value) is provided. The current in differential protection calculation
is not actual secondary value but per unit value which is got by actual secondary value
of each branch of transformer divided by transformer secondary rated current of each
side (i.e., I2bBrm).
3.6.2.3 Phase Compensation
 Phase compensation principle
False differential current is caused by phase shift between the power transformer primary current
and secondary current for delta/wye, so phases of each side secondary current must be
compensated by this phase compensation. △ →Y and Y→△ transfer methods by settings can be
selected to adjust phase angle of secondary current on each side of the transformer, and △ →Y
transfer method is recommended. Zero-sequence current is always eliminated both at Y and Δ
windings by adopting Δ→Y method.
The following transforming method is based on the assumptions listed here:
1. Each side three-phase CT of transformer shall be connected in star type.
2. The positive polarity of each side three-phase CT shall be at busbar side.
The wiring connection of HV, MV and LV sides may be different, so it is needed to compensate
phase of each side current of transformer for calculation of current differential protection. There
are two transforming methods for phase compensation: Δ→Y and Y→Δ, and different transforming
methods will result in the difference.

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3 Operation Theory
Phase compensation is controlled by the following settings:
1. [Clk_MVS_WRT_HVS], [Clk_LVS_WRT_HVS]: the wiring o’clock of MV/LV side with respect

to HV side, is the parameter shown on transformer nameplate with the range of 0~11, and
need no further calculation.
2. [Clk_PhComp]: the target o'clock each side current will be shifted to for phase compensation.
3. [HVS.En_I0Elim], [MVS.En_I0Elim] and [LVS.En_I0Elim]: logic settings to enable

zero-sequence current elimination for phase compensation of each side of transformer. The
setting is recommended to be set to “1” in general condition, and only if one side of
transformer, without earthing transformer being connected to, is not grounded, the setting of
corresponding side is recommended to be set to “0”.
For example:
The vector group of a transformer is Y0/Δ11 and the target o'clock ([Clk_PhComp]) is set to LV
side. Therefore, the setting [Clk_LVS_WRT_HVS] should be set to “11”.
1. For HV side, with reference to the set target o'clock, the o'clock of HV side is 1 (i.e. wiring
o'clock 12-target o'clock 11) clock, so the matrix of relative o'clock 1 is adopted to compensate
HV side current.
2. For LV side, with reference to the set target o'clock, the o'clock of LV side is 0 (i.e. wiring
o'clock 11- target o'clock 11), so the matrix of relative o'clock 0 is adopted to compensate LV
side current.
If an earthing transformer is connected outside the protection zone of differential protection, the
setting [HVS.En_I0Elim] (or [LVS.En_I0Elim]) could be disabled, i.e. set to 0.
If an earthing transformer is connected within the protection zone of differential protection, then
zero-sequence current must be eliminated and otherwise differential protection may operate
unexpectedly during an external fault. Therefore the setting [HVS.En_I0Elim] (or [LVS.En_I0Elim])
must be enabled, i.e., set to 1.
Table 3.6-1 Matrix of phase compensation
Matrix (without zero-sequence current Matrix (with zero-sequence current

Relative o'clock
elimination) elimination)
0
(No phase shit)
1
(Shift 30°leading)
2
(shift 60°leading)

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3 Operation Theory
3
(Shit 90°leading)
4
(Shit 120°leading)
5
(Shift 150°leading)
6
(Shift 180°leading)
7
(Shift 150°lagging)
8
(Shift 120°lagging)
S9
(Shift 90°lagging)
10
(Shift 60°lagging)
11
(Shift 30°lagging)
3.6.2.4 Calculate Differential and Restraint Currents
The equation of calculating differential current is:

 I dA   I A1  I A2   I A3  I A4 
         
 dB  M 1  I B1 2bBr1 M 2  I B 2  2bBr 2 M 3  I B3 2bBr3 M 4  I B 4  / I 2bBr 4 
I   / I   / I   / I  
 I dC   I C1  I C 2  I C 3 I C 4 
          
1 2 3 4
Equation 3.6-8
 I A5   I A6 
   
M 5   I B5  / I 2bBr5  M 6   I B6  / I 2bBr 6
I C5  I C6 
     
5 6
The above equation can be simplified to the following:
 I dA  I  A1  I  A2  I  A3  I A4  I A5  I A6


 I dB  I  B1  I  B 2  I  B3  I B 4  I B 5  I B 6 Equation 3.6-9

 I dC  I C1  I C 2  I C 3  I C 4  I C 5  I C 6

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3 Operation Theory
The equation of calculating restraint current is:
 1
 
 I rA  2 I  A1  I  A2  I  A3  I  A4  I  A5  I  A6


 I rB 
1

I B1  I B 2  I B3  I B 4  I B5  I B 6  Equation 3.6-10
 2
 1

 I rC  2 I C1  I C 2  I C 3  I C 4  I C 5  I C 6 

Where:
IAm, IBm, ICm are the secondary current of branch m (m=1, 2, 3, 4, 5, 6).
I'Am, I'Bm, I'Cm are corrected secondary current of branch m (m=1, 2, 3, 4, 5, 6).
IdA, IdB, IdC are differential currents.
IrA, IrB, IrC are restraint currents.
M1, M2, M3, M4, M5, M6 are matrixes of phase shifting of each branch of transformer respectively.
Its value is decided according to the vector group of transformer and please refers to “section
3.6.2.2” for details.
I2bBr1, I2bBr2, I2bBr3, I2bBr4, I2bBr5, I2bBr6 are rated secondary values of each branch of transformer
respectively.
Current compensation process is shown in the flowing figure by taken 2-winding transformer with
three-phase CT inputs for an example. In an ideal situation, the differential current (i.e.,
Id=I'_H+I'_L) should be zero during the normal operation of the transformer or an external fault
occurring.
*
HV side I_H I_L LV side

*
*
*
I'_H I'_L
PCS-978
Phase shift/zero sequence Phase shift/zero sequence
current elimination (*M1) current elimination (*M2)
Magnitude compensation Magnitude compensation

(/I2bBr1) (/I2bBr2)
I''_H I''_L
Calculate differential current and restraint current
Figure 3.6-1 Current compensation calculation process
Where:
I_H, I_L are primary currents of HV and LV sides respectively.

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3 Operation Theory
I'_H, I'_L are secondary currents of HV and LV sides respectively.
I''_H, I''_L are secondary corrected currents of HV and LV sides respectively.
M1, M2 are matrixes of phase shifting and zero-sequence current elimination of HV and LV sides
respectively.
I2bBr1, I2bBr2 are rated secondary currents at HV and LV sides respectively.
NOTICE!
The symbol “*” represents the polarity of CT. If current flowing into the polarity of CT, the
current direction is defined as forward direction.
To clarify the situation, three important operation conditions with ideal and matched measurement
quantities are considered.
1. Through-flowing current under undisturbed conditions or external fault:
I'_H flows into the protected zone, I'_L leaves the protected zone, according to the definition of
signs in above figure, therefore I'_H=–I'_L.
Moreover |I'_H|=|I'_L|
Id=|I'_H+I'_L|=|I'_H-I'_H|=0
Ir=(|I'_H|+|I'_L|)/2=(|I'_H|+|I'_H|)/2=|I'_H|
Differential current (Id) is far less than restraint current (Ir), and current differential protection does
not operate.
2. Internal short-circuit fault, infeed with equal currents each side:
The following applies I'_L=I'_H, moreover |I'_L|=|I'_H|
Id=|I'_H+I'_L|=|I'_H+I'_H|=2|I'_H|
Ir=(|I'_H|+|I'_L|)/2=(|I'_H|+|I'_H|)/2=|I'_H|
Differential current (Id) is two times of restraint current (Ir), and current differential protection
operates.
3. Internal short-circuit fault, infeed from one side only:
The following applies I'_L=0
Id=|I'_H+I'_L|=|I'_H+0|=|I'_H|
Ir=(|I'_H |+|I'_L|)/2=(|I'_H|+|0|)/2=|I'_H|/2
Differential current (Id) are two times of restraint current (Ir), and current differential protection
operates.
3.6.2.5 Biased Differential Element
1. Sensitive biased differential element

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3 Operation Theory
The currents for following calculation are the products of the actual secondary current of each side
multiplying its own correction coefficient. The sensitive biased differential element with low pickup
setting and restraint slope is much more sensitive for a slight internal fault. Four blocking elements,
CT saturation, inrush current, overexcitation and CT circuit failure (optional) have also been
included for the protection in order to prevent it from the unwanted operation during an external
fault.
Equation 3.6-11
Where:
Id is the differential current.
Ir is the restraint current.
IPkp is the pickup setting of biased differential protection (i.e., [87T.I_Biased]).
Knee1 and Knee2 are respectively current settings of knee point 1 and knee point 2 (i.e.,
[87T.I_Knee1] and [87T.I_Knee2]).
K1, K2 and K3 are three slopes of biased differential protection. (i.e., [87T.Slope1], [87T.Slope2],
[87T.Slope3], recommended values: [87T.Slope1]=0.2, [87T.Slope2]=0.5 and [87T.Slope3]=0.75.)
Operation characteristic of sensitive biased differential element is shown below.

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3 Operation Theory
Differential current
K=2
[87T.I_Inst]
t
en
m
le
le
ia
0.
6 nt
K= re
ffe
di
ed
as
bi
[87T.Slope1] ve [87T.Slope3]
iti
ns
se
of
ea
ar
n
a tio
er
op
1.2
[87T.Slope2]
[87T.I_Biased] Restraint current

0.8
[87T.I_Knee1] [87T.I_Knee2]
Figure 3.6-2 Operation characteristic of sensitive biased differential element
2. Conventional biased differential element
Conventional biased differential element with higher setting and restraint coefficient comparing
with sensitive biased differential element is blocked only by an inrush current detection.
Conventional biased differential element provides faster operation for severe internal faults. Its
operation criterion is:
Equation 3.6-12
NOTICE!
The slope and the knee point are fixed in program, values of which eliminate the
influence of CT saturation during an external fault and ensures reliable operation even if
CT is saturated during an internal fault by means of its biased characteristic. Therefore,
the slope and the knee point with constant values do not need to be set by user.
Operation characteristic of conventional biased differential element is shown below.

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3 Operation Theory
K=2
[87T.I_Inst]
en al
lem on
t
l e nti
tia ve
ren con
iffe of
d d area
bia ation
K=0.6
se
er
op
1.2
Restraint current
0.8
Figure 3.6-3 Operation characteristic of conventional biased differential element
3.6.2.6 Instantaneous Differential Element
Instantaneous differential element for transformer is to accelerate the operation speed for
transformer's internal fault. The element has no blocking element but to guard that the setting must
be greater than the maximum inrush current. Instantaneous differential element shall operate to
clear the fault when any phase differential current is higher than its setting. Its operation criterion
is:
Id>[87T.I_Inst] Equation 3.6-13
Where:
Id is the maximum value of three phase differential currents.

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3 Operation Theory
F operation area of instantaneous
K=2 differential element
[87T.I_Inst]
of d
r ea ase t K=0.6
a i n
[87T.Slope1] n lb e
tio na elem
a o
e r ti a l ve
iti t
op ven nti e ns en
n r e s em
co iffe of l el [87T.Slope3]
d ea ia
ar ent
n r
io iffe
at
per ed d
E C o as
bi
D
1.2
[87T.Slope2]
[87T.I_Biased]
0.8 B Restraint current
A [87T.I_Knee2]
[87T.I_Knee1]
Figure 3.6-4 Operation characteristic of biased/instantaneous differential elements
The characteristic of internal faults is a straight line with the slope 2 (63.4°) in the operation
diagram (dash-dotted line K=2)
Point A shows normal operation of transformer.
Point B shows CT saturation.
Point C, D, E, and F indicate internal faults or external fault of transformer.
1. Sensitive biased differential element will send tripping signal monitored by CT saturation,
overexcitation, inrush current and CT circuit failure (optional). It can ensure sensitivity and avoid
the unwanted operation when CT is saturated during an external fault. Its operation area is the tint
shadow area in the figure above.
When a slight intern fault occurs, differential current rises not greatly and the operating point
moves from A to D into the tripping area of sensitive biased differential protection.
When an external fault occurs, the short-circuit current rise strongly, causing a correspondingly
high restraint current (2 times through-flowing current) with little differential current. After CT
reaches saturation (point B), a differential quantity is produced and the restraint quantity is
reduced. In consequence, the operating point may moves into the tripping area of sensitive biased
differential protection. Because CT saturation criterion is equipped, sensitive biased differential
protection will not maloperate even the fault point moves into the operation area.
2. Conventional biased differential element will send tripping signal monitored by inrush current
only. It eliminates the influence of transient and steady saturations of CT during an external fault
and ensures reliable operation even if CT is in saturation condition during an internal fault by

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3 Operation Theory
means of its biased characteristic. Its operation area is the deeper shadow area in the figure
above.
When an internal fault occurs, differential current rises greatly and the operating point moves to E
in the tripping area of conventional biased differential protection. (Only the second harmonic
criterion is adapted to distinguishing inrush current for blocking conventional biased differential
protection.)
3. Unrestrained instantaneous differential protection element will send tripping signal without
any blocking if differential current of any phase reaches its setting. Its operation area is over the
above two areas with the deepest dark shadow.
When a severe internal fault occurs, differential current rises sharply and the operating point
moves to F in the operation area of instantaneous differential element.
3.6.2.7 DPFC Biased Differential Element
DPFC biased differential protection is regardless of the load current and is sensitive to small
internal fault current within the transformer. Its performance against current transformer saturation
is also good. DPFC (Deviation of Power Frequency Component) is the power frequency
component of fault component, which is the differential value between the sampling value at this
time point and that at a cycle before.
DPFC biased differential element has the higher anti-CT saturation characteristic, the sensitivity of
which to slight inter-turn fault is maintained during normal operation of transformer. The sensitivity
of transformer differential protection is improved greatly when DPFC biased differential element is
enabled, especially in the situation inter-turn fault during heavy load operation.
200
100
-100
-200
0 20 40 60 80 100 120
Original Current
100
50
-50
-100
0 20 40 60 80 100 120
DPFC current
I(k) is the sampling value at a point.
I(k-24) is the value of a sampling point before a cycle, 24 is the sampling points in one cycle.
From above figures, it is concluded that DPFC can reflect the sudden change of fault current at the
initial stage of a fault and has a perfect performance of fault detection. DPFC biased differential

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3 Operation Theory
protection reflects variation of load condition to perform a sensitive protection for the transformer.
Lab tests show that it is more sensitive than the biased differential element under the heavy load
condition. DPFC restraint current and differential current are phase-segregated. DPFC biased
differential element can be blocked by inrush current, overexcitation and CT circuit failure. The
operation criterion is as follows:
Equation 3.6-14
Where:
ΔIdt is the floating threshold varied with the change of load current from time to time. The change of
load current is small and gradually under normal or even power swing condition, the adaptive
floating threshold (ΔIdt) is higher than the change of current under these conditions and hence the
Idth is fixed threshold and need not use to configure it. The sum value of ΔIdt and Idth is equal to
0.2p.u.
, , are DPFC current of branch k of the transformer.
ΔId is DPFC differential current.
ΔIr is DPFC restraint current, it is the maximum current among the restraint current of three
phases.
NOTICE!
Because the calculation of restraint current is different between DPFC biased

differential element and biased differential protection, it is difficult to test the
characteristic at site, so we recommend qualitative function test only at site.
Operation characteristic of DPFC biased differential element is shown below.

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3 Operation Theory
K=m
K=0.75
1.2p.u.
K=0.6
0.2p.u.
Restraint current
0.333p.u. 2p.u.
Figure 3.6-5 Operation characteristic of DPFC biased differential protection
The value of m is not greater than 1. For the phase with maximum restraint current, m is equal to 1,
and for other phases, m is less than 1.
DPFC biased differential element can detect a slight inter-turn fault of transformer more sensitively
than biased current differential element. During a slight inter-turn fault, fault current will flow
through transformer whether transformer is fed from one side or from both sides. Therefore,
following two typical situations (an external fault and a slight inter-turn fault) are given to show
differential and restraint current calculation.
During normal operation, Ia_HVS=1A∠0°, Ib_LVS=1A∠180°
1. A slight inter-turn fault: I'a_HVS=1.3A∠0°, I'b_LVS=1.1A∠180°, other phase are supposed

as zero
 Biased differential element:
Id=|I'a_HVS+I'b_LVS|
=|1.3A∠0°+1.1A∠180°|=0.2A
Ir=0.5x(|I'a_HVS|+|I'b_LVS|)
=0.5x(|1.3A∠0°|+|1.1A∠180°|)=1.2A
 DPFC biased differential element:
ΔId=|(I'a_HVS-Ia_HVS)+(I'b_LVS-Ib_LVS)|
=|(1.3A∠0°-1A∠0°)+(1.1A∠180°-1A∠180°)|=0.2A
ΔIr=max(|I'a_HVS-Ia_HVS|,|I'b_LVS-Ib_LVS|)

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3 Operation Theory
=max(|1.3A∠0°-1A∠0°|,|1.1A∠180°-1A∠180°|)=0.3A
Conclusion: DPFC biased differential element is more sensitive than biased differential element
during an internal fault.
2. An external fault: I'a_HVS=2A∠0°, I'b_LVS=2A∠180°, other phase are supposed as zero
 Biased differential element:
Id=|I'a_HVS+I'b_LVS|
=|2A∠0°+2A∠180°|=0A
Ir=0.5x(|I'a_HVS|+|I'b_LVS|)
=0.5x(|2A∠0°|+|2A∠180°|)=2A
 DPFC biased differential element:
ΔId=|(I'a_HVS-Ia_HVS)+(I'b_LVS-Ib_LVS)|
=|(2A∠0°-1A∠0°)+(2A∠180°-1A∠180°)|=0A
ΔIr=max(|I'a_HVS-Ia_HVS|, |I'b-_LVS-Ib_LVS|)
=max(|2A∠0°-1A∠0°|,|2A∠180°-1A∠180°|)=1A
Conclusion: DPFC biased differential element does not operate during an external fault.
3.6.2.8 Inrush Current Discrimination
The device provides optional inrush current distinguished principles: harmonic principle (second
harmonic and third harmonic) or waveform symmetry principle. The logic setting
[87T.Opt_Inrush_Ident] is used to select distinguished principle. The discrimination of inrush
current by third harmonics is independent criterion, and is not controlled by the setting
[87T.Opt_Inrush_Ident]. When an internal fault occurs and CT goes to stable saturation, there are
great third harmonic component in CT secondary current. Because sensitive biased differential
element has too high sensitivity, the third harmonic criterion is only used to block sensitive biased
differential element to prevent it from maloperation when both [87T.Opt_Inrush_Indent] and
[En_Hm3_Inrush] are set as “1”.
1. Inrush current discrimination based on harmonics
The second and third harmonics of differential current can be used to distinguish inrush current. Its
criteria are:
Equation 3.6-15
Where:
and are the second and third harmonics of phase differential current respectively.
is the fundamental component of corresponding phase differential current.

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3 Operation Theory
It is recommended to set [87T.K_Hm2_Inrush]=0.15 and [87T.K_Hm3_Inrush]=0.2.
2. Inrush current discrimination based on waveform symmetry principle
The differential current is basically the fundamental sinusoidal wave during a fault. When the
transformer is energized, plentiful harmonics will appear, and the waveform will be distorted,
interrupted and unsymmetrical. Wave symmetry principle is used to distinguish inrush current.
CT saturation characteristics make waveform unsymmetrical between the first half cycle and the
second half cycle. During internal faults, current waveform is sinusoidal wave, so two half cycles of
wave are almost symmetrical after aperiodic component is eliminated (calculate the differential of
differential current in fact).
As shown in Figure 3.6-6, arc ABC is a cycle of typical waveform of differential current with
aperiodic component. Flip the arc BC of second half cycle vertically to get the arc B'C', and then
move it forward half cycle to get the arc B''C''. The degree of symmetry of current wave is shown
as
Equation 3.6-16
Where:
X: arc AB
Y: arc B''C''
S+: are of X-Y
S-: are of X+Y
Figure 3.6-6 Schematic of waveform symmetry principle
For a differential current waveform, the area of X is almost equal to that of Y and the value of Ksym
is almost 0. For an unsymmetrical waveform, the area of X is not equal to that of Y, so the value of
Ksym is a great value. Therefore, waveform of inrush current can be distinguished from the
waveform of internal fault according to the value of K sym.
Both waveform symmetry principle and second harmonic principle are based on current distortion

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3 Operation Theory
due to inrush current, and the only difference is the mathematical method. The second harmonic
principle is to calculate the percentage of second harmonic in differential current, but the waveform
symmetry principle is to calculate the percentage of even harmonic to total differential current.
3.6.2.9 Inrush Blocking Mode
There are two optional blocking modes for inrush current, self-adaptive blocking mode and
phase-to-phase cross blocking mode, by the logic setting [87T.Opt_BlkMode_Inrush].
Self-adaptive blocking mode can enhance ability of differential protection to avoid maloperation
during transformer energization effectively and ensure high speed of differential protection for
faults under normal operation. The self-adaptive blocking mode is recommended to be selected in
the actual application.
1. Self-adaptive blocking mode
The device has an energizing detection element by current criterion (without additional breaker
position signal) to check whether the transformer is in the process of energization. Once the
transformer in the process of energization is detected, the following criterions are adopted to
improve the stability to avoid mal-operation caused by inrush current.
 Criterion 1
The device automatically decreases the restraint coefficient values of second harmonics and wave
distortion during the initial stage of transformer energization and with the passage of time
automatically increases those values which shall be not greater than corresponding values of
settings. This feature ensures biased differential element fast operation for transformer energized
on to a fault in addition to the inrush current blocking.
 Criterion 2
The device can be self-adaptive to enable the phase-to-phase crossing block mode according to
the comprehensive characteristics of three-phase differential current. If inrush current is
distinguished, the enables phase-to-phase crossing block mode for short time, and then switches
to phase-segregated blocking mode after a period.
 Criterion 3
If the second harmonic percent of differential current used as auxiliary criteria continues to rise,
then biased differential element is kept being blocked.
2. Phase-to-phase crossing blocking mode
Only if two phases current are distinguished not inrush current, then differential element of
corresponding two phases will be released to operate.
Conventional blocking mode is phase blocking mode, and a list is given below to compare the
difference among three blocking modes under different cases.
Table 3.6-2 Comparison of different blocking modes
Case Harmonic current Mode 1 Mode 2 Mode 3

1 Ida (large number of harmonic) Not operate Not operate Not operate

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3 Operation Theory
Case Harmonic current Mode 1 Mode 2 Mode 3

Idb (large number of harmonic)
Idc (large number of harmonic)
Ida (normal)
2 Idb (normal) Operate Operate Operate
Idc (normal)
Ida (large number of harmonic) Operate or not operate
3 Idb (large number of harmonic) according to differential Not operate Not operate
Idc (normal) current waveform
Ida (large number of harmonic)
4 Idb (normal) Operate Operate Not operate
Idc (normal)
Mode 1: self-adaptive blocking mode
Mode 2: phase-to-phase crossing blocking mode
Mode 3: phase blocking mode (Not provided by PCS-978)
For mode 1 in case 3, when blocking criterion 1, 2 and 3 of inrush current discrimination are all
released to differential element, differential element can operate. Otherwise, differential element
will be blocked if any of three blocking criterions blocks.
Case 4 is usually an internal fault, and blocking mode 2 can ensure differential protection operate
correctly if there is an internal fault in case 4. Case 3 may be an internal fault or inrush current, and
blocking mode 1 can distinguish through its perfect criteria, hence, it is recommended to use
blocking mode 1.
NOTICE!
Only self-adaptive blocking mode (mode 1) and phase-to-phase crossing blocking

mode (mode 2) are provided by PCS-978.
The following figure shows the logic of inrush current blocking differential protection.

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3 Operation Theory
SIG Transformer energization >=1

&
SIG Blocking criterion 1 &
SIG Blocking criterion 3
SIG Flag_NoInrush_Harm &

>=1
SET [87T.Opt_Inrush_Ident]
&
No Inrush (Phase A)
&
SIG Flag_NoInrush_Wave No Inrush (Phase B)
SIG 87T.St No Inrush (Phase C)
SIG Flag_NoInrush_Hm3 >=1
Only valid for sensitive biased

EN [87T.En_Hm3_Blk]
differential element
SIG No Inrush (Phase A) &

& >=1
& >=1
SIG No Inrush (Phase B)
Not block 87T
&
&
SIG No Inrush (Phase C)
&
>=1
SET [87T.Opt_BlkMode_Inrush]
>=1
SIG Transformer energization 100ms 0ms &
SIG Blocking criterion 2
Figure 3.6-7 Logic of inrush current blocking current differential protection
Where:
“Flag_NoInrush_Harm” is the internal signal that means no inrush current is detected by the
harmonic principle.
“Flag_NoInrush_Wave” is the internal signal that means no inrush current is detected by the
waveform symmetry principle.
“Flg_NoInrush_Hm3” is the internal signal that means no inrush current is detected by the third
harmonic principle.
3.6.2.10 CT Saturation Detection
There are two kinds of CT saturation, i.e. transient CT saturation and stable CT saturation. If an

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external fault or an internal fault occurs, CT primary current increases greatly and CT secondary
current consists of fundamental component, DC component and harmonic component. The
decaying DC component results in remanent magnetism in magnetic core, and with the
accumulation of remanent magnetism, CT goes into saturation state which is called transient CT
saturation. With the time passed, the DC component decays to zero almost and CT is still
saturated caused by AC excitation, which is called stable CT saturation.
According to tests in lab, it is found that the second harmonic component is greater than the third
harmonic component at the stage of CT transient saturation and the third harmonic is greater than
the secondary harmonic at the stage of CT stable saturation. Therefore, the second and third
harmonics both can be used to detect CT saturation.
In order to prevent an unwanted operation of sensitive biased differential protection caused by

transient or steady state saturation of CT during an external fault, the second and third harmonics
of secondary current of individual CTs are used for the protection equipment to discriminate
saturation of three-phase CT. If CT saturation is detected, then sensitive biased differential
element will be blocked.
Equation 3.6-17
Where:
is the fundamental component of one phase current.
is the secondary harmonic of the same phase current.
is the third harmonic of the same phase current.
and are fixed coefficients of secondary and third harmonics respectively.
If any harmonic of one phase current meets the above equation, it will be considered that it is CT
saturation to cause this phase differential current and sensitive biased differential element will be
blocked.
Internal faults can be distinguished from external faults by differential protection through the
asynchronous method of differential and restraint, and it is needed that the saturation free time of
CT is no less than 4ms for internal faults to ensure differential protection operate correctly with the
added CT saturation criterion.
3.6.2.11 Overexcitation Detection
When a transformer is overexcited, the exciting current will increase sharply which may result in
an unwanted operation of differential protection. Therefore the overexcitation shall be
discriminated to block differential protection. The third or fifth harmonic of differential current can
be selected to determinate overexcitation.
Id_3rd/5th>[87T.K_Hm3/Hm5_OvExc]×Id_1st Equation 3.6-18

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Where:
Id_1st is the fundamental component of differential current.
Id_3rd/5th is the third or fifth harmonic of differential current.
The fifth harmonic is recommended to be selected for overexcitation calculation.
The degree of overexcitation (overexcitation factor n) can is evaluated as follows:
Equation 3.6-19
Where:
and are per unit value of voltage and frequency respectively.
The base value for calculating per unit value of voltage is rated secondary voltage value (phase
voltage) of the voltage transformer, and the base value for calculating per unit value of frequency
is rated frequency. During normal operation, n = 1.
If overexcitation factor is less than 1.4, biased differential element is blocked when the constant of
fifth or third harmonics is greater than [87T.K_Hm3/Hm5_OvExc] and this condition is judged as
overexcitation condition without damages to transformer. If overexcitation factor is greater than 1.4,
biased differential element is no longer being blocked by overexcitation because transformer is
damaged in this situation.
3.6.2.12 Differential CT Circuit Supervision
1. Differential CT circuit abnormality
If the differential current in any phase is continually greater than the alarm setting [87T.I_Alm] over
10s, the differential current abnormality alarm [87T.Alm_Diff] will be issued, but this alarm will not
block differential protection.
2. Differential CT circuit failure
The following two cases are considered as CT circuit failure, and the device can discriminate at
which side CT circuit is failure by unbalanced currents. Differential CT secondary circuit failure can
be judged more accurately and reliably by adopting combined method of voltage and current.
 First case, if none of following four conditions is satisfied after the fault detector of biased
differential current, or biased residual differential current, or biased winding differential current
picks up, it will be judged as CT circuit failure and the alarm will be issued.
1) Negative-sequence voltage at any side is greater than 2%Upp (Upp is the secondary
phase-to-phase rated voltage).
2) Any phase current at any side increases after fault detector picks up.
3) The maximum phase current is greater than 1.1p.u. after the fault detector picks up.
4) DPFC element of any phase-to-phase voltage at any side picks up.

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 If the alarm of differential CT circuit abnormality (i.e. [87T.Alm_Diff]) is issued and

negative-sequence current at one side is greater than 0.04 times maximum phase current at
the same side or greater than 0.1In, and then CT circuit failure will be judged.
3. Influence of CT circuit failure on differential protection
The alarm of CT circuit failure can be settable to block transformer differential protection, reactor
differential protection, restricted earth-fault protection and winding differential protection. The
alarm of CT circuit failure is latched once issued, it can be reset only after the failure is cleared and
the device is reset.
 Transformer's conventional biased differential element and instantaneous differential element

are always not blocked during CT circuit failure.
 Transformer's DPFC biased differential element is always blocked during CT circuit failure.
 Transformer's sensitive biased differential element will be blocked during CT circuit failure
when the logic setting [87T.En_CTS_Blk] set as “1”.
 Reactor's sensitive biased differential element will be blocked during CT circuit failure when
the logic setting [87R.En_CTS_Blk] is set as “1”.
 Biased restricted earth-fault element will be blocked during CT circuit failure when the logic
setting [64REF.En_CTS_Blk] is set as “1”.
 Biased winding differential protection will be blocked during CT circuit failure when the logic
setting [87W.En_CTS_Blk] is set as “1”.
NOTICE!
The operation time of biased differential element controlled by CT circuit failure has
additional 50ms delay than that of biased differential protection not controlled by CT
circuit failure.

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87T
87T.I3P1 87T.St
87T.I3P2 87T.On_Inst
87T.I3P3 87T.On_Biased
87T.I3P4 87T.On_DPFC
87T.I3P5 87T.Op
87T.I3P6 87T.Op_Inst
87T.En1 87T.Op_Biased
87T.En2 87T.Op_DPFC
87T.Blk 87T.Alm_Diff
87T.Alm_CTS
3.6.4 I/O Signals

Table 3.6-3 I/O signals of transformer differential protection

1 87T.I3P1 Three-phase current data input 1 for transformer current differential protection.
Input signal 1 of enabling transformer current differential protection. It is triggered
7 87T.En1
from binary input or programmable logic etc.
Input signal 2 of enabling transformer current differential protection. It is triggered
8 87T.En2
Input signal of blocking transformer current differential protection. It is triggered
9 87T.Blk
1 87T.St Transformer differential protection starts.
Instantaneous differential element of transformer differential protection is
2 87T.On_Inst
enabled.
3 87T.On_Biased Biased differential element of transformer differential protection is enabled.
4 87T.On_DPFC DPFC differential element of transformer differential protection is enabled.
5 87T.Op_Inst Instantaneous differential element of transformer differential protection operates.
6 87T.Op_Biased Biased differential element of transformer differential protection operates.
7 87T.Op_DPFC DPFC differential element of transformer differential protection operates.

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8 87T.Op Transformer differential protection operates.
9 87T.Alm_Diff Differential current of transformer differential protection is abnormal.
10 87T.Alm_CTS CT secondary circuit of transformer differential protection is abnormal.
Instantaneous differential element of transformer differential protection picks up
11 87T.TrigDFR_Inst
to trigger DFR function.
Biased differential element of transformer differential protection picks up to trigger
12 87T.TrigDFR_Biased
DFR function.
DPFC differential element of transformer differential protection picks up to trigger
13 87T.TrigDFR_DPFC
DFR function.
3.6.5 Logic
SIG 87T.En1
&
SIG 87T.En2
SIG 87T.Blk
EN [87T.En_Inst] &
SET Idmax>[87T.I_Inst]
&
EN [87T.En_Biased] & >=1 87T.St
SET Idmax>[87T.I_Biased]
EN [87T.En_DPFC] &
SET ΔId>1.25ΔIdt+Idth
Figure 3.6-8 Logic diagram of transformer differential protection start
EN [87T.En_Inst]
&
SIG 87T.En1
& 87T.On_Inst
SIG 87T.En2
SIG 87T.Blk
&
SET Idmax>[87T.I_Inst]
87T.Op_Inst
SIG 87T.FD_Inst 0ms 500ms
Figure 3.6-9 Logic diagram of instantaneous differential element

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EN [87T.En_Biased]
&
SIG 87T.En1
& 87T.On_Biased
SIG 87T.En2
SIG 87T.Blk
SIG Conventional 87T & &
SIG Inrush current
SIG 87T.FD_Biased 0ms 500ms
EN [87T.En_Biased]
&
SIG 87T.En1
& &
SIG 87T.En2
SIG 87T.Blk
>=1
SIG Sensitive 87T 0ms 500ms & 87T.Op_Biased
SIG CT saturation >=1
SIG Inrush current
SIG CT circuit failure & &

&
EN [87T.En_CTS_Blk]
SIG Overexcitation &
SIG U*/f*>1.4
SIG 87T.FD_Biased 0ms 500ms
Figure 3.6-10 Logic diagram of biased differential element

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EN [87T.En_DPFC]
&
SIG 87T.En1
& 87T.On_DPFC
SIG 87T.En2
SIG 87T.Blk
SIG DPFC 87T
SIG Inrush current

& &
SIG CT circuit failure 87T.Op_DPFC
SIG Overexcitation &
SIG U*/f*>1.4
SIG 87T.FD_DPFC 0ms 500ms
Figure 3.6-11 Logic diagram of DPFC biased differential element
SIG U2>2%Upp >=1
>=1
SIG DPFC line voltage pickup
>=1 &
SIG Any phase current increase >=1 &
CT circuit failure
SIG Ipmax>1.1p.u.
SIG 87T.FD_Biased
SIG CT circuit failure &

T 0ms x.AlmH_CTS
SIG I2>0.04Ipmax or I2>0.1In
&
T 0ms 87T.Alm_CTS
Figure 3.6-12 Logic diagram of CT circuit failure alarm
Where:
Idmax is the maximum value of three phase differential currents.
“87T.FD_Inst” means that the fault detector of instantaneous differential element picks up.
“87T.FD_Biased” means that the fault detector of biased differential element picks up.
“87T.FD_DPFC” means that the fault detector of DPFC biased differential protection picks up.
“Upp” is phase-to-phase secondary rated voltage.
“T” is an internal time delay parameter, and it is floating and not open for user’s configuration.

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3 Operation Theory
3.6.6 Settings
Table 3.6-4 Settings of transformer differential protection

Current setting of knee point 1 for
1 87T.I_Knee1 0.100~1.000 0.001 p.u.
transformer differential protection
2 87T.I_Knee2 4.000~8.000 0.001 p.u.
3 87T.I_Biased 0.050~5.000 0.001 p.u. Pickup setting of biased differential element
Current setting of instantaneous differential
4 87T.I_Inst 0.050~20.000 0.001 p.u.
element
5 87T.Slope1 0.010~0.900 0.001 Slope 1 of biased differential element
Coefficient of second harmonics for inrush
8 87T.K_Hm2_Inrush 0.050~0.800 0.001
current detection
Coefficient of third harmonics for inrush
9 87T.K_Hm3_Inrush 0.050~0.800 0.001
current detection
Current setting of differential circuit
10 87T.I_Alm 0.050~1.500 0.001 p.u.
abnormality alarm
Coefficient of third or fifth harmonic for
11 87T.K_Hm3/Hm5_OvExc 0.050~0.800 0.001 overexcitation detection
The recommended value is 0.25.
Logic setting of enabling/disabling
instantaneous differential element
12 87T.En_Inst 0 or 1 1
0: disable
1: enable
conventional biased differential element
13 87T.En_Biased 0 or 1 1
0: disable
1: enable
Logic setting of enabling/disabling DPFC
biased differential element
14 87T.En_DPFC 0 or 1 1
0: disable
1: enable
Option of inrush current discrimination
principle:
15 87T.Opt_Inrush_Ident 0, 1 1
0: waveform symmetry
1: Harmonic principle
Option of inrush blocking mode
16 87T.Opt_BlkMode_Inrush 0, 1 1 0: self-adaptive blocking
1: phase-to-phase crossing
Logic setting of enabling/disabling third
17 87T.En_Hm3_Blk 0 or 1 1
harmonic blocking for inrush current

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0: disable
1: enable
Logic setting of enabling/disabling block
biased differential element during CT circuit
18 87T.En_CTS_Blk 0 or 1 1 failure
0: disable
1: enable
Option of third or fifth harmonic for
overexcitation criterion
19 87T.Opt_Hm3/Hm5_OvExc 0, 1 1
0: third harmonic
1: fifth harmonic
Tripping logic setting of transformer
differential protection
20 87T.OutMap 0000~FFFF
Refer to section 3.27 for detailed
description
3.7 Reactor Current Differential Protection (87R)
3.7.1 Application
If an earth fault or phase-to-phase fault of reactor occurs, current differential protection can
operate quickly to clear the fault to avoid the reactor from damages or reduce the maintenance
cost as low as possible. Different to transformer current differential protection based on
electromagnetic balance, reactor current differential protection is based on Kirchhoff's law, so it is
needed to develop current differential protection according to the actual application of reactor not
only to use transformer current differential protection to protect reactors.

Reactor current differential protection consists of biased differential element, instantaneous
differential element, DPFC biased differential element and zero-sequence differential element.
Biased differential element is two-slope differential element with biased characteristic.
Unrestrained differential element is to accelerate the operating speed for reactor's severe internal
faults without biased characteristic and blocking elements. DPFC biased differential element
calculated by current variation has high sensitivity to earth faults at ground end of reactor.
Zero-sequence differential element based on calculated residual current of two sides of reactor
has high sensitivity to asymmetric fault. Above four differential protection elements work
coordinately to form the high-speed current differential protection with high sensitivity.
1. Fault detector based on biased differential current
Its operation equation is as follows.

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3 Operation Theory
Id>[87R.I_Biased] Equation 3.7-1
Where:
2. Fault detector based on instantaneous differential current
Id>0.9x[87R.I_Inst] Equation 3.7-2
Where:
3. Fault detector based on DPFC differential current
Equation 3.7-3
Where:
is the floating threshold varied with the change of load current from time to time. The change
of load current is small and gradually under normal or even power swing condition, and the
adaptive floating threshold ( ) is higher than the change of current under these conditions and
hence the element maintains stability.
and are DPFC current of two ends of reactor representatively.
is DPFC differential current.
is the fixed threshold and the value is 0.2p.u..
This fault detector, regardless of direction of power flow and very sensitive, is used to guard DPFC
biased differential protection. The setting is fixed and thus site setting is not required.
4. Fault detector of residual differential current
It includes biased characteristic and instantaneous characteristic, and its operation equation is as
follows.
I0d>[87R.I_Biased]
Equation 3.7-4
I0d>[87R.I_Inst]
Where:
I0d is residual differential current.

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3 Operation Theory
Under normal condition, the magnitudes of secondary current of both ends of reactor are different
due to the mismatch between CT ratios. The current value difference shall be eliminated before
calculation for current differential protection by amplitude compensation.
1. Calculate rated primary current at each side
Sn
I1b  Equation 3.7-5
3U n
Where:
S n is the rated capacity of reactor (i.e., the setting [Sn] in “System Settings” menu).
U n is rated voltage of reactor. (i.e., the setting [Un] in “System Settings” menu).
I1b is rated primary current of reactor.
2. Calculate rated secondary current at each side
Equation 3.7-6
Where:
I2b1, I2b2 are rated secondary current of two ends of reactor.
CTLine is CT ratio at the line side of reactor (also called CT1 hereinafter).
CTNP is CT ratio at the neutral point of reactor (also called CT2 hereinafter).
3. Correction coefficients
Kph1=1
Kph2=(I1n_CT2)/(I1n_CT1) Equation 3.7-7
Kph2≤4
Where:
I1n_CT1 is the primary current of CT at the line side of reactor.
I1n_CT2 is the primary current of CT at the neutral point of reactor.
Kph1 is the correction coefficient of CT at the line side of reactor.

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Kph2 is the correction coefficient of CT at the neutral point of reactor.
Line side of reactor is taken as reference side, so the correction coefficient of line side is 1 and that
of neutral point is equal to the ratio of primary current of CT2 to primary current of CT1. The
maximum ratio of two sides is 4. If the ratio is out of the limit, the device will be blocked and
corresponding alarm messages are issued.
When viewing settings and values of current differential protection in the device, the unit “p.u.” (per
unit value) can be found. The current in differential protection calculation is not actual secondary
value but per unit value which is got by actual secondary value of each side of reactor divided by
reactor secondary rated current of each branch (i.e., I2b1, I2b2).
3.7.2.3 Calculations of Differential and Restraint Currents
 I dA   I A1  I A2 
     
I
 dB   K  /
ph1  I B1 2b1I  K 
ph2  I B 2  / I 2b 2
Equation 3.7-8
 I dC   I C1  I C 2
    
1 2
I dA  I  A1  I  A2

I dB  I  B1  I  B 2 Equation 3.7-9

I dC  I C1  I C 2
Where:
IA1, IB1, IC1 are the equation vectors, the secondary current of line side of reactor.
IA2, IB2, IC2 are the equation vectors, the secondary current of neutral side of reactor.
IA1, IB1, IC1 are the corrected secondary current of line side of reactor.
IA2, IB2, IC2 are the corrected secondary current of neutral side of reactor.
IdA, IdB, IdC are differential currents.
Kph1, Kph2 are corrected coefficients of line and neutral sides of reactor respectively.
I2b1, I2b2 are CT rated secondary values at line side and at neutral point of reactor respectively.
The equation of calculating restraint current is:
 I rA  I  A2

 I rB  I B 2 Equation 3.7-10

 I rC  I C 2
Where:
IrA, IrB, IrC are restraint currents.
Current compensation process is shown in the flowing figure. In an ideal situation, the differential

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3 Operation Theory
current (i.e., Id=I'_Line+I'_NP) should be zero during normal operation of reactor or an external
fault.
*
*
I_Line I_NP
Line side CT1 CT2 Neutral point
*
*
*
*
I'_Line I'_NP
PCS-978
Magnitude compensation (*Kph1/I2b1) Magnitude compensation (*Kph2/I2b2)
I''_Line I''_NP
Calculate differential current and restraint current
Figure 3.7-1 Current compensation calculation process
NOTICE!
current direction is defined as positive direction.
Where:
I_Line, I_NP are primary currents of line side and neutral point of reactor respectively.
I'_Line, I'_NP are secondary currents of line side and neutral point of reactor respectively.
I''_Line, I''_NP are corrected secondary currents of line side and neutral point of reactor
respectively.
CT1, CT2 are current transformer at line side and neutral point of reactor respectively.
Kph1, Kph2 are corrected coefficients of line side and neutral point of reactor respectively.
I2b1, I2b2 are rated secondary values of CT at line side and neutral point of reactor respectively.
To clarify the situation, two important operation conditions with ideal and matched measurement
quantities are considered.
I'_Line flows into the protected zone, I'_NP leaves the protected zone, i.e. is negative
according to the definition of signs in above figure, therefore I'_Line=–I'_NP.
Moreover |I'_Line|=|I'_NP|
Id=|I'_Line+I'_NP|=0
Ir=|I'_NP|=|I'_Line|
No differential current (Id=0), restraint current (Ir) corresponds to double the through-flowing

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current, and current differential protection does not operate.
2. Internal short-circuit，|I'_Line|>|I'_NP|
The following applies I'_NP=0.5xI'_Line
Id=|I'_Line+I'_NP|=|I'_Line+0.5xI'_Line|=1.5x|I'_Line|
Ir=|I'_NP|=0.5x|I'_Line|
Differential current (Id) are three times of restraint current (Ir) and corresponding to the total
fault, and current differential protection operates.
3.7.2.4 Biased Differential Element
Biased differential element with initial restraint slope consists of sensitive and conventional
differential elements as well as independent CT saturation criterion and harmonic blocking.
1. Sensitive biased differential element
The currents used in this section analysis and the following analysis have been corrected, that
means the currents for following calculation are the products of the actual secondary current of
each side multiplying its own correction coefficient.
The sensitive biased differential element with low pickup setting and restraint slope is much more
sensitive for a slight internal fault. Three blocking elements, CT saturation, inrush current, CT
circuit failure (optional) have also been included in order to prevent it from unwanted operation
during an external fault.
Equation 3.7-11
Where:
and are phase currents of line side and neutral point of reactor respectively.
is the differential current.
is the restraint current.
KP is knee point, and its value is determined by the settings [87R.I_Biased] and [87R.Slope].
In order to improve the sensitivity of differential protection, the current of neutral point is taken as
restraint current. When an internal fault occurs, current partly flows into ground through the short
circuit point, so the current of neutral point will decrease and therefore the sensitivity of differential
protection is improved. Operation characteristic of sensitive biased differential element is shown

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below.
K
[87R.I_Inst]
ia l
nt
re
ffe
di
ed
as
K=0.6 bi
it ive t
s n
en e
f s elem
e ao
ar
n
a tio
er [87R.Slope]
Op
1.2p.u.
[87R.I_Biased]
Restraint current
0 KP 0.8p.u.
Figure 3.7-2 Operation characteristic of sensitive biased differential element
2. Conventional biased differential element
Conventional biased differential element with higher setting and restraint coefficient comparing
with sensitive biased differential element, which is blocked only by an inrush current detection.
Conventional biased differential element provides fast operation for severe internal faults.
Operation criterion is:
Equation 3.7-12
NOTICE!
Parameters of this protection have been fixed in the program and do not need to be
configured by user.
Operation characteristic of conventional biased differential element is shown below.

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3 Operation Theory
[87R.I_Inst]
t l
en na
m io
le nt
l e ve
ia n
nt co
re of
ffe a
di are
K=0.6
ed n
as i o
bi rat
pe
O
1.2p.u.
Restraint current
0 0.8p.u.
Figure 3.7-3 Operation characteristic of conventional biased differential element
3.7.2.5 Instantaneous Differential Element
Instantaneous differential element for reactor is to accelerate the operation speed for reactor's
internal fault. The element has no blocking element but to guard that the setting must be greater
than the maximum unbalanced current caused by inrush current. Instantaneous differential
element shall operate to clear the fault when any phase differential current is higher than its setting.
Operation criterion is:
Id>[87R.I_Inst] Equation 3.7-13
Where:
Id is the maximum value of three phase differential currents.
Operation characteristic of instantaneous differential element is shown below.

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K
Operating area of
F instantaneous differential element
[87R.I_Inst]
t l
en na
K=0.6 l
ia
m io
nt
le nt
re
le e
ffe
ia nv
di
nt co
ed
re of
ias
eb
ffe a
di are
iv
it t
ns en
ed g
as in
se m
bi rat
of ele
pe
ea
O ar
E g
in
at
er
Op
[87R.Slope]
D
1.2p.u.
[87R.I_Biased]
A Restraint current
0 KP 0.8p.u.
Figure 3.7-4 Operation characteristic of biased and Instantaneous differential element
Where:
The value of K is not more than 1.
A is the point shows normal operation of reactor.
D, E, and F are points show internal faults of reactor.
1. Sensitive biased differential element will send tripping signal monitored by criteria of CT
transient characteristic difference, and CT circuit failure (optional). It can ensure sensitivity
and avoid the unwanted operation when CT is saturated during an external fault or caused by
inrush current. Its operation area is the tint shadow area in the figure above.
When a slight intern fault occurs, differential current rises not greatly and the operating point
moves from A to D into the operation area of sensitive biased differential element.
2. Conventional biased differential element will send tripping signal without blocking criteria. It
eliminates the influence of transient and steady CT saturations during an external fault and
ensures reliable operation even if CT is in saturation condition during an internal fault by
means of its biased characteristic. Its operation area is the deeper shadow area in the figure
above.
When an internal fault occurs, differential current rises greatly and the operating point moves
to E in the operation area of conventional biased differential element.
3. Instantaneous differential element will send tripping signal without any blocking if differential
current of any phase reaches its setting. Its operation area is over the above two areas with

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3 Operation Theory
the deepest dark shadow.
When a severe internal fault occurs, differential current rises sharply and the operating point
moves to F in the operation area of instantaneous differential element.
3.7.2.6 DPFC Biased Differential Element
DPFC biased differential element is regardless of load current and is sensitive to small internal
fault current within the reactor. Its performance against CT saturation is also good. Lab tests show
that it is more sensitive than biased differential element under the heavy load condition.
DPFC biased differential element has the higher anti-CT saturation characteristic, the sensitivity of
which to faults with fault resistance and faults close to neutral side is maintained during normal
operation of reactor. Floating threshold patent technology is adopted to prevent maloperation of
DPFC differential protection due to system frequency deviation, external faults and CB tripping
process.
The sensitivity of reactor current differential protection is improved greatly when DPFC differential
protection enabled, especially in the situation faults with fault resistance and faults close to neutral
point. Operation criteria are:
Equation 3.7-14
Where:
of load current is small and gradually under normal or even power swing condition, the adaptive
floating threshold ( ) is higher than the change of current under these conditions and hence the
is fixed threshold and need not use to configure it. The sum value of and is equal to
0.2p.u.
, , are the DPFC current of line side of reactor.
, , are the DPFC current of neutral point of reactor.
is the DPFC differential current.
is the DPFC restraint current, it is the maximum current among the restraint current of three

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3 Operation Theory
phases.
NOTICE!
Calculation of restraint current of DPFC biased differential element is different to the

biased differential element, it is difficult to test the characteristic at site, so we
recommend qualitative function test only at site.
The calculation of DPFC restraint current and differential current are phase-segregated. DPFC
biased differential element is blocked by inrush current and CT circuit failure. DPFC biased
differential element has the higher anti-CT saturation characteristic, the sensitivity of which to
slight inter-turn fault is maintained during normal operation of reactor.
An example of fault calculation is given.
During normal operation, Ia_Line=0.5A∠180°, Ib_NP=0.5A∠180°
1. An external fault: I'a_Line’=2A∠180°, I'b_NP=2A∠180°, other phase supposed zero
 Biased differential protection for the fault:
Id=|I'a_Line+I'b_NP|=|2A∠180°+2A∠180°|=0A
Ir=|I'b_NP|=|2A∠180°|=2A
 DPFC differential protection for the fault:
ΔId=|(I'a_Line-Ia_Line)+(I'b_NP-Ib_NP)|
=|(2A∠0°-0.5A∠0°)+(2A∠180°-0.5A∠180°)|=0A
ΔIr=Max(|I'a_Line-Ia_Line|, |I'b_NP-Ib_NP|)
=Max(|2A∠0°-0.5A∠0°|,| 2A∠180°-0.5A∠180°|)=1.5A
Conclusion: DPFC differential protection does not operate during an external fault.
2. A sight turn-to-ground fault: I'a_Line=1.1A∠0°, I'b_NP=0.7A∠180°, other phase supposed

zero
 Biased differential protection for the fault:
Id=|I'a_Line+I'b_NP|=|1.1A∠0°+0.7A∠180°|=0.3A
Ir=|I'b_NP|=0.7A
 DPFC differential protection for the fault:
ΔId=|(I'a_Line-Ia_Line)+(I'b_NP-Ib_NP)|
=|(1.1A∠0°-0.5A∠0°)+(0.7A∠180°-0.5A∠180°)|=0.4A
ΔIr= Max(|I'a_Line-Ia_Line|, |I'b_NP-Ib_NP|)
=Max(|1.1A(∠0°-0.5A∠0°|,|0.7A∠180°-0.5A∠180°|)=0.6A
Conclusion: DPFC differential protection is more sensitive than biased differential protection

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3 Operation Theory
during an internal fault.
Operation area of DPFC
K=m
K=0.75
1.2p.u.
0.2p.u. K=0.6 Restraint current
0.333p.u. 2p.u.
Figure 3.7-5 Operation characteristic of DPFC biased differential element
The value of m is not greater than 1. For the phase with maximum restraint current, m is equal to 1,
and for other phases, m is less than 1.
3.7.2.7 Zero-sequence Differential Element
Operation criteria are:
Equation 3.7-15
Equation 3.7-16
Equation 3.7-17
Where:
are calculated residual current of two ends of reactor respectively
is residual differential current.
is residual restraint current
In order to prevent zero-sequence differential element from being affected by non-identical CT

transient characteristic and CT saturation, positive-sequence current restraint blocking criterion is
adopted and its criterion is showed below.

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3 Operation Theory
I0>β0×I1 Equation 3.7-18
Where:
I0 is the zero-sequence current at a side.
I1 is its corresponding positive-sequence current.
β0 is a proportional constant.
Operation characteristic of zero-sequence differential element is shown below.

Operating area of
instantaneous zero-sequence
F
[87R.I_Inst]
l l
tia na
K=0.6
en tio
ce
t fe r e n
en
en dif nv
qu
o
e
el nc of c
- s
ro
ze t
ue a
em e
eq re
iv e e n
-s a
sit m
ro ing
en ele
f s tial
ze r a t
o
ea eren
pe
ar
O
g diff
a tin
er
Op
[87R.Slope]
1.2p.u.
[87R.I_Biased]
Restraint current
0 KP 0.8p.u.
Figure 3.7-6 Operation characteristic of zero-sequence differential element
3.7.2.8 Inrush Current Discrimination
Please refer to Section 3.6.2.8 for details.
3.7.2.10 Differential CT Circuit Supervision

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3 Operation Theory
87R
87R.I3P1 87R.St
87R.I3P2 87R.Op
87R.En1 87R.Op_Inst
87R.En2 87R.Op_InstREF
87R.Blk 87R.Op_Biased
87R.Op_DPFC
87R.Op_REF
87R.On_Inst
87R.On_InstREF
87R.On_Biased
87R.On_DPFC
87R.On_DPFC
87R.Alm_Diff
87R.Alm_CTS
3.7.4 I/O Signals

Table 3.7-1 I/O signals of reactor differential protection

1 87R.I3P1 Three-phase current data input 1 for reactor differential protection.
Input signal 1 of enabling reactor differential protection. It is triggered from binary
3 87R.En1
input or programmable logic etc.
Input signal 2 of enabling reactor differential protection. It is triggered from binary
4 87R.En2
Input signal of blocking reactor differential protection. It is triggered from binary
5 87R.Blk
1 87R.St Reactor differential protection starts.
2 87R Op_Inst Instantaneous differential element of reactor differential protection operates.
Instantaneous zero-sequence differential element of reactor differential
3 87R Op_InstREF
protection operates.
4 87R Op_Biased Biased differential element of reactor differential protection operates.
5 87R Op_DPFC DPFC differential element of reactor differential protection operates.

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3 Operation Theory

6 87R Op_REF Zero-sequence differential element of reactor differential protection operates.
7 87R.Op Reactor differential protection operates.
8 87R On_Inst Instantaneous differential element of reactor differential protection is enabled.
9 87R On_InstREF
protection is enabled.
10 87R On_Biased Biased differential element of reactor differential protection is enabled.
11 87R On_DPFC DPFC differential element of reactor differential protection is enabled.
12 87R On_REF Zero-sequence differential element of reactor differential protection is enabled.
13 87R Alm_Diff Differential current of reactor differential protection is abnormal.
14 87R Alm_CTS CT secondary circuit of reactor differential protection is abnormal.
Instantaneous differential element reactor differential protection picks up to
15 87R.TrigDFR_Inst
trigger DFR function.
Biased differential element of reactor differential protection picks up to trigger
16 87R.TrigDFR_Biased
DFR function.
DPFC differential element of reactor differential protection picks up to trigger
17 87R.TrigDFR_DPFC
DFR function.
3.7.5 Logic
SIG 87R.En1
&
SIG 87R.En2
SIG 87R.Blk
EN [87R.En_Inst] &
SIG Idmax>[87R.I_Inst]
>=1
EN [87R.En_Biased] &
SIG Idmax>[87R.I_Biased]
&
EN [87R.En_REF]
&
SIG I0d>[87R.I_Inst]
>=1 >=1 87R.St
EN [87R.En_REF] &
SIG I0d>[87R.I_Biased]
EN [87R.En_DPFC] &
SIG ΔId>1.25ΔIdt+ΔIdh
Figure 3.7-7 Logic diagram of reactor differential protection start

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3 Operation Theory
EN [87R.En_Inst]
&
SIG 87R.En1
& 87R.On_Inst
SIG 87R.En2
SIG 87R.Blk
&
SET Idmax>[87R.I_Inst] 87R.Op_Inst
SIG 87R.FD_Inst 0ms 500ms
Figure 3.7-8 Logic diagram of instantaneous differential element
SIG Conventional 87R

&
SIG 87R.FD_Biased 0ms 500ms
EN [87R.En_Biased]
&
SIG 87R.En1
& 87R.On_Biased
SIG 87R.En2
&
SIG 87R.Blk
>=1
SIG Sensitive 87R & 87R.Op_Biased
SIG CT saturation
&
EN [87R.En_CTS_Blk]
SIG 87R.FD_Biased 0ms 500ms
Figure 3.7-9 Logic diagram of biased differential element
EN [87R.En_DPFC]
&
SIG 87R.En1
& 87R.On_DPFC
SIG 87R.En2
SIG 87R.Blk
SIG DPFC 87R & &

87R.Op_DPFC
SIG CT saturation
&
SIG CT circuit failure
SIG Inrush current
SIG 87R.FD_DPFC 0ms 500ms
Figure 3.7-10 Logic diagram of DPFC biased differential element

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3 Operation Theory
EN [87R.En_REF]
&
EN [87R.En_Inst] 87R.On_InstREF
SIG 87R.En1
&
SIG 87R.En2
SIG 87R.Blk
&
SET I0d>[87R.I_Inst]
87R.Op_InstREF
SIG 87R.FD_InstREF 0ms 500ms
SIG Conventional 87R REF

&
SIG 87R.FD_REF 0ms 500ms
EN [87R.En_REF]
&
SIG 87R.En1
& 87R.On_REF
SIG 87R.En2
&
SIG 87R.Blk
>=1
SIG Sensitive 87R REF & 87R.Op_REF
SIG CT saturation
&
EN [87R.En_CTS_Blk]
SIG 87R.FD_REF 0ms 500ms
Figure 3.7-11 Logic diagram of zero-sequence differential element
Where:
Idmax is the maximum value of three phase differential currents.
“87R.FD_Inst” means that the fault detector of instantaneous differential element picks up.
“87R.FD_Biased” means that the fault detector of biased differential element picks up.
“87R.FD_DPFC” means that the fault detector of DPFC biased differential protection picks up.
“87R.FD_InstREF” means that the fault detector of instantaneous zero-sequence differential

protection picks up.
“87R.FD_REF” means that the fault detector of DPFC zero-sequence differential protection picks
up.

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3 Operation Theory
3.7.6 Settings
Table 3.7-2 Settings of reactor current differential protection

1 87R.I_Biased 0.05~5 0.001 p.u. Pickup setting of biased differential element
2 87R.I_Inst 0.05~20 0.001 p.u. Current setting of instantaneous differential element
3 87R.Slope 0.1~0.9 0.001 Slope of biased differential element
4 87R.K_Hm2_Inrush 0.05~0.3 0.001
current detection
Coefficient of third harmonics for inrush current
5 87R.K_Hm3_Inrush 0.05~0.3 0.001
detection
Current setting of differential current abnormality
6 87R.I_Alm 0.1~1.5 0.001 p.u.
alarm
Logic setting of enabling/disabling instantaneous
7 87R.En_Inst 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling conventional
8 87R.En_Biased 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling DPFC biased
9 87R.En_DPFC 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling zero-sequence
10 87R.En_REF 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling block biased
differential element during CT circuit failure
11 87R.En_CTS_Blk 0 or 1
0: disable
1: enable
Tripping logic setting of reactor current differential
protection.
12 87R.OutMap 0000~FFFF The logic setting is shared by the instantaneous
differential element, biased differential element
and DPFC biased differential element.
3.8 Restricted Earth Fault Protection (64REF)
3.8.1 Application
Restricted earth fault protection (REF) is meant to protect a single winding of a power transformer,

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3 Operation Theory
and the protected winding must be earthed. In the case of delta windings, the winding must be
earthed by an earthing transformer, which must be electrically placed between the winding and the
current transformers. REF can be applied to protection of two-winding transformer, three-winding
transformer or auto-transformer.
REF is a kind of differential protection, so it calculates differential current and restrained current.
The differential current is a vector difference of the neutral current (i.e., current flowing in the
neutral conductor) and the residual current from the lines. For internal faults, this difference is
equal to the total earth fault current. REF operates on the fault current only, and is not dependent
on eventual load currents. This makes REF a very sensitive protection.
NOTICE!

3.8.2.1 Overview
The difference between current differential protection and REF is that the first one is based on
adjusted phase current balance and the latter is based on balance of calculated residual current
and residual current from neutral CT.
Three groups of REF are for each side of a three-winding transformer at most. REF is not affected
by inrush current and the tap of transformer. CT Transient detection function based on the ratio of
residual current to positive current is adopted to eliminate the influence of difference of transient
characteristic to REF.
*
HV side I_H LV side

*
*
3I0Cal'_H
Magnitude compensation
I'_HNP *
REF at HV side I_HNP
Figure 3.8-1 Application for two-windings transformer with one CB at one side

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3 Operation Theory
HV side 1
* * *
I_H1
LV side
I_H2
3I0Cal'_H1 3I0Cal'_H2 * * *
HV side 2
Magnitude
*
compensation
REF at HV side I_HNP
Magnitude
compensation
Magnitude
compensation
I'_HNP
Figure 3.8-2 Application for two-windings transformer with two CBs at one side
HV side
* * *
I_H
3I0Cal'_H I_M
*
MV side CW side
*
*
3I0Cal'_M
*
I_CW
Magnitude
LV side
compensation
REF at HV side
Magnitude
compensation
I'_CW
Magnitude
compensation
Figure 3.8-3 Application for auto-transformer
Maximum 4 group of CTs and 1 neutral point CT inputs for REF, and the maximum current inputs
applied for an auto-transformer with two circuit breakers at HV and MV sides respectively.
NOTICE!
current direction is defined as positive direction. Three phase currents and neutral point
current of a three-phase winding are used to calculate REF. Polarity of three-phase CT

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3 Operation Theory
is at busbar side, and the default polarity of neutral point CT is at transformer side as
shown in Figure 3.8-1, Figure 3.8-2 and Figure 3.8-3. It is should be noted that the
definition of CT polarity is different with other differential protection of transformer.
DANGER!
Before REF of a side is put into service on site, polarity of neutral point CT must have
been checked by a primary injection test. Otherwise an undesired operation may occur
during an external earth fault.
REF's pickup criterion is:
I0d>[x.64REF.I_Biased] Equation 3.8-1
Where:
I0d is the residual differential current of some side.
If CTs used for REF have different primary rated values, the device will automatically adjust the
currents with respective correction ratio shown as below.
I1n I1n _ max

K lph   K lb and K  min( ,4) Equation 3.8-2
I1n _ max lb
I1n _ min
Where:
K1ph is the correction coefficient of the calculated side.
I1n is CT primary rated value at calculated side.
I1n_min is minimum primary rated value among all CTs for REF.
I1n_max is maximum primary rated value among all CTs for REF.
This calculation method is to take the minimum CT primary rated value of all calculated sides as
the reference side. If the multiple of maximum CT primary rated value to minimum CT primary
rated value is greater than 4, then reference side shall be taken as 4 and other sides shall be
calculated proportionally. Otherwise, the reference side shall be taken as 1, and other sides will be
calculated proportionally.
The currents used in the following analysis have been corrected, that means the currents for
following calculation are the products of the actual secondary current of each side multiplying its
own correction coefficient (K1ph).
3.8.2.4 Calculate Differential and Restraint Current
The equation of calculating residual differential current is:

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3 Operation Theory
I0d  K lph1  I01 / I 2n _ CT1  K lph2  I02 / I 2n _ CT 2  K lph3  I03 / I 2n _ CT 3  K lph4  I04 / I 2n _ CT 4  K lphNP I NP / I 2n _ CTNP
          
1 2 3 4 5
  I 02
I 0d  I 01   I 03
  I 04
  I NP Equation 3.8-3
Where:
I0d is the residual differential current.
I01, I02, I03, I04 are secondary values of calculated residual current at each side.
INP is secondary current at neutral point.
I'01, I'02, I'03, I'04 are secondary values of corrected calculated residual current at each side.
I'NP is the secondary corrected current at neutral point.
K1ph1, K1ph2, K1ph3, K1ph4 are corrected coefficients of amplitude compensation at each side.
K1phNP is corrected coefficient of amplitude compensation at neutral point.
I2n_CT1, I2n_CT2, I2n_CT3, I2n_CT4 are CT rated secondary values at each side.
I2n_CTNP is CT rated secondary value at neutral point.
The equation of calculating residual restraint current is:
 , I02
I0r  max{ I01  , I03
 , I04
 , I0 NP } Equation 3.8-4
Where:
I0r is the residual restraint current.
Ia
*
A
Ib
*
B
Ic
*
C
*
I_NP
3I0Cal' =I'c+I'b+I'a
I'_NP REF
Figure 3.8-4 REF principle
I_NP' flows into the protected zone from ground, 3I0Cal' leaves the protected zone, i.e. is

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3 Operation Theory
positive according to the definition of signs in above figure, therefore I_NP'= 3I0Cal'.
I0d=|3I0Cal'–I_NP'|=|3I0Cal'–3I0Cal'|=0
I0r=Max(|3I0Cal'|, |I_NP'|)=|3I0Cal'|
No differential current, but restraint current corresponds to the through-flowing current, hence,
REF does not operate.
2. Internal short-circuit:
The following applies I_NP'=–3I0Cal', moreover |I_NP'|=|3I0Cal'|
3I0d=|3I0Cal'–I_NP'|=|3I0Cal'–(–3I0Cal')|=2x|3I0Cal'|
3I0r=Max(|3I0Cal'|, |I_HNP)=Max(|3I0Cal'|, |3I0Cal'|)=|3I0Cal'|
Differential current are two times of restraint current and corresponding to the total fault, hence,
REF operates.
3.8.2.5 Operation Criterion
The operation criteria of REF protection are as follows:
Equation 3.8-5
Where:
is the differential current at side x of transformer.
is the restraint current at side x of transformer.
, , , are the calculated residual currents at side x of transformer.
is the residual current from neutral point CT at side x of transformer.

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3 Operation Theory
3.8.2.6 Operation Characteristic
K=m
[x.64REF.Slope]
[x.64REF.I_Biased]
Restraint current
[x.64REF.I_Knee]
Figure 3.8-5 Operation characteristic of REF
The value of m is defined by the branch number for REF calculation. For example, there are two
branches at HV side (wye winding with neutral point earthed), so there are three branches
constitute REF of HV side and m is equal to 3.
3.8.2.7 CT Transient Characteristic Difference Detection
Non-identical CT characteristics can cause unbalance current. During phase-to-phase faults and
three-phase faults, the unbalance of three-phase CTs results in residual current which may lead to
maloperation of RFE. Therefore, positive-sequence current restraint blocking criterion is adopted
to prevent REF from maloperation in above mentioned conditions.
When the residual current of REF at each side is greater than 0 times positive-sequence current,
it is decided that zero-sequence current is caused by a fault and release REF. Positive-sequence
current restraint blocking criterion is showed below.
I0>β0×I1 Equation 3.8-6
Where:
I0 is the zero-sequence current at a side.
I1 is its corresponding positive-sequence current.
β0 is a proportional constant and the value is 0.6
CT saturation detection function based on 2nd and 3rd harmonics is adopted to avoid
maloperation of REF during an external fault. Please refer to Section 3.6.2.10 for details.

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3 Operation Theory
3.8.2.9 CT Circuit Supervision
CT circuit supervision for REF is divided into two kinds: differential CT circuit abnormality without
the pickup of the fault detector and differential CT circuit failure with the pickup of the fault detector.
3.8.2.9.1 CT Circuit Abnormality
If the following operation formula is met for 10s, CT circuit abnormality alarm of REF will be issued
without blocking the protection.
The operation formula is as follows:
I0d>Max(0.2×[x.64REF.I_Biased], 0.1In) Equation 3.8-7
3.8.2.9.2 CT Circuit Failure
64REF
x.64REF.I3P1 x.64REF.St
x.64REF.I3P2 x.64REF.On
x.64REF.I3P3 x.64REF.Op
x.64REF.I3P4 x.64REF.Alm_Diff
x.64REF.I1P x.64REF.Alm_CTS
x.64REF.En1
x.64REF.En2
x.64REF.Blk
3.8.4 I/O Signals

Table 3.8-1 I/O signals of restricted earth-fault protection

Three-phase current data input 1 for restricted earth fault protection at side x of of
1 x.64REF.I3P1
transformer.
2 x.64REF.I3P2
transformer.
3 x.64REF.I3P3
transformer.
4 x.64REF.I3P4
transformer.
Residual current data input for restricted earth fault protection at side x of of
5 x.64REF.I1P
transformer.

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Input signal 1 of enabling restricted earth fault protection at side x of of transformer.
6 x.64REF.En1
It is triggered from binary input or programmable logic etc.
Input signal 2 of enabling restricted earth fault protection at side x of of transformer.
7 x.64REF.En2
Input signal of blocking restricted earth fault protection at side x of of transformer. It
8 x.64REF.Blk
is triggered from binary input or programmable logic etc.
1 x.64REF.St Restricted earth-fault protection at side x of transformer starts.
2 x.64REF.On Restricted earth-fault protection at side x of transformer is enabled.
3 x.64REF.Op Restricted earth-fault protection at side x of transformer operates.
Differential current of restricted earth-fault protection at side x of transformer is
4 x.64REF.Alm_Diff
abnormal.
CT secondary circuit of restricted earth-fault protection at side x of transformer is
5 x.64REF.Alm_CTS
abnormal.
Restricted earth-fault protection at side x of transformer picks up to trigger DFR
6 x.64REF.TrigDFR
function.
3.8.5 Logic
SIG I0d>[x.64REF.I_Biased] &

x.64REF.St
EN [x.64REF.En] &
x.64REF.On
SIG x.64REF.En1
&
SIG x.64REF.En2
SIG x.64REF.Blk
SIG Flag_x.64REF &
SIG I0>β0×I1
&
SIG CT saturation
EN [x.64REF.En_CTS_Blk]
&
SIG x.3I0Ext>0.04In >=1 & [x.64REF.t_Op] 0ms x.64REF.Op
EN [x.64REF.En_NPCurr]
SIG x.64REF.FD 0ms 500ms
Figure 3.8-6 Logic diagram of restricted earth fault protection
Where:
“Flag_x.64REF” means that operation criterion of REF at side x is satisfied.

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3 Operation Theory
x.3I0Ext is the measured residual current at side x.
“x.64REF.FD” means that the fault detector of REF at side x picks up.
3.8.6 Settings
Table 3.8-2 Settings of restricted earth fault protection

Knee point setting of REF
1 x.64REF.I_Knee 0.1~4 0.001 In
0.5In is recommended.
2 x.64REF.I_Biased 0.05~5 0.001 In Pickup setting of REF
Percentage restraint coefficient of REF
3 x.64REF.Slope 0.2~0.75 0.001
0.5 is recommended.
Time delay for REF
4 x.64REF.t_Op 0~20 0.001 s
Recommended value is zero.
Logic setting of enabling/disabling block REF
during CT circuit failure
5 x.64REF.En_CTS_Blk 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling neutral
current criterion
6 x.64REF.En_NPCurr 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling REF
7 x.64REF.En 0 or 1 0: disable
1: enable
8 x.64REF.OutMap 0000~FFFF Tripping logic setting of REF
3.9 Winding Differential Protection (87W)
3.9.1 Application
When each side and common winding of auto-transformer are installed with three phase CTs,
winding differential protection can be equipped. Winding differential protection is based on
Kirchhoff's law, so inrush current has no effect on it. Winding differential protection consists of
phase winding differential protection and residual winding differential protection. Residual winding
differential protection adopts the calculated residual current of each side and common winding for
the protection calculation and three-phase CT polarity is easy to be checked. The operation
principle of which is similar to that of REF, but compared to REF, winding differential protection can
operate not only during internal earth faults but also during phase-to-phase faults.

3.9.2.1 Overview
Winding differential protection is based on Kirchhoff's first law and calculates differential currents

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of electrical connection circuits including phase A, phase B phase C and residual differential
currents. Inrush current and tap change of the transformer have no effect on winding differential
protection. Winding differential protection has high sensitivity to internal earth faults because there
is no load current in the restraint current. Normally, winding differential protection is applied in
following two situations.
HV side
* * *
I_H
I_M
I'_H
*
MV side
*
CW side
*
I'_M
I_CW
Magnitude
LV side
compensation Winding
* * *
differential
Magnitude protection
compensation
Magnitude I'_CW
compensation
Figure 3.9-1 Winding differential protection applied to auto-transformer
HV side 1
* * * I_Bush
*
I_H1
LV side
*
HV side
*
I_H2
* * *
I'_H1
I'_H2 HV side 2
Magnitude
compensation Winding differential
protection
Magnitude
compensation
Magnitude
compensation
I'_HBush
Figure 3.9-2 Winding differential protection applied to stub differential protection
Where:
I_HBush is primary current value of bushing CT at HV side
I'_HBush is secondary current value of bushing CT at HV side

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DANGER!
When winding differential protection is used as stub differential protection, CT polarity

must be checked. If CT polarity at CB side and bushing CT polarity at some side of a
transformer are both at busbar side, either of them must be reversed by PCS-Explorer.
The criterion of fault detector of winding differential protection is as follows.
Iwd>[87W.I_Biased] Equation 3.9-1
Where:
Iwd is winding differential current.
If CTs used by winding differential protection have differential primary rated value, then the current
compensation is carried out in the program automatically with parameters input. Following gives
the criteria of calculating correction coefficient.
I1n
K wph   K wb
I1n _ max
Equation 3.9-2
I1n _ max
K wb  min( ,4)
I1n _ min
Where:
Kwph is the correction coefficient of the calculated CT input.
I1n is the primary value of CT at calculated CT input.
I1n_min is the minimum value among primary values of all CTs for winding differential protection.
I1n_max is the maximum value among primary values of all CTs for winding differential protection.
This calculation method is to take the minimum CT primary rating of all calculated CT inputs as the
reference. If the multiple of the maximum CT primary ratio to the minimum CT primary rating is
greater than 2.95, then reference shall be taken as 2.95 and others shall be calculated
proportionally. Otherwise, the reference shall be taken as 1, and others will be calculated
proportionally.
The currents used in the following analysis have been corrected, which means the currents for
following calculation are the products of the actual secondary current of each side multiplying its
own correction coefficient (Kwph).

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3.9.2.4 Calculate Differential and Restraint Current
The differential current is as follows.
 I wdA   I A1   I A2   I A3 
       
I
 wdB   K I I I
  B1  / I 2n _ CT1  K wph2   B 2  / I 2n _ CT 2  K wph3   B3  / I 2n _ CT 3 
 I wdC  wph1  IC1  IC 2   IC 3 
       
 I wd 0   I 01  I 02   I 
  03 
1 2 3
Equation 3.9-3
 I A4   I A5 
   
I B4  I
K wph4   / I 2n _ CT 4  K wph5   B5  / I 2n _ CT 5
IC 4   IC 5 
   
 I   I 
04  05 
4 5
Equation 3.9-4
The restraint current is:
Equation 3.9-5
Where:
IwdA, IwdB, IwdC, Iwd0 are respectively three phase and residual winding differential currents.
IAn, IBn, ICn, I0n are respectively secondary values of three phase currents and calculated neutral
current of branch m (m=1, 2, 3, 4, 5).
I'An, I'Bn, I'Cn, I'0n are respectively secondary values of corrected three phase currents and
calculated residual current of branch m (m=1, 2, 3, 4, 5).
Kwph1, Kwph2, Kwph3, Kwph4, Kwph5 are corrected coefficients of each side for magnitude compensation
respectively.
I2n_CT1, I2n_CT2, I2n_CT3, I2n_CT4, I2n_CT5 are respectively rated secondary values of CTs of each
branch.
IwrA, IwrB, IwrC, Iwr0 are secondary values of three phase restraint currents and neutral restraint
current respectively.

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The operation criteria of winding differential protection is as follows, and maximum 5 branches are
supported for the calculation.
Equation 3.9-6
Where:
Iw1, Iw2, Iw3, Iw4, Iw5 are currents of five branches respectively.
Iwd is winding differential current.
Iwr is winding restraint current.
NOTICE!
For protecting an autotransformer, a winding differential protection is composed of

three-phase currents of HV side, LV side and common winding. When calculated
residual currents of each branch are used for the calculation, the winding differential
protection (87W) becomes neutral differential protection (87N) also called residual
differential protection in the following description.
3.9.2.6 Operation Characteristic

K=m
[87W.Slope]
[87W.I_Biased]
Restraint current
[87W.I_Knee]
Figure 3.9-3 Operating characteristic of winding differential protection
The value of m is defined by the branch number for winding differential protection. For example,

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winding differential protection is applied for protecting an autotransformer including HV side, MV

side and common winding and m is equal to 3.
CT saturation detection function based on 2nd and 3rd harmonics is adopted to avoid
maloperation of winding differential protection during an external fault. Please refer to Section
3.6.2.10 for details.
3.9.2.8 CT Circuit Supervision
3.9.2.8.1 CT Circuit Abnormality
If the following operation formula is met for 10s, CT circuit abnormality alarm of winding differential
protection will be issued without blocking the protection.
The operation criterion is as follows:
Iwd>max(0.2×[87W.I_Biased], 0.1In) Equation 3.9-7
Where:
In is CT rated secondary voltage.
3.9.2.8.2 CT Circuit Failure
87W
87W.I3P1 87W.St
87W.I3P2 87W.On_PhSeg
87W.I3P3 87W.On_REF
87W.I3P4 87W.Op_PhSeg
87W.I3P5 87W.Op_REF
87W.En1 87W.Alm_Diff
87W.En2 87W.Alm_CTS
87W.Blk
3.9.4 I/O Signals

Table 3.9-1 I/O signals of winding differential protection

1 87W.I3P1 Three-phase current data input 1 for winding differential protection.

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Input signal 1 of enabling winding differential protection. It is triggered from binary
6 87W.En1
Input signal 2 of enabling winding differential protection. It is triggered from binary
7 87W.En2
Input signal of blocking winding differential protection. It is triggered from binary input
8 87W.Blk
or programmable logic etc.
1 87W.St Winding differential protection starts.
2 87W.On_PhSeg Phase-segregated winding differential protection is enabled.
3 87W.On_REF Restricted earth-fault element of winding differential protection is enabled.
4 87W.Op_PhSeg Phase-segregated winding differential protection operates.
5 87W.Op_REF Restricted earth-fault element of winding differential protection operates.
6 87W.Alm_Diff Differential current of winding differential protection is abnormal.
7 87W.Alm_CTS CT secondary circuit of winding differential protection is abnormal.
8 87W.TrigDFR Winding differential protection picks up to trigger DFR function.

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3.9.5 Logic
SIG 87W.En1
&
SIG 87W.En2
SIG 87W.Blk
&
SIG Iwd>[87W.I_Biased] 87W.St
EN [87W.En]
SIG 87W.En1
&
SIG 87W.En2
&
SIG 87W.Blk
87W.On_PhSeg
EN [87W.En_PhSeg]
SIG 87W.Flag_DIFF
& &
SIG CT Staturation 87W.Op_PhSeg
EN [87W.En_CTS_Blk]
SIG 87W.FD 0ms 500ms
SIG 87W.En1
&
SIG 87W.En2
&
SIG 87W.Blk
87W.On_REF
EN [87W.En_REF]
SIG Flag_PSBlk &
SIG 87W.Flag_DIFF
& &
SIG CT Staturation 87W.Op_REF
EN [87W.En_CTS_Blk]
SIG 87W.FD 0ms 500ms
Figure 3.9-4 Logic diagram of winding differential protection
Where:
“87W.Flag_DIFF” means that the operation criterion of winding differential protection is satisfied.
“87W.FD” means that the fault detector of winding differential protection picks up.
“Flag_PSBlk” means that the operation criterion of positive-sequence blocking is satisfied.

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3.9.6 Settings
Table 3.9-2 Settings of winding differential protection

Knee point setting of biased winding differential
1 87W.I_Knee 0.1~4 0.001 In
protection.
Pickup setting of biased winding differential
2 87W.I_Biased 0.05~5 0.001 In
protection
Percentage restraint coefficient of biased
3 87W.Slope 0.1~0.9 0.001
winding differential protection
Logic setting of enabling/disabling blocking
winding differential protection during CT circuit
4 87W.En_CTS_Blk 0 or 1 failure
0: disable
1: enable
Logic setting of enabling/disabling phase winding
differential protection.
5 87W.En_PhSeg 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling winding
6 87W.En_REF 0 or 1
0: disable
1: enable
Tripping logic setting of winding differential
7 87W.OutMap 0000~FFFF
protection
3.10 Inter-turn Fault Protection (21IT)
3.10.1 Application
Shunt reactors as the key equipment are widely applied in extra-high voltage and ultra-high
voltage level power system, which has a dominate effect on safe operation of the power system.
The inter-turn fault is a common internal fault occurred in reactor, but current differential protection
cannot operate during inter-turn faults. Considering earth fault protection cannot be taken as the
fast protection for inter-turn faults, a dedicated protection for inter-turn protection of reactor is
needed to be equipped.
Inter-turn faults in reactors present a formidable challenge to the protection engineer. The current
and voltage changes encountered during an inter-turn fault can be of similar magnitude as load
variation, and therefore, sensitive, reliable protection schemes should be considered.

Inter-turn fault protection consists of zero-sequence power direction element and zero-sequence
impedance element. They can improve sensitivity and ensure the device against maloperation

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during external faults, transient process (such as series compensated lines, LC resonance, power
swing etc.) or abnormal conditions (such as pole disagreement, CT secondary circuit failure, etc.)
Inter-turn fault protection adopts the current from CT at line side of reactor. The amplitude of
residual voltage is compensated to ensure zero-sequence power direction element can distinguish
direction correctly when system impedance is too low. Inter-turn fault protection will be blocked
during CT and VT circuit failure.
DPFC inter-turn fault detector will enable inter-turn fault protection, and its operation equation is as
follows.
Equation 3.10-1
Where:
of load current is small and gradually under normal or even power swing condition, and the
adaptive floating threshold ( ) is higher than the change of current under these conditions and
hence the element maintains stability.
and are DPFC current of two ends of reactor representatively.
is DPFC differential current.
is the fixed threshold and the value is 0.2p.u..
3.10.2.2 Residual Power Direction Element
The wiring diagram of shunt reactors in power system is shown as Figure 3.10-1.
F1
AC1 Zs1 ZL Zs2 AC2
* Relay 1 Relay 2 *
Zr1 Zr2 F2
Shunt reactor 1 Shunt reactor 2
Figure 3.10-1 Wiring diagram of shunt reactors in power system
Where:
AC1, AC2: equivalent voltage source
Zs1, Zs2: equivalent system impedance

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Zr1, Zr2: impedance of shunt reactor
ZL: line impedance
F1: fault point 1
F2: fault point 2
1. F1: External single-phase earth fault of line (close-up external earth fault)
The fault point is zero-sequence power source, the equivalent zero-sequence network is shown
below.
Zs' U0 Zr2
I0
Fault PS
Figure 3.10-2 Equivalent zero-sequence network for F1
Where:
Zs': equivalent system impedance, Zs'=(Zr1//Zs1+ ZL)//Zs2
U0: relay detected zero sequence voltage
I0: relay detected zero sequence current
FaultPS: fault power source
It is an external earth fault, so viewing from the device location, zero-sequence current flows to
reactor from reactor grounding point and via transmission line back to the ground at the earth fault
point. Therefore, the equation between U0 and I0 at the relay location is: U0=I0xZr2.
Vector relation between U0 and I0 is:
U0
I0
Figure 3.10-3 Vector relation for F1
2. F2: Internal inter-turn fault
Because of the fault point in reactor, the equivalent zero-sequence network is shown below.

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Z's Zr2-1 Zr2-2

U0
I0 Fault PS
Figure 3.10-4 Equivalent zero-sequence network for F2
Where:
Z's: equivalent system impedance, Z's=(Zr2//Zs2+ ZL)//Zs2
Zr2-1: impedance of Zr2 part 1
Zr2-2: impedance of Zr2 part 2
U0: detected zero-sequence voltage by the device
I0: detected zero-sequence current by the device
Fault PS: fault power source
It is an internal inter-turn fault, so viewing from reactor relay location, zero-sequence current flows
from reactor to ground through system reactance. Therefore, the equation between U0 and I0 at
the device location is: U0=-I0xZ's.
Vector relation between U0 and I0 is
I0
U0
Figure 3.10-5 Vector relation for F2
The phase angle of residual current leading residual voltage is nearly 90°if an inter-turn fault of
reactor winding occurs. The residual current phase leads the residual voltage phase if an internal
single-phase earth fault occurs, and the residual current phase lags the residual voltage phase if
an external single-phase earth fault occurs. Therefore, the phase angle between residual current
and residual voltage can be used to distinguish internal faults from external faults. The
zero-sequence impedance of system very small compared to reactor impedance, so the residual
voltage detected by the device will not be sensitive to operate and need to be compensated.
The operation criterion of residual power direction element is:
Equation 3.10-2

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Where:
and are respectively calculated residual voltage and calculated residual current from VT
and CT at the line side of reactor.
is the zero-sequence impedance of reactor including neutral earthing reactor, i.e.,

[21I.Zn_Reac_NP].
k is the floating coefficient adaptive to variation of zero-sequence voltage and current from 0 to
0.8.
3.10.2.3 Zero-sequence Impedance Element
Zero-sequence impedance of reactor is usually thousands of ohms which is greater than system
impedance. When an inter-turn fault or internal single-phase earth fault of reactor occurs, the
impedance detected by the device is exactly the zero-sequence impedance of system. If an
external single-phase fault of reactor occurs, the impedance detected by the device is the
zero-sequence impedance of reactor. According to different values of measured impedances,
inter-turn faults (or internal fault) and external earth faults can be distinguished.
Operation criterion:
Zm<0.25xZ0 Equation 3.10-3
Where:
Zm is measured zero-sequence impedance.
Z0 is zero-sequence impedance of reactor.
NOTICE!
When VT abnormality (including star line of VT is not connected) is detected, the

operation criteria of residual power direction element and zero-sequence impedance
element are not satisfied, which implies that inter-turn fault protection is out of service.
When CT abnormality at line side is detected, the operation criteria of residual power
direction element and zero-sequence impedance element are not satisfied, which
implies that inter-turn fault protection is out of service.
21IT
21IT.I3P 21IT.St
21IT.U3P 21IT.On
21IT.En1 21IT.Op
21IT.En2
21IT.Blk

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3.10.3 I/O Signals

Table 3.10-1 I/O signals of inter-turn protection

1 21IT.I3P Three-phase current data input for inter-turn fault protection.
2 21IT.U3P Three-phase voltage data input for inter-turn fault protection.
Input signal 1 of enabling inter-turn fault protection. It is triggered from binary input or
3 21IT.En1
Input signal 2 of enabling inter-turn fault protection. It is triggered from binary input or
4 21IT.En2
Input signal of blocking inter-turn fault protection. It is triggered from binary input or
5 21IT.Blk
1 21IT.St Inter-turn fault protection starts.
2 21IT.On Inter-turn fault protection is enabled.
3 21IT.Op Inter-turn fault protection operates.
4 21IT.TrigDFR Inter-turn fault protection picks up to trigger DFR function.
3.10.4 Logic
EN [21IT.En]
&
SIG 21IT.En1
&
SIG 21IT.En2
21IT.On
SIG 21IT.Blk
SIG Flag_ZSImpedance &

& &
SIG FwdDir_ROC 21IT.Op
SIG Alm_VTS &
&
SIG AlmL_CTS
21IT.St
SIG 21IT.FD_DPFC 0ms 500ms
Figure 3.10-6 Logic diagram of inter-turn fault protection
Where:
“Flag_ZSImpedance” means that zero-sequence impedance element operates.
“FwdDir_ROC” means that zero-sequence power direction element operates.
21IT.FD_DPFC means that DPFC inter-turn fault detector operates.

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3.10.5 Settings
Table 3.10-2 Settings of inter-turn fault protection

inter-turn fault protection
1 21IT.En 0 or 1
0: disable
1: enable
Tripping logic setting of inter-turn
2 21IT.OutMap 0000~FFFF
fault protection
3.11 Overexcitation Protection (24)
3.11.1 Application
Overexcitation results from excessive applied voltage, possibly in combination with below-normal
frequency. Such condition may occur when a unit is on load, but are more likely to arise when it is
on open circuit, or at a loss of load occurrence. Transformers directly connected to generators are
in particular danger to experience overexcitation condition.
During overexcitation, field current of transformer rises greatly to cause excessive heating and
severe damage. The transformer, working magnetic flux density near the knee point, is subject to
overexcitation. Frequency range for normal operation is 45~55Hz for 50Hz working frequency of
power system and 55~65Hz for 60Hz working frequency of power system.
Overexcitation protection can be configured at any side of transformer through PCS-Explorer, and
it is recommended to be equipped at the side without OLTC.

Overexcitation protection consists of two stages definite-time overexcitation protection and one
stage inverse-time overexcitation protection for trip purpose or alarm purpose. The voltage for
protection calculation is RMS of three phase voltages and not affected by frequency fluctuation.
Overexcitation inverse-time curve is sectional linear curve, which has high adaptability.
The overexcitation degree can be reflected by overexcitation multiple which is calculated by

voltage and frequency, according to the following equation.
n=U*/f* Equation 3.11-1
Where:
U* and f* are per unit value of voltage and frequency respectively.
The base value for calculating per unit value of voltage is secondary voltage corresponding to
primary voltage of one side of transformer, and the base value for calculating per unit value of
frequency is rated frequency. Hence, under normal operation, n should be equal to 1.

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For example, overexcitation protection is equipped at HV side, primary voltage of HV side is

525kV (i.e., [HVS.U1n_Tr]=525kV) and voltage transformer ratio is 500kV/100V. The base value
for calculating per unit value of voltage is equal to:
This base voltage calculation is carried out in the device and users need not calculate VT ratio
when configure settings.
1. Definite-time operation criterion:
U*/f*>[24DTn.K_Set] Equation 3.11-2
Inverse-time overexcitation protection realizes inverse-time characteristic by linear processing on

given inverse-time operation characteristic, obtaining overexcitation multiple by calculation, and
getting the corresponding time delay by sectional linear insertion. It reflects the heat accumulation
and radiation.
Several groups of setting point with independent settings can be configured for simulating the
inverse-time operation characteristics curve and this protection can satisfy overexcitation
requirements of various transformers.
Following figure shows inverse-time characteristic of overexcitation protection.
U*/f*
n0
n1
n2
n3
n4
n5
n6
n7
n8
n9
t (s)
0 t0 t1t2 t3 t4 t5 t6 t7 t8 t9
Figure 3.11-1 Inverse-time characteristic of overexcitation protection
The main harm of overexcitation to transformer is overheat, so accumulation method is adopted

and accumulate the time delay according to curve time corresponding to calculated overexcitation
multiple. When accumulated time delay is greater than the operating time delay, inverse-time
overexcitation protection operates. Dissipating process is also simulated, when overexcitation
multiple is less than the minimum overexcitation multiple setting, the accumulated value
decreases to 0 gradually. If overexcitation protection operates and overexcitation condition
disappears, thermal accumulation value decreases to 0 in 10s.

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Overexcitation multiple comprises overexcitation information at current instant and also

overexcitation information integrated over various time intervals from its beginning.
Inverse-time characteristic curve can be specified by several overexcitation multiple settings, and
the relation among various settings of n and t are:
24DT1
24DT1.OvExc 24DT1.St
24DT1.En1 24DT1.On
24DT1.En2 24DT1.Op
24DT1.Blk
24DT2
24DT2.OvExc 24DT2.St
24DT2.En1 24DT2.On
24DT2.En2 24DT2.Alm
24DT2.Blk
24IDMT
24IDMT.OvExc 24IDMT.St
24IDMT.En1 24IDMT.On
24IDMT.En2 24IDMT.Op
24IDMT.Blk 24IDMT.Alm
3.11.4 I/O Signals

Table 3.11-1 I/O signals of overexcitation protection

Measurement data (including frequency and voltage) required by stage n of
1 24DTn.OvExc
definite-time overexcitation protection. (n=1, 2)
Input signal 1 of enabling stage n of definite-time overexcitation protection. It is
2 24DTn.En1
triggered from binary input or programmable logic etc. (n=1, 2)
3 24DTn.En2

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Input signal of blocking stage n of definite-time overexcitation protection. It is
4 24DTn.Blk
Measurement data (including frequency and voltage) required by inverse-time
5 24IDMT.OvExc
overexcitation protection.
Input signal 1 of enabling inverse-time overexcitation protection. It is triggered from
6 24IDMT.En1
binary input or programmable logic etc.
Input signal 2 of enabling inverse-time overexcitation protection. It is triggered from
7 24IDMT.En2
Input signal of blocking inverse-time overexcitation protection. It is triggered from
8 24IDMT.Blk
1 24DT1.St Stage 1 of definite-time overexcitation protection starts.
2 24DT1.On Stage 1 of definite-time overexcitation protection is enabled.
3 24DT1.Op Stage 1 of definite-time overexcitation protection operates to trip.
6 24DT2.Alm Stage 2 of definite-time overexcitation protection operates to alarm.
7 24IDMT.St Inverse-time overexcitation protection starts
8 24IDMT.On Inverse-time overexcitation protection is enabled.
9 24IDMT.Op Inverse-time overexcitation protection operates to trip.
10 24IDMT.Alm Inverse-time overexcitation protection operates to alarm.
11 24DT1.TrigDFR Stage 1 of definite-time overexcitation protection picks up to trigger DFR function.
12 24DT2.TrigDFR Stage 2 of definite-time overexcitation protection picks up to trigger DFR function.
13 24DTIDMT.TrigDFR Inverse-time overexcitation protection picks up to trigger DFR function.
3.11.5 Logic
SIG 24DT1.En1
&
SIG 24DT1.En2 &
24DT1.On
SIG 24DT1.Blk
&
EN [24DT1.En]
[24DT1.t_Op] 0ms 24DT1.Op
SIG U*/f*>[24DT1.K_Set]
24DT1.St
SIG 24DT2.En1
&
SIG 24DT2.En2 &
24DT2.On
SIG 24DT2.Blk
&
EN [24DT2.En]
[24DT2.t_Op] 0ms 24DT2.Alm
SIG U*/f*>[24DT2.K_Set]
24DT2.St
Figure 3.11-2 Logic diagram of definite-time overexcitation protection

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SIG 24IDMT.En1
&
SIG 24IDMT.En2 &
24IDMT.On
SIG 24IDMT.Blk
24IDMT.St
EN [24IDMT.En]
&
SIG U*/f*>[24IDMT.Kn_Set] & IDMT 24IDMT.Op
EN [24IDMT.En_Trp]
&
SIG U*/f*>[24IDMT.K_Alm] & IDMT 24IDMT.Alm
EN [24IDMT.En_Alm]
Figure 3.11-3 Logic diagram of inverse-time overexcitation protection
3.11.6 Settings
Table 3.11-2 Settings of overexcitation protection

It is used to set reference voltage of
overexcitation calculation, and it is
1 24.Un 0~2000 0.001 kV
usually set as primary rated voltage
at calculated side of transformer
Voltage option between phase
voltage and phase-to-phase voltage
for calculation of overexcitation
2 24.Opt_Up/Upp 0, 1 1
protection
0: phase voltage
1: phase-to-phase voltage
Multiple setting of stage 1 of
3 24DT1.K_Set 1.0~1.7 0.001 definite-time overexcitation
protection for trip purpose
Time delay setting of stage 1 of
4 24DT1.t_Op 0.1~9999 0.001 s definite-time overexcitation
Logic settings of enabling/disabling
stage 1 of definite-time
overexcitation protection for trip
5 24DT1.En 0 or 1
purpose
0: disable
1: enable
Tripping logic settings of stage 1 of
6 24DT1.OutMap 0000~FFFF definite-time overexcitation
7 24DT2.K_Set 1.0~1.7 0.001 Multiple setting of stage 2 of

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definite-time overexcitation
protection for alarm purpose
overexcitation protection for alarm
9 24DT2.En 0 or 1
purpose
0: disable
1: enable
Highest-limit multiple setting of
10 24IDMT.K0_Set 1.0~1.7 0.001 inverse-time overexcitation
protection: n0
Time delay setting corresponding to
11 24IDMT.t0_Op 0.1~9999 0.001 s
highest-limit setting: t0
Multiple setting 1 of inverse-time
12 24IDMT.K1_Set 1.0~1.7 0.001
overexcitation protection: n1
13 24IDMT.t1_Op 0.1~9999 0.001 s
multiple setting 1: t1
14 24IDMT.K2_Set 1.0~1.7 0.001
15 24IDMT.t2_Op 0.1-9999 0.001 s
16 24IDMT.K3_Set 1.0~1.7 0.001
17 24IDMT.t3_Op 0.1~9999 0.001 s
18 24IDMT.K4_Set 1.0~1.7 0.001
19 24IDMT.t4_Op 0.1~9999 0.001 s
20 24IDMT.K5_Set 1.0~1.7 0.001
21 24IDMT.t5_Op 0.1~9999 0.001 s
22 24IDMT.K6_Set 1.0~1.7 0.001
23 24IDMT.t6_Op 0.1~9999 0.001 s
24 24IDMT.K7_Set 1.0~1.7 0.001
25 24IDMT.t7_Op 0.1~9999 0.001 s Time delay setting corresponding to

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26 24IDMT.K8_Set 1.0~1.7 0.001
27 24IDMT.t8_Op 0.1~9999 0.001 s
Lowest-limit multiple setting of
28 24IDMT.K9_Set 1.0~1.7 0.001
inverse-time overexcitation: n9
29 24IDMT.t9_Op 0.1~9999 0.001 s
lowest-limit multiple setting: t9
Multiple setting of inverse-time
30 24IDMT.K_Alm 0.5~0.99 0.001 overexcitation protection for alarm
purpose
inverse-time overexcitation
31 24IDMT.En_Alm 0 or 1 protection for alarm purpose
0: disable
1: enable
Cooling time of inverse-time
32 24IDMT.t_Cooling 0.1~9999 0.001 s
33 24IDMT.En_Trp 0 or 1 protection for trip purpose
0: disable
1: enable
Tripping logic setting of inverse-time
34 24IDMT.OutMap 0000~FFFF 1
NOTICE!
Please input the corresponding values of selected 10 points of overexcitation curve of

transformer to the device and the values of 10 points are distributed averagely.
Inverse-time overexcitation protection is set with reference to the curve given by the
transformer manufactory. The relation among all settings of inverse-time overexcitation
protection is:
[24IDMT.K9_Set]<[24IDMT.K8_ Set]<…<[24IDMT.K1_Set]<[24IDMT.K0_ Set]
[24IDMT.t0_Op]<[ 24IDMT.t1_ Op]<…<[24IDMT.k8_ Op] <[24IDMT.t9_ Op]
3.12 Frequency Protection (81)
3.12.1 Application
In case of frequency decline due to lack of active power in the power system, underfrequency
protection operates to shed part of the load according to the declined value of frequency to

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re-balance between power supply and the load. On the contrary, if the power frequency of regional
rises due to the active power excess demand, overfrequency protection operates to perform
generator rejection to shed part of the generators automatically according to the rising frequency
so that power supply and the load are re-balanced.

1. Underfrequency protection
The operation criterion is:
f<[81U.f_Pkp] Equation 3.12-1
2. Overfrequency protection
f>[81O.f_Pkp] Equation 3.12-2
Where:
f is the measured system frequency.
3.12.2.2 Blocking Element
1. Underfrequency Protection
In order to prevent possible maloperation of underfrequency protection in conditions of high

harmonics, voltage circuit failures and so on, such blocking measures are carried out as follows:
1) undervoltage blocking
If the positive voltage U<0.15Un, underfrequency will be blocked.
2) df/dt blocking
If -df/dt≥[81U.df/dt_Blk], underfrequency protection will be blocked. The blocking will not be

released automatically until the system frequency recovers to be less than the setting [81U.f_Pkp].
3) frequency over-range blocking
If the system frequency is less than the setting [f_low_FreqAlm] or greater than the setting
[f_High_FreqAlm], underfrequency protection will be blocked.
2. Overfrequency Protection
In order to prevent possible maloperation of overfrequency protection in conditions of high

harmonics, voltage circuit failures and so on, such blocking measures are carried out as follows:
1) Blocking in undervoltage condition
If the positive voltage U<0.15Un, overfrequency protection will be blocked.

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3 Operation Theory
2) frequency over-range blocking element
If the system frequency is less than the setting [f_low_FreqAlm] or greater than the setting
[f_High_FreqAlm], overfrequency protection will be blocked.
3.12.2.3 Protection Principle
The operation criteria of underfrequency protection and overfrequency protection are shown as
following respectively, and the corresponding protection operates when any criterion is met.
f<[81U.UFx.f_Set] Equation 3.12-3
f>[81O.OFx.f_Set] Equation 3.12-4
Where:
f is the measured system frequency.
81O
81O.U3P 81O.St
81O.Freq 81O.OF1.On
81O.En1 81O.OF2.On
81O.En2 81O.OF3.On
81O.Blk 81O.OF4.On
81O.OF1.Op
81O.OF2.Op
81O.OF3.Op
81O.OF4.Op

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81U
81U.U3P 81U.St
81U.Freq 81U.UF1.On
81U.En1 81U.UF2.On
81U.En2 81U.UF3.On
81U.Blk 81U.UF4.On
81U.UF1.Op
81U.UF2.Op
81U.UF3.Op
81U.UF4.Op
3.12.4 I/O Signals

Table 3.12-1 I/O signals of frequency protection

1 81O.U3P Three-phase voltage data input for overfrequency protection.
2 81O.Freq Measured frequency data input for overfrequency protection.
Input signal 1 of enabling overfrequency protection. It is triggered from binary input
3 81O.En1
Input signal 2 of enabling overfrequency protection. It is triggered from binary input
4 81O.En2
Input signal of blocking overfrequency protection. It is triggered from binary input or
5 81O.Blk
6 81U.U3P Three-phase voltage data input for underfrequency protection.
7 81U.Freq Measured frequency data input for underfrequency protection.
Input signal 1 of enabling underfrequency protection. It is triggered from binary
8 81U.En1
9 81U.En2
Input signal of blocking underfrequency protection. It is triggered from binary input
10 81U.Blk
1 81O.St Overfrequency protection starts.
2 81O.OF1.On Stage 1 of overfrequency protection is enabled.
6 81O.OF1.Op Stage 1 of overfrequency protection operates.

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10 81O.TrigDFR Overfrequency protection picks up to trigger DFR function.
11 81U.St Underfrequency protection starts.
12 81U.UF1.On Stage 1 of underfrequency protection is enabled.
16 81U.UF1.Op Stage 1 of underfrequency protection operates.
20 81U.TrigDFR Underfrequency protection picks up to trigger DFR function.

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3.12.5 Logic
SIG 81U.En1
&
SIG 81U.En2 Enable 81U
SIG 81U.Blk
SIG U1<0.15Un >=1
SET -df/dt>[81U.df/dt_Blk]
SET f<[f_low_FreqAlm] >=1 >=1

Block 81U
SET f>[f_High_FreqAlm]
SIG x.In_VT
SET f<[81U.f_Pkp] 50ms 0ms &
SIG Block 81U &
SIG Enable 81U

&
SIG f<[81U.UF1.f_Set] [81U.UF1.t_Op] 0ms 81U.UF1.Op
EN [81U.UF1.En]
&
81U.UF1.On
&
SIG [81U.UF2.En]
&
81U.UF2.On
&
EN [81U.UF3.En]
&
81U.UF3.On
&
EN [81U.UF4.En]
&
81U.UF4.On
Figure 3.12-1 Logic diagram of underfrequency protection

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SIG 81O.En1
&
SIG 81O.En2 Enable 81O
SIG 81O.Blk
OTH U1<0.15Un
SET f<[f_low_FreqAlm] >=1 >=1

Block 81O
SET f>[f_High_FreqAlm]
SIG x.In_VT
SET f>[81O.f_Pkp] 50ms 0ms &
SIG Block 81O &
SIG Enable 81O

&
SET f>[81O.OF1.f_Set] [81O.OF1.t_Op] 0ms 81O.OF1.Op
EN [81O.OF1.En]
&
81O.OF1.On
&
EN [81O.OF2.En]
&
81O.OF2.On
&
EN [81O.OF3.En]
&
81O.OF3.On
&
EN [81O.OF4.En]
&
81O.OF4.On
Figure 3.12-2 Logic diagram of overfrequency protection
3.12.6 Settings
Table 3.12-2 Settings of frequency protection

Pickup setting of overfrequency
1 81O.f_Pkp 50~65 0.01 Hz
protection
2 81O.OFn.f_Set 50~65 0.01 Hz Frequency setting of stage n of

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overfrequency protection (n=1, 2, 3,
4)
Time delay of stage n of
3 81O.OFn.t_Op 0~6000 0.001 s overfrequency protection (n=1, 2, 3,
4)
stage n of overfrequency protection
4 81O.OFn.En 0 or 1 (n=1, 2, 3, 4)
0:disable
1:enable
Tripping logic setting of stage n of
5 81O.OFn.OutMap. 0000~FFFF overfrequency protection (n=1, 2, 3,
4)
Pickup setting of underfrequency
6 81U.f_Pkp 45~60 0.01 Hz
protection
df/dt setting of blocking
7 81U.df/dt_Blk 0.05~20 0.01 Hz/s
underfrequency protection
Frequency setting of stage n of
8 81U.UFn.f_Set 45~60 0.01 Hz underfrequency protection (n=1, 2,
3, 4)
9 81U.UFn.t_Op 0~6000 0.001 s underfrequency protection (n=1, 2,
3, 4)
stage n of underfrequency
10 81U.UFn.En 0 or 1 protection (n=1, 2, 3, 4)
0:disable
1:enable
df/dt blocking function for stage n of
underfrequency protection (n=1, 2,
11 81U.UFn.En_df/dt_Blk 0 or 1
3, 4)
0:disable
1:enable
12 81U.UFn.OutMap 0000~FFFF underfrequency protection (n=1, 2,
3, 4)
3.13 Impedance Protection (21)
3.13.1 Application
When phase overcurrent protection and earth fault protection cannot meet the sensitivity

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requirement of transformer backup protection, impedance protection may be configured. The

operation mode of power system has little effect on impedance protection, so impedance
protection cooperates with protections of adjacent equipment more easily.
NOTICE!
Impedance protection consists of two stages phase-to-phase impedance elements and two stages
phase-to-ground elements, and power swing blocking releasing function. CT polarity of each side
is at busbar side, and directions settings are based on this polarity.
The fault detector of impedance protection includes the fault detector based on DPFC
phase-to-phase current and the fault detector based on negative-sequence current. Impendence
protection will be enabled for 500ms if any fault detector picks up, and will keep being enabled if
phase-to-phase or phase-to-ground impedance element operates.
1. Fault detector based on DPFC phase-to-phase current
ΔI>1.25ΔIt+Ith Equation 3.13-1
Where:
ΔIt is the floating threshold value which will arise automatically and gradually according to
increasing of the output of deviation component. In order to ensure the threshold current is slightly
greater than the unbalance current, multiple 1.25 of the deviation component is reasonable.
ΔI is the deviation value of phase-to-phase current.
Ith is the fixed threshold (0.2In).
 Fault detector based on negative-sequence current
I2>0.2In Equation 3.13-2
Where:
I2 is the negative-sequence current.
In is the CT secondary rated current.
3.13.2.2 Phase-to-phase Impedance Element
Figure 3.13-1 shows operating characteristic of phase-to-phase impedance element with relay
characteristic angle [x.21.RCA] (φm).

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jx
Zp
m
R
Zn
Figure 3.13-1 Operating characteristic of phase-to-phase impedance element
Where:
Zn is the reverse impedance setting [x.21.ZP1.Z_Rev] or [x.21.ZP2.Z_Rev] (pointing to system)
Zp is the forward impedance setting [x.21.ZP1.Z_Fwd] or [x.21.ZP2.Z_Fwd] (pointing to

transformer)
The operation criterion of phase-to-phase impedance element is:
Equation 3.13-3
NOTICE!
If VT circuit abnormal message [x.Alm_VTS] is issued or VT is out of service,

impedance protection will be blocked.
3.13.2.3 Phase-to-ground Impedance Element
Figure 3.13-2 shows operating characteristic of phase-to-ground impedance element with relay
characteristic angle [x.21.RCA].
jx
Zp
m
R
Zn
Figure 3.13-2 Operating characteristic of phase-to-ground impedance element

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Where:
Zn is the reverse impedance setting [x.21.ZG1.Z_Rev] or [x.21.ZG2.Z_Rev] (pointing to system)
Zp is the forward impedance setting [x.21.ZG1.Z_Fwd] or [x.21.ZG2.Z_Fwd] (pointing to

transformer)
The operation criterion of phase-to-phase impedance relay is as follows.
Equation 3.13-4
Where:
K=(Z0-Z1)/3Z1 is the zero-sequence compensation coefficient ([x.21.K0]) and recommended value

is 0~2. “k” is generally 0.6 if protection direction points to local busbar, and “k” is 0~0.1, if
protection direction points to transformer.
3.13.2.4 Power Swing Blocking Releasing (PSBR)
PCS-978 adopts releasing power swing blocking to avoid maloperation of impedance protection
resulting from power swing. In another word, in order to avoid unwanted operation of impedance
relay during system oscillation, the protection is blocked all along under the normal condition and
power swing. Only if fault (internal fault or power swing with internal fault) is detected, power swing
blocking for impedance protection is released by PSBR element.
Power swing blocking for impedance element will be released if any of the following PSBR
elements operate.
1. Fault detector PSBR element (FD PSBR)
2. Unsymmetrical fault PSBR element (UF PSBR)
3. Symmetrical fault PSBR element (SF PSBR)
1. Fault detector PSBR element
If any of the following condition is matched, FD PSBR will operate for 160ms.
1) Positive-sequence overcurrent element does not operate (i.e. Equation 3.13-5 is met) at the
moment that one of the fault detectors of impedance protection picks up.
I1<[x.21.I_PSBR] Equation 3.13-5
I1 is positive-sequence current.
2) Positive-sequence overcurrent element operates (i.e. Equation 3.13-6 is met) at the moment
that one of the fault detectors of impedance protection picks up, but the duration of keeping
operating is less than 10ms.
I1>[x.21.I_PSBR] Equation 3.13-6

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3 Operation Theory
2. Unsymmetrical fault PSBR element
The operation criterion:
I 0  I 2  m  I1 Equation 3.13-7
Where:
“m” is the internal fixed coefficient which can ensure UF PSBR operate during power swing with an
internal unsymmetrical fault, while not operate during power swing or power swing with an external
fault.
I1, I2, I0 are positive-sequence current, negative-sequence current and zero-sequence current
respectively.
3. Symmetrical fault PSBR element
If a three-phase fault occurs and FD PSBR is invalid (160ms after fault detector operates), neither
FD PSBR nor UF PSBR will be able to operate to release the distance protection. Thus, SF PSBR
is provided for this case specially. This detection is based on measuring the voltage at power
swing center:
UOS=U1×COSΦ Equation 3.13-8
Where:
Φ: the angle between positive-sequence voltage and positive-sequence current
U1: the positive-sequence voltage
The criterion of SF PSBR element comprises the following two parts:
1) when -0.03UN<UOS<0.08UN, the SF PSBR element will operate after 150ms.
2) when -0.1UN<UOS<0.25UN, the SF PSBR element will operate after 500ms.
NOTICE!
If the time delay of impedance protection is more than 1.5s, PSBR function is not
required for impedance protection.

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3 Operation Theory
21
x.21.I3P x.21.St
x.21.U3P x.21.ZP1.On
x.21.En1 x.21.ZP2.On
x.21.En2 x.21.ZG1.On
x.21.Blk x.21.ZG2.On
x.21.ZP1.Op
x.21.ZP2.Op
x.21.ZG1.Op
x.21.ZG2.Op
3.13.4 I/O Signals

Table 3.13-1 I/O signals of impedance protection

1 x.21.I3P Three-phase current data input for impedance protection at side x of transformer.
2 x.21.U3P Three-phase voltage data input for impedance protection at side x of transformer.
Input signal 1 of enabling impedance protection at side x of transformer. It is
3 x.21.En1
triggered from binary input or programmable logic etc.
4 x.21.En2
Input signal of blocking impedance protection at side x of transformer. It is triggered
5 x.21.Blk
1 x.21.St Impedance protection at side x of transformer starts.
Stage n of phase-to-phase impedance protection at side x of transformer is
2 x.21.ZPn.On
enabled. (n=1, 2)
Stage n of phase-to-ground impedance protection at side x of transformer is
3 x.21.ZGn.On
enabled. (n=1, 2)
Stage n of phase-to-phase impedance protection at side x of transformer operates.
4 x.21.ZPn.Op
(n=1, 2)
Stage n of phase-to-ground impedance protection at side x of transformer
5 x.21.ZGn.Op
operates. (n=1, 2)
Stage n of phase-to-phase impedance protection at side x of transformer picks up
6 x.21.ZPn.TrigDFR
to trigger DFR function. (n=1, 2)
Stage n of phase-to-ground impedance protection at side x of transformer picks up
7 x.21.ZGn.TrigDFR
to trigger DFR function. (n=1, 2)

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3 Operation Theory
3.13.5 Logic
SIG UF PSBR >=1
SIG SF PSBR
>=1
SET I1>[x.21.I_PSBR] 10ms 0 &
0 160ms
SIG x.21.FD
>=1
EN [x.21.En_PSBR]
&
SIG Flag_ZPn x.21.ZPn.On
EN [x.21.ZPn.En]
&
SIG x.21.En1
&
SIG x.21.En2
SIG x.21.Blk
& x.21.St
SIG x.Alm_VTS >=1 &
[x.21.ZPn.t_Op] 0s x.21.ZPn.Op
SIG x.In_VT
SIG x.21.FD 0 500ms
SIG UF PSBR >=1
SIG SF PSBR
>=1
SET I1>[x.21.I_PSBR] 10ms 0 &
0 160ms
SIG x.21.FD
>=1
EN [x.21.En_PSBR]
&
SIG Flag_ZGn x.21.ZGn.On
EN [x.21.ZGn.En]
&
SIG x.21.En1
&
SIG x.21.En2
SIG x.21.Blk
&
x.21.St
SIG x.Alm_VTS >=1 &
[x.21.ZGn.t_Op] 0s x.21.ZGn.Op
SIG x.In_VT
SIG x.21.FD 0 500ms
Figure 3.13-3 Logic diagram of impedance protection (n=1, 2)

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3 Operation Theory
Where:
“x.21.FD” means that the fault detector based on DPFC phase-to-phase current or
negative-sequence current at x side of transformer operates.
“Flag_ZPn” means that phase-to-phase operation equation of stage n of impedance protection is

met.
“Flag_ZGn” means that phase-to-ground operation equation of stage n of impedance protection is

met.
3.13.6 Settings
Table 3.13-2 Settings of impedance protection

Relay characteristic angle (also called
1 x.21.RCA 1~89 0.01 deg
reach angle)
Current setting of PSBR element
2 x.21.I_PSBR 0.04~150 0.001 A It should be greater than maximum
load current.
power swing blocking releasing
function to control impedance
3 x.21.En_PSBR 0 or 1
protection
0: disable
1: enable
Forward impedance setting of stage
4 x.21.ZP1.Z_Fwd 0.01~200 0.001 Ω 1 of phase-to-phase impedance
protection
Reverse impedance setting of stage
5 x.21.ZP1.Z_Rev 0.01~200 0.001 Ω 1 of phase-to-phase impedance
protection
Time delay of stage 1 of
6 x.21.ZP1.t_Op 0.05~20 0.001 s phase-to-phase impedance
protection
stage 1 of phase-to-phase
7 x.21.ZP1.En 0 or 1 impedance protection
0: disable
1: enable
Tripping logic setting of stage 1 of
8 x.21.ZP1.OutMap 0000~FFFF phase-to-phase impedance
protection
protection

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protection
protection
0: disable
1: enable
protection
Zero-sequence compensation
14 x.21.K0 0~2 0.001
coefficient
15 x.21.ZG1.Z_Fwd 0.01~200 0.001 Ω 1 of phase-to-ground impedance
protection
16 x.21.ZG1.Z_Rev 0.01~200 0.001 Ω 1 of phase-to-ground impedance
protection
17 x.21.ZG1.t_Op 0.05~20 0.001 s phase-to-ground impedance
protection
stage 1 of phase-to-ground
18 x.21.ZG1.En 0 or 1 impedance protection
0: disable
1: enable
19 x.21.ZG1.OutMap 0000~FFFF phase-to-ground impedance
protection
protection
protection
protection
23 x.21.ZG2.En 0 or 1 Logic setting of enabling/disabling

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impedance protection
0: disable
1: enable
protection
3.14 Phase Overcurrent Protection (50/51P)
3.14.1 Application
When a fault occurs in power system, the current increases and phase overcurrent protection
operates to avoid damages to protected equipment. Voltage control element can be selected to
improve the sensitivity of phase overcurrent protection and directional element can be selected to
improve the selectivity of the protection. In case that phase overcurrent protection operates
unexpectedly, harmonic blocking element can be selected to block the protection.
An external fault will result in transformer overload, and phase overcurrent protection operates to
trip circuit breakers of transformer to avoid physical damage. To small transformers, phase
overcurrent protection can protect transformer from internal faults as main protection, to
large-scale transformers, no-directional protection is applied as the backup protection of
transformer differential protection.
NOTICE!
Phase overcurrent protection includes four stages phase overcurrent protection with independent
logic, current and time delay settings. Stage 1, 2, 3 are definite-time characteristic, and stage 4
can be selected as definite-time or inverse-time characteristic. The inverse-time characteristic is
selectable, among IEC and ANSI/IEEE standard inverse-time characteristics and a user-defined
inverse-time curve. Each stage of phase overcurrent protection can select voltage control element,
direction element, and harmonic blocking element.
IP>[x.50/51Pn.I_Set] Equation 3.14-1
Where:
IP is measured phase current.

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3.14.2.2 Time Curve
Stage 4 can be selected as definite-time or inverse-time characteristic, and the inverse-time

characteristic is selectable, among IEC and ANSI/IEEE standard inverse-time characteristics and
a user-defined inverse-time curve. The inverse-time operating time curve is as follows.
Equation 3.14-2
Where:
Iset is current setting [x.50/51P4.I_Set].
TP is time multiplier setting [x.50/51P4.TMS].
K, C is constants.
α is a constant.
The user can select the operating characteristic from various inverse-time characteristic curves by
setting [x.50/51P4.Opt_Curve], and parameters of available characteristics for selection are
shown in the following table.
Table 3.14-1 Inverse-time curve parameters
x.51P4.Opt_Curve Description K α C
DefTime Definite time
IECN IEC Normal inverse 0.14 0.02 0
IECV IEC Very inverse 13.5 1.0 0
IECE IEC Extremely inverse 80.0 2.0 0
IECST IEC Short-time inverse 0.05 0.04 0
IECLT IEC Long-time inverse 120.0 1.0 0
ANSIE ANSI Extremely inverse 28.2 2.0 0.1217
ANSIV ANSI Very inverse 19.61 2.0 0.491
ANSI ANSI Inverse 0.0086 0.02 0.0185
ANSIM ANSI Moderately inverse 0.0515 0.02 0.114
ANSILTE ANSI Long-time extremely inverse 64.07 2.0 0.25
ANSILTV ANSI Long-time very inverse 28.55 2.0 0.712
ANSILT ANSI Long-time inverse 0.086 0.02 0.185
UserDefine Programmable user-defined
If all available curves do not comply with user application, the user may configure setting
[x.50/51P4.Opt_Curve] to “UserDefine” to customize the inverse-time curve characteristic, and
constants K, α and C with PCS-Explorer software.
3.14.2.3 Voltage Control Element
Phase overcurrent protection is equipped as the backup protection of transformer and adjacent

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power equipment, and voltage is usually used to control phase overcurrent protection to improve
sensitivity of the protection. Unsymmetrical faults result in unsymmetrical sequence voltages and
symmetrical faults lead to low three phase voltages at relay location, so phase overcurrent
protection can operate if the sequence voltage greater than a setting or phase voltage lower than
a setting. Therefore, current settings of phase overcurrent protection can be set lower with high
sensitivity.
The voltage control element picks up if phase-to-phase voltage is lower than its setting or
negative-sequence voltage is greater than its setting. The operation criterion is:
UΦΦ<[x.50/51P.VCE.UPP_VCE] Equation 3.14-3
or
U2>[ x.50/51P.VCE.U2_VCE] Equation 3.14-4
Where:
UΦΦ is the phase-to-phase voltage.
U2 is the negative-sequence voltage.
The voltage at any side can be used as the input of voltage control element, and there is a logic
settings used to select at which side voltage control element is used to control phase overcurrent
protection of some side.
Overcurrent element Voltage control

Ia> Uab< or Uca< or U2>
Ib> Ubc< or Uab< or U2>
Ic> Uca< or Ubc< or U2>
3.14.2.4 Direction Element
Phase overcurrent protection can select to be controlled by direction element to fulfill coordinating
with other protections of power grid
Positive-sequence voltage (U1) is adopted as polarizing voltage, and memory voltage is used
during close-up faults to ensure the direction element working properly. Phase current (IP) is
adopted for calculation of direction element, and if phase current is less than current threshold,
neither of forward and reverse directions is met.
When a fault occurs at forward direction, the angle between polarizing voltage and fault current is:
Equation 3.14-5
When a fault occurs at reverse direction, the angle is:

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3 Operation Theory
Equation 3.14-6
Relay characteristic angle [ x.50/51P.DIR.RCA], i.e., the angle polarizing voltage leading fault
current, is given as the directional setting, and the forward operating range is:
Equation 3.14-7
If VT and CT are connected as shown in Figure 3.14-1, i.e. polarity of CT is at busbar side, and
forward direction points to protected object, then forward and reverse operating regions are shown
in Figure 3.14-2.
VT
Dir
Reverse
Direction
Element
CT
Forward
Protected
Object
Figure 3.14-1 VT and CT connection of direction element
Reverse
URef (U1)
Φsen
Φsen+180°
IDir (Ip) Forward
Figure 3.14-2 Directional characteristic
3.14.2.5 Harmonic Blocking Element
When phase overcurrent protection is used to protect transformer during transformer energization,
in order to prevent inrush current leading to maloperation of phase overcurrent protection,
harmonic blocking function can be selected.
Blocking mode is selectable between phase segregated blocking mode or phase crossing

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3 Operation Theory
blocking mode through the setting [x.50/51P.HMB.Opt_HmBlk]. If any phase harmonic meets the
following criterion, harmonic blocking condition is satisfied. However, when any phase current is
greater than the setting [x.50/51P.HMB.I_Rls_HmBlk], phase overcurrent protection does not be
blocked by harmonic even if blocking condition is satisfied.
Operation criterion:
IP_2nd>[x.50/51P.HMB.K_Hm2]×IP Equation 3.14-8
Where:
IP_2nd is second harmonic of phase current
IP is fundamental component of phase current.
If fundamental component of any phase current is lower than the minimum operating current
(0.04In), then harmonic calculation is not carried out and harmonic blocking element does not
work.
50/51P
x.50/51Pn.I3P x.50/51Pn.St
x.50/51Pn.U3P x.50/51Pn.On
x.50/51Pn.En1 x.50/51Pn.Op
x.50/51Pn.En2
x.50/51Pn.Blk
3.14.4 I/O Signals

Table 3.14-2 I/O signals of phase overcurrent protection

Three-phase current data input for stage n of phase overcurrent protection at side
1 x.50/51Pn.I3P
x of transformer or reactor. (n=1, 2, 3, 4)
Three-phase voltage data input for stage n of phase overcurrent protection at side
2 x.50/51Pn.U3P
x of transformer or reactor. (n=1, 2, 3, 4)
Input signal 1 of enabling stage n of phase overcurrent protection at side x of
3 x.50/51Pn.En1 transformer or reactor. It is triggered from binary input or programmable logic etc.
(n=1, 2, 3, 4)
4 x.50/51Pn.En2 transformer or reactor. It is triggered from binary input or programmable logic etc.
(n=1, 2, 3, 4)
Input signal of blocking stage n of phase overcurrent protection at side x of
5 x.50/51Pn.Blk
transformer or reactor. It is triggered from binary input or programmable logic etc.

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(n=1, 2, 3, 4)
Stage n of phase overcurrent protection at side x of transformer or reactor starts.
1 x.50/51Pn.St
(n=1, 2, 3, 4)
Stage n of phase overcurrent protection at side x of transformer or reactor is
2 x.50/51Pn.On
enabled. (n=1, 2, 3, 4)
Stage n of phase overcurrent protection at side x of transformer or reactor
3 x.50/51Pn.Op
operates. (n=1, 2, 3, 4)
Stage n of phase overcurrent protection at side x of transformer or reactor picks up
4 x.50/51Pn.TrigDFR
to trigger DFR function. (n=1, 2, 3, 4)
3.14.5 Logic
SIG x.50/51Pn.VCE.En &

&
SIG x.50/51Pn.VCE.Blk UPP VCE Release
SET UΦΦ<[x.50/51P.VCE.Upp_VCE] &
SIG x.Alm_VTS >=1

>=1
SIG x.In_VT &
EN [x.50/51P.En_VTS_Blk]
SIG x.50/51Pn.VCE.En &

&
SIG x.50/51Pn.VCE.Blk U2 VCE Release
SET U2<[x.50/51P.VCE.U2_VCE] &
SIG x.Alm_VTS >=1

>=1
SIG x.In_VT &
EN [x.50/51P.En_VTS_Blk]
Figure 3.14-3 Logic diagram of voltage control element (n=1, 2, 3, 4)

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SET [x.50/51Pn.Opt_Dir]=Forward &
SIG Direction element (Forward)

>=1
SIG Direction element (Reverse) & &
>=1
SET [x.50/51Pn.Opt_Dir]=Reverse DIR Release
SIG x.Alm_VTS >=1

&
SIG x.In_VT
&
>=1
EN [x.50/51P.DIR.En_VTS_Blk]
SET [x.50/51Pn.Opt_Dir]=Non_Directional
Figure 3.14-4 Logic diagram of direction element (n=1, 2, 3, 4)
SIG [x.50/51Pn.En]
&
SIG x.50/51Pn.En1
& x.50/51Pn.On
SIG x.50/51Pn.En2
SIG x.50/51Pn.Blk
SET IP>[x.50/51Pn.I_Set]
SIG UPP VCE Release >=1

& x.50/51Pn.St
SIG U2 VCE Release >=1 & &
[x.50/51Pn.t_Op] 0ms x.50/51Pn.Op
EN [x.50/51Pn.En_VCE]
SIG DIR Release
SIG Second harmonic &
EN [50/51Pn.En_Hm2_Blk]
Figure 3.14-5 Logic Diagram of phase overcurrent protection (n=1, 2, 3)

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SIG [x.50/51P4.En]
&
SIG x.50/51P4.En1
& x.50/51P4.On
SIG x.50/51P4.En2
SIG x.50/51P4.Blk
SET IP>[x.50/51P4.I_Set]
SIG UPP VCE Release >=1

x.50/51P4.St
&
SIG U2 VCE Release >=1 & & Timer
t
x.50/51P4.Op
EN [x.50/51P4.En_VCE] t
SIG DIR Release
EN [50/51P4.En_Hm2_Blk]
Figure 3.14-6 Logic Diagram of phase overcurrent protection (stage 4)
Where:
UΦΦ is the phase-to-phase voltage
U2 is the negative-sequence voltage
3.14.6 Settings
Table 3.14-3 Settings of phase overcurrent protection

Phase-to-phase voltage setting of
1 x.50/51P.VCE.Upp_VCE 2~200 0.001 V
voltage control element
Negative-sequence voltage setting
2 x.50/51P.VCE.U2_VCE 2~200 0.001 V
of voltage control element
Relay characteristic angle of phase
3 x.50/51P.DIR.RCA 0~360 1 deg
overcurrent protection
Harmonic blocking coefficient of
4 x.50/51P.HMB.K_Hm2 0.05~1.0 0.001
phase overcurrent protection
Current setting of releasing harmonic
blocking function of phase
5 x.50/51P.HMB.I_Rls_HmBlk 0.04~150 0.001 A
overcurrent protection.
It is recommended to set as 0.15.
Option of harmonic blocking mode
6 x.50/51P.HMB.Opt_HmBlk 0, 1 1 0: phase-segregated blocking mode
1: phase crossing blocking mode
7 x.50/51P.En_VTS_Blk 0 or 1 block for phase overcurrent
protection during VT circuit abnormal

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0: disable
1: enable
When VT circuit fails or VT is not in
service, phase overcurrent
protection will be blocked if the
setting is set as “1”, and phase
overcurrent protection is not
controlled by direction element and
voltage control element if the setting
is set as ”0”.
Current setting of stage n of phase
8 x.50/51Pn.I_Set 0.04~30In 0.001 A
overcurrent protection (n=1, 2, 3)
Time delay of stage n of phase
9 x.50/51Pn.t_Op 0~3600 0.001 s
voltage control element for phase
10 x.50/51Pn.En_VCE 0 or 1 overcurrent protection (n=1, 2, 3)
0: disable
1: enable
Non_Directional
Direction option of stage n of phase
11 x.50/51Pn.Opt_Dir Forward
Reverse
harmonic blocking for stage n of
phase overcurrent protection (n=1, 2,
12 x.50/51Pn.En_Hm2_Blk 0 or 1
3)
0: disable
1: enable
stage n of phase overcurrent
13 x.50/51Pn.En 0 or 1 protection (n=1, 2, 3)
0: disable
1: enable
14 x.50/51Pn.OutMap 0000~FFFF phase overcurrent protection (n=1, 2,
3)
Pickup setting of stage 4 of phase
15 x.50/51P4.I_Set 0.04~30In 0.001 A
Multiple of the maximum operating
16 x.50/51P4.K_I_Max 10~40 0.001 current to the pickup setting of stage
4 of phase overcurrent protection
Time delay of stage 4 of phase
17 x.50/51P4.t_Op 0~3600 0.001 s

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Time multiplier setting of stage 4 of
18 x.50/51P4.TMS 0.05~3.2 0.001
Minimum delay of stage 4 of phase
19 x.50/51P4.tmin 0~20 0.001 s
The constant K of stage 4 of phase
20 x.50/51P4.K 0~120 0.001
The constant C of stage 4 of phase
21 x.50/51P4.C 0~20 0.001
The exponent alpha of stage 4 of
22 x.50/51P4.Alpha 0.02~5 0.001
DefTime
IECN
IECV
IECE
IECST
IECLT
Option of characteristic curve for
ANSIE
23 x.50/51P4.Opt_Curve stage 4 of phase overcurrent
ANSIV
protection
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
voltage control element for stage 4 of
24 x.50/51P4.En_VCE 0 or 1 phase overcurrent protection
0: disable
1: enable
Non_Directional
Direction option of stage 4 of phase
25 x.50/51P4.Opt_Dir Forward
Reverse
harmonic blocking for stage 4 of
26 x.50/51P4.En_Hm2_Blk 0 or 1 phase overcurrent protection
0: disable
1: enable
stage 4 of phase overcurrent
27 x.50/51P4.En 0 or 1 protection
0: disable
1: enable
28 x.51P4.OutMap 0000~FFFF Tripping logic setting of stage 4 of

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NOTICE!
If the minimum operating time [x.50/51P4.tmin] is set to “0”, the maximum operating
current is valid, and the setting [x.50/51P4.K_I_Max] can be set according to
requirements. If the current is greater than [x.50/51P4.K_I_Max] multiplying
[x.50/51P4.I_Set], the operating time of IDMT becomes flat, i.e. the operating time is
equal to the operating time of IDMT at the point current equal to [x.50/51P4.K_I_Max]
multiplying [x.50/51P4.I_Set]. If [x.50/51P4.tmin] is not set to “0”, then maximum
operating current is not valid and users only can set the setting [x.50/51P4.tmin].
3.15 Earth Fault Protection (50/51G)
3.15.1 Application
During normal operation of power system, there is trace residual current whereas a fault current
flows to earth will result in greater residual current. Therefore residual current is adopted for the
calculation of earth fault protection.
In order to improve the selectivity of earth fault protection in power grid with multiple power
sources, directional element can be selected to control earth fault protection. For application on
transformer circuits, second harmonic also can be selected to block earth fault protection to avoid
the effect of sympathetic current on the protection.
NOTICE!
Earth fault protection includes four stages earth fault element with independent logic, current and
time delay settings. Stage 1, 2, 3 are definite-time characteristic, and stage 4 can be selected as
definite-time or inverse-time characteristic. The inverse-time characteristic is selectable, among
IEC and ANSI/IEEE standard inverse-time characteristics and a user-defined inverse-time curve.
Measured neutral current or calculated residual current can be selected for the calculation of earth
fault protection. Earth fault protection is controlled by direction element and second harmonic
Directional element can select among no direction, forward direction and reverse direction.
3I0>[x.50/51Gn.3I0_Set] Equation 3.15-1
Where:

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3 Operation Theory
3I0 is measured neutral current or calculated residual current, which is selected by user through
the setting [x.50/51Gn.Opt_3I0], n (n=1, 2, 3 or 4).
3.15.2.2 Time Curve
Stage 4 can be selected as definite-time or inverse-time characteristic, and inverse-time operation

time curve is as follows.
Equation 3.15-2
Where:
Iset is residual current setting [x.50/51G4.3I0_Set].
TP is time multiplier setting [x.50/51G4.TMS].
K and C are constants.
α is a constant.
I is actual value of measured current from the neutral CT or calculated residual current.
setting [x.50/51G4.Opt_Curve], and parameters of available characteristics for selection are
x.50/51G4.Opt_Curve Time Characteristic K α C

UserDefine Programmable User-defined
If all available curves do not comply with user application, the user may configure setting
[x.50/51G4.Opt_Curve] to “UserDefine” to customize the inverse-time curve characteristic, and

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3 Operation Theory
3.15.2.3 Direction Element
Calculated residual voltage (3U0) is adopted as polarizing quantity (i.e. polarizing voltage) of
directional element. The current quantity can select the measured neutral current (IN) or the
calculated residual current (3I0).
When a fault occurs at forward direction, the angle polarizing voltage leading fault current is:
Equation 3.15-3
When a fault occurs at reverse direction, the angle is:
Equation 3.15-4
Relay characteristic angle [x.50/51G.DIR.RCA], i.e., the angle of polarizing voltage leading fault
current, is given as the directional setting, and the forward operating region is:
Equation 3.15-5
If VT and CT are connected as shown in Figure 3.15-1, i.e. polarity of CT is at busbar side, and
forward direction points to protected object, then forward and reverse operating regions are shown
in Figure 3.15-2.
VT
Dir
Reverse
Direction
Element
CT
Forward
Protected
Object
Figure 3.15-1 VT and CT connection of direction element

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3 Operation Theory
Forward
IDir (3I0 or IN)
Uref(3U0)
Φsen
Reverse
Figure 3.15-2 Directional characteristic
3.15.2.4 Harmonic Blocking Element
In order to prevent effects of sympathetic inrush current on earth fault protection, harmonics
blocking function can be selected for each stage.
When the percent of second harmonic to fundamental component of zero-sequence current is

greater than setting [x.50/51G.HMB.K_Hm2], harmonic blocking element operates to block earth
fault protection if logic setting [x.50/51Gn.En_Hm2_Blk] (n=1, 2, 3 or 4) is set as “1”. Operation
criterion:
Equation 3.15-6
Where:
I0_2nd is second harmonic of zero sequence current/
I0 is fundamental component of zero sequence current.
When residual current is greater than the setting [x.50/51G.HMB.3I0_Rls_HmBlk], earth fault
protection does not be blocked by harmonic even if the operation criterion is satisfied.
If fundamental component of zero-sequence current is lower than the minimum operating current
(0.4In), harmonic calculation is not carried out and harmonic blocking element does not work.

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50/51G
x.50/51Gn.I3P x.50/51Gn.St
x.50/51Gn.U3P x.50/51Gn.On
x.50/51Gn.I1P x.50/51Gn.Op
x.50/51Gn.En1
x.50/51Gn.En2
x.50/51Gn.Blk
3.15.4 I/O Signals

Table 3.15-2 I/O signals of earth fault protection

Three-phase voltage data input for stage n of earth fault protection at side x of
1 x.50/51Gn.U3P
transformer or reactor. (n=1, 2, 3, 4)
Three-phase current data input for stage n of earth fault protection at side x of
2 x.50/51Gn.I3P
Measured neutral current data input for stage n of earth fault protection at side x of
3 x.50/51Gn.I1P
Input signal 1 of enabling stage n of earth fault protection at side x of transformer or
4 x.50/51Gn.En1
reactor. It is triggered from binary input or programmable logic etc. (n=1, 2, 3, 4)
Input signal 2 of enabling stage n of earth fault protection at side x of transformer or
5 x.50/51Gn.En2
Input signal of blocking stage n of earth fault protection at side x of transformer or
6 x.50/51Gn.Blk
Stage n of earth fault protection at side x of transformer or reactor starts. (n=1, 2, 3,
1 x.50/51Gn.St
4)
Stage n of earth fault protection at side x of transformer or reactor is enabled. (n=1,
2 x.50/51Gn.On
2, 3, 4)
Stage n of earth fault protection at side x of transformer or reactor operates. (n=1,
3 x.50/51Gn.Op
2, 3, 4)
Stage n of earth fault protection at side x of transformer or reactor picks up to
4 x.50/51Gn.TrigDFR
trigger DFR function. (n=1, 2, 3, 4)

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3.15.5 Logic
SET [x.50/51Gn.Opt_Dir]=Forward &

>=1
SIG Direction element (Forward) &
SIG Direction element (Reverse) &
SET [x.50/51Gn.Opt_Dir]=Reverse
SIG x.Alm_VTS >=1

&
SIG x.In_VT
&
>=1
>=1 DIR Release
EN [x.50/51G.DIR.En_VTS_Blk]
SET [x.50/51Gn.Opt_Dir]=Non_Directional
Figure 3.15-3 Logic diagram of direction element (n=1, 2, 3, 4)
EN [x.50/51Gn.En]
&
SIG x.50/51Gn.En1
& x.50/51Gn.On
SIG x.50/51Gn.En2
SIG x.50/51Gn.Blk
SET [x.50/51Gn.Opt_3I0] &
SET 3I0>[x.50/51Gn.3I0_Set]
>=1 &
x.50/51Gn.St
& &
[x.50/51Gn.t_Op] 0ms x.50/51Gn.Op
SET IN>[x.50/51Gn.3I0_Set]
SIG DIR Release
EN [x.50/51Gn.En_Hm2_Blk]
Figure 3.15-4 Logic diagram of earth fault protection (n=1, 2, 3)

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3 Operation Theory
EN [x.50/51G4.En]
&
SIG x.50/51G4.En1
& x.50/51G4.On
SIG x.50/51G4.En2
SIG x.50/51G4.Blk
SET [x.50/51G4.Opt_3I0] &
SET 3I0>[x.50/51G4.3I0_Set]
>=1 &
&
SET IN>[x.50/51G4.3I0_Set]
x.50/51G4.St
SIG DIR Release
& Timer
t
SIG Second harmonic & x.50/51G4.Op
t
EN [x.50/51G4.En_Hm2_Blk]
Figure 3.15-5 Logic diagram of earth fault protection (stage 4)
Where:
3I0 is calculated residual current.
IN is measured neutral current.
3.15.6 Settings
Table 3.15-3 Settings of earth fault protection

Relay characteristic angle of earth
1 x.50/51G.DIR.RCA 0~360 1 deg
fault protection
2 x.50/51G.HMB.K_Hm2 0.05~1.0 0.001
earth fault protection
Current setting of releasing
3 x.50/51G.HMB.3I0_Rls_HmBlk 0.04~150 0.001 A harmonic blocking function of earth
fault protection
earth fault protection be blocked
during VT circuit abnormality
0: disable
4 x.50/51G.DIR.En_VTS_Blk 0 or 1 1: enable
service, directional earth fault is
blocked if the setting is set as “1”.
Directional earth fault protection

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switches to non-directional earth
fault protection if the setting is set as
“0”.
Current setting of stage n of earth
5 x.50/51Gn.3I0_Set 0.04~30In 0.001 A
fault protection (n=1, 2, 3)
Time delay of stage n of earth fault
6 x.50/51Gn.t_Op 0~3600 0.001 s
protection (n=1, 2, 3)
Non_Directional
Direction option of stage n of earth
7 x.50/51Gn.Opt_Dir Forward
Reverse
Option of residual current for the
calculation of stage n of earth fault
8 x.50/51Gn.Opt_3I0 0, 1 1 protection (n=1, 2, 3)
0: Measured residual current
1: Calculated residual current
9 x.50/51Gn.En_Hm2_Blk 0 or 1 earth fault protection (n=1, 2, 3)
0: disable
1: enable
stage n of earth fault protection (n=1,
10 x.50/51Gn.En 0 or 1 2, 3)
0: disable
1: enable
11 x.50/51Gn.OutMap 0000~FFFF
earth fault protection (n=1, 2, 3)
Pickup setting of stage 4 of earth
12 x.50/51G4.3I0_Set 0.04~30In 0.001 A
fault protection
Multiplier of the maximum operating
13 x.50/51G4.K_3I0_Max 10~40 0.001 residual current to the pickup setting
of stage 4 of earth fault protection
Time delay of stage 4 of earth fault
14 x.50/51G4.t_Op 0~3600 0.001 s
protection
15 x.50/51G4.TMS 0.05~3.2 0.001
Minimum delay of stage 4 of earth
16 x.50/51G4.tmin 0~20 0.001 s
fault protection
The constant K of stage 4 of earth
17 x.50/51G4.K 0~120 0.001
fault protection
The constant C of stage 4 of earth
18 x.50/51G4.C 0~20 0.001
fault protection
19 x.50/51G4.Alpha 0.02~5 0.001 The exponent alpha of stage 4 of

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DefTime
IECN
IECV
IECE
IECST
IECLT
ANSIE Option of characteristic curve for
20 x.50/51G4.Opt_Curve
ANSIV stage 4 of earth fault protection
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
Non_Directional
Direction option of stage 4 of earth
21 x.50/51G4.Opt_Dir Forward
fault protection
Reverse
calculation of stage 4 of earth fault
22 x.50/51G4.Opt_3I0 0, 1 1 protection
23 x.50/51G4.En_Hm2_Blk 0 or 1 earth fault protection
0: disable
1: enable
stage 4 of earth fault protection
24 x.50/51G4.En 0 or 1
0: disable
1: enable
25 x.50/51G4.OutMap 0000~FFFF
NOTICE!
If the minimum operating time [x.50/51G4.tmin] is set to “0”, the maximum operating
current is valid, and the setting [x.50/51G4.K_3I0_Max] can be set according to
requirements. If the current is greater than [x.50/51G4.K_3I0_Max] multiplying
[x.50/51G4.3I0_Set], the operating time of IDMT becomes flat, i.e. the operating time is
equal to the operating time of IDMT at the point residual current equal to
[x.50/51G4.K_3I0_Max] multiplying [x.50/51G4.3I0_Set]. If [x.50/51G4.tmin] is not set
to “0”, then maximum operating current is not valid and users only can set the setting

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[x.50/51G4.tmin].
3.16 Negative-Sequence Overcurrent Protection (50/51Q)
3.16.1 Application
Negative-sequence overcurrent protection is applied as the backup protection for generator.

When an unsymmetrical short-circuit fault or a three-phase fault occurs in power system, there is
negative-sequence current generated in stator winding of generator, and negative-sequence
current will produce an opposite rotating magnetic field in gap. Therefore, harmonic currents occur
in rotor, which make some parts with great current density be locally burned and even result in the
retaining ring loosing due to heat to lead to great damage of generator. Negative-sequence
overcurrent protection is equipped to prevent generator from such damage.
NOTICE!
Negative-sequence overcurrent protection includes two stages negative-sequence overcurrent

protection with independent logic, current and time delay settings. Stage 1 is definite-time
characteristic, and stage 2 can be selected as definite-time or inverse-time characteristic. The
inverse-time characteristic is selectable, among IEC and ANSI/IEEE standard inverse-time
characteristics and a user-defined inverse-time curve.
The operation criterion of stage 1 negative-sequence overcurrent protection is:
I2>[x.50/51Q1.I2_Set] Equation 3.16-1
Where:
I2 is negative-sequence current.
3.16.2.2 Time Curve
Stage 2 can be selected as definite-time or inverse-time characteristic, and inverse-time operating

time curve is as follows.
Equation 3.16-2
Where:
Iset is negative-sequence current setting [x.50/51Q2.I2_Set].

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Tp is time multiplier setting [x.50/51Q2.TMS].
α is a constant.
I is actual value of measured negative-sequence current.
setting [x.50/51Q2.Opt_Curve], and parameters of available characteristics for selection are
x.50/51Q2.Opt_Curve Time Characteristic K α C

UserDefine Programmable User-defined
If all available curves do not comply with user application, user may configure setting
[x.50/51Q2.Opt_Curve] to “UserDefine” to customize the inverse-time curve characteristic, and
50/51Q
x.50/51Qn.I3P x.50/51Qn.St
x.50/51Qn.En1 x.50/51Qn.On
x.50/51Qn.En2 x.50/51Qn.Op
x.50/51Qn.Blk
3.16.4 I/O Signals

Table 3.16-2 I/O signals of negative-sequence overcurrent protection

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Three-phase current data input for stage n of negative-sequence overcurrent
1 x.50/51Qn.I3P
protection at side x of transformer. (n=1, 2)
Input signal 1 of enabling stage n of negative-sequence overcurrent protection at
2 x.50/51Qn.En1 side x of transformer. It is triggered from binary input or programmable logic etc.
(n=1, 2)
Input signal 2 of enabling stage n of negative-sequence overcurrent protection at
3 x.50/51Qn.En2 side x of transformer. It is triggered from binary input or programmable logic etc.
(n=1, 2)
Input signal of blocking stage n of negative-sequence overcurrent protection at
4 x.50/51Qn.Blk side x of transformer. It is triggered from binary input or programmable logic etc.
(n=1, 2)
Stage n of negative-sequence overcurrent protection at side x of transformer
1 x.50/51Qn.St
starts. (n=1, 2)
Stage n of negative-sequence overcurrent protection at side x of transformer is
2 x.50/51Qn.On
enabled. (n=1, 2)
3 x.50/51Qn.Op
operates. (n=1, 2)
Stage n of negative-sequence overcurrent protection at side x of transformer picks
4 x.50/51Qn.TrigDFR
up to trigger DFR function. (n=1, 2)
3.16.5 Logic
EN [x.50/51Q1.En]
&
SIG x.50/51Q1.En1
& x.50/51Q1.On
SIG x.50/51Q1.En2
SIG x.50/51Q1.Blk
&
SIG x.50/51Q1.I3P x.50/51Q1.St
[x.50/51Q1.t_Op] 0ms x.50/51Q1.Op

SET [x.50/51Q1.I2_Set]
EN [x.50/51Q2.En]
&
SIG x.50/51Q2.En1
& x.50/51Q2.On
SIG x.50/51Q2.En2 Timer
t
x.50/51Q2.Op
SIG x.50/51Q2.Blk t
&
SIG x.50/51Q2.I3P x.50/51Q2.St
SET [x.50/51Q2.I2_Set]
Figure 3.16-1 Logic diagram of negative-sequence overcurrent protection

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3.16.6 Settings
Table 3.16-3 Settings of negative-sequence overcurrent protection

Current setting of stage 1 of negative-sequence
1 x.50/51Q1.I2_Set 0.04~30In 0.001 A
Time delay of stage 1 of negative-sequence
2 x.50/51Q1.t_Op 0~3600 0.001 s
Logic setting of enabling/disabling stage 1 of
negative-sequence overcurrent protection
3 x.50/51Q1.En 0 or 1
0: disable
1: enable
4 x.50/51Q1.OutMap 0000~FFFF
Pickup setting of stage 2 of negative-sequence
5 x.50/51Q2.I2_Set 0.04~30In 0.001 A
negative-sequence current to the pickup setting
6 x.50/51Q2.K_I2_Max 10~40 0.001
of stage 2 of negative-sequence overcurrent
protection
7 x.50/51Q2.t_Op 0~3600 0.001 s
Time multiplier setting of stage 2 of ground
8 x.50/51Q2.TMS 0.05~3.2 0.001
Minimum delay of stage 2 of negative-sequence
9 x.50/51Q2.tmin 0~20 0.001 s
The constant K of stage 2 of negative-sequence
10 x.50/51Q2.K 0~120 0.001
-sequence overcurrent protection
The constant C of stage 2 of negative-sequence
11 x.50/51Q2.C 0~20 0.001
12 x.50/51Q2.Alpha 0.02~5 0.001
DefTime
IECN
IECV
IECE
IECST
IECLT Option of characteristic curve for stage 2 of
13 x.50/51Q2.Opt_Curve
ANSIE negative-sequence overcurrent protection
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV

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ANSILT
UserDefine
14 x.50/51Q2.En 0 or 1
0: disable
1: enable
NOTICE!
If the minimum operating time [x.50/51Q2.tmin] is set to “0”, the maximum operating
current is valid, and the setting [x.50/51Q2.K_I2_Max] can be set according to
requirements. If the current is greater than [x.50/51Q2.K_I2_Max] multiplying
[x.50/51Q2.I_Set], the operating time of IDMT becomes flat, i.e. the operating time is
equal to the operating time of IDMT at the point negative-sequence current equal to
[x.50/51Q2.K_I2_Max] multiplying [x.50/51Q2.I2_Set]. If [x.51Q2.tmin] is not set to “0”,
then maximum operating current is not valid and users only can set the setting
[x.50/51Q2.tmin].
3.17 Phase Overvoltage Protection (59P)
3.17.1 Application
In the power system, when users operating circuit breakers or a fault occurring, system
parameters will change, which can cause the power system electromagnetic energy converting
and transferring and overvoltage will appears in the system. Overvoltage protection is equipped
for the protection of electric equipment and its insulation.
NOTICE!

Phase overvoltage protection includes two stages phase overvoltage element with independent
logic, voltage and time delay settings. Stage 1 is definite-time characteristic, and stage 2 can be
selected as definite-time or inverse-time characteristic. The inverse-time characteristic is
selectable among IEC and ANSI/IEEE standard inverse-time characteristics and a user-defined
inverse-time curve.
Phase overvoltage protection can select phase voltage or phase-to-phase voltage for protection
calculation.

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 Phase voltage criterion
Two operation criteria of definite-time overvoltage protection are as follows, which of them is
selected determined by the logic setting [x.59Pn.Opt_1P/3P].
Equation 3.17-1
Equation 3.17-2
Where:
UΦ_max is the maximum value of three phase voltages.
When [x.59Pn.Opt_1P/3P] is set as “0”, “1-out-of-3” logic (i.e., Equation 3.17-1) is selected as
operation criterion
operation criterion.
 Phase-to-phase voltage criterion
Two operation criteria of definite-time overvoltage protection are as follows, which of them is
selected determined by the logic setting [x.59Pn.Opt_1P/3P].
Equation 3.17-3
Equation 3.17-4
Where:
UΦΦ_max is the maximum value of phase-to-phase value of one side.
3.17.2.2 Time Curve
Stage 2 of phase overvoltage protection can be selected as definite-time or inverse-time

characteristic, and inverse-time operating time curve is as follows.

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Equation 3.17-5
Where:
Uset is voltage setting [x.59P2.U_Set].
Tp is time multiplier setting [x.59P2.TMS].
α is a constant.
U is actual measured phase voltage (or phase-to-phase voltage) value.
setting [x.59P2.Opt_Curve], and parameters of available characteristics for selection are shown in
the following table.
x.59P2.Opt_Curve Time Characteristic K α C

[x.59P2.Opt_Curve] at “UserDefine” to customize the inverse-time curve characteristic, and

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59P
x.59Pn.U3P x.59Pn.St
x.59Pn.En1 x.59Pn.On
x.59Pn.En2 x.59Pn.Op
x.59Pn.Blk
3.17.4 I/O Signals

Table 3.17-2 I/O signals of phase overvoltage protection

Three-phase voltage data input for stage n of phase overvoltage protection at side
1 x.59Pn.U3P
x of transformer. (n=1, 2)
Input signal 1 of enabling stage n of phase overvoltage protection at side x of
2 x.59Pn.En1
transformer. It is triggered from binary input or programmable logic etc. (n=1, 2)
3 x.59Pn.En2
Input signal of blocking stage n of phase overvoltage protection at side x of
4 x.59Pn.Blk
1 x.59Pn.St Stage n of phase overvoltage protection at side x of transformer starts. (n=1, 2)
Stage n of phase overvoltage protection at side x of transformer is enabled. (n=1,
2 x.59Pn.On
2)
3 x.59Pn.Op Stage n of phase overvoltage protection at side x of transformer operates. (n=1, 2)
Stage n of phase overvoltage protection at side x of transformer picks up to trigger
4 x.59Pn.TrigDFR
DFR function. (n=1, 2)

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3.17.5 Logic
EN [x.59P1.En]
&
SIG x.59P1.En1
& x.59P1.On
SIG x.59P1.En2
SIG x.59P1.Blk
&
SIG x.59P1.U3P x.59P1.St
[x.59P1.t_Op] 0ms x.59P1.Op

SET [x.59P1.U_Set]
EN [x.59P2.En]
&
SIG x.59P2.En1
& x.59P2.On
SIG x.59P2.En2 Timer
t
x.59P2.Op
SIG x.59P2.Blk t
&
SIG x.59P2.U3P x.59P2.St
SET [x.59P2.U_Set]
Figure 3.17-1 Logic diagram of phase overvoltage protection
3.17.6 Settings
Table 3.17-3 Settings of phase overvoltage protection

Voltage setting of stage 1 of phase overvoltage
1 x.59P1.U_Set 2~200 0.001 V
protection
Time delay of stage 1 of phase overvoltage
2 x.59P1.t_Op 0~3600 0.001 s
protection
Option of phase voltage or phase-to-phase
voltage used for protection calculation of stage 1
3 x.59P1.Opt_Up/Upp 0, 1 1 of phase overvoltage protection
0: phase voltage
Option of “1-out-of-3” logic or “3-out-of-3” logic
used for operation criterion of stage 1 of phase
4 x.59P1.Opt_1P/3P 0, 1 1 overvoltage protection
0: 1-out-of-3
1: 3-out-of-3
phase overvoltage protection
5 x.59P1.En 0 or 1 1
0: disable
1: enable

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Tripping logic setting of stage 1 of phase
6 x.59P1.OutMap 0000~FFFF
overvoltage protection
Pickup setting of stage 2 of phase overvoltage
7 x.59P2.U_Set 2~200 0.001 V
protection
Multiplier of the maximum operating voltage to
8 x.59P2.K_U_Max 1~10 0.001 the pickup setting of stage 2 of phase
9 x.59P2.t_Op 0~3600 0.001 s
protection
10 x.59P2.Opt_Up/Upp 0~1 1 of phase overvoltage protection
0: phase voltage
11 x.59P2.Opt_1P/3P 0~1 1 overvoltage protection
0: 1-out-of-3
1: 3-out-of-3
Time multiplier setting of stage 2 of phase
12 x.59P2.TMS 0.05~3.2 0.001
Minimum delay of stage 2 of phase overvoltage
13 x.59P2.tmin 0~20s 0.001 s
protection
The constant K of stage 2 of phase overvoltage
14 x.59P2.K 0~120 0.001
protection
The constant C stage 2 of phase overvoltage
15 x.59P2.C 0~20 0.001
protection
The exponent alpha stage 2 of phase
16 x.59P2.Alpha 0.02~5 0.001
DefTime
IECN
IECV
IECE
IECST
IECLT
ANSIE Option of characteristic curve for stage 2 of
17 x.59P2.Opt_Curve
ANSIV overvoltage protection
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine

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18 x.59P2.En 0 or 1
0: disable
1: enable
NOTICE!
If the minimum operating time [x.59P2.tmin] is set to “0”, the maximum operating
voltage is valid, and the setting [x.59P2.K_U_Max] can be set according to
requirements. If the voltage is greater than [x.59P2.K_U_Max] multiplying
[x.59P2.U_Set], the operating time of IDMT becomes flat, i.e. the operating time is
equal to the operating time of IDMT at the point voltage equal to [x.59P2.K_U_Max]
multiplying [x.59P2.U_Set]. If [x.59P2.tmin] is not set to “0”, then maximum operating
voltage is not valid and users only can set the setting [x.59P2.tmin].
3.18 Residual Overvoltage Protection (59G)
3.18.1 Application
A single phase earth fault happening to ungrounded system or Peterson coil grounded system will
result in residual overvoltage, so residual overvoltage protection is equipped to prevent protected
equipment being damaged by residual overvoltage in this condition.
NOTICE!

Residual overvoltage protection includes two stages residual overvoltage element with
independent logic, voltage and time delay settings. Stage 1 is definite-time characteristic, and
stage 2 can be selected as definite-time or inverse-time characteristic. The inverse-time
characteristic is selectable among IEC and ANSI/IEEE standard inverse-time characteristics and a
user-defined inverse-time curve.
3U0>[x.59Gn.3U0_Set] Equation 3.18-1
Where:
3U0 is measured residual voltage.

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3.18.2.2 Time Curve
Stage 2 of residual overvoltage protection can be selected as definite-time or inverse-time

characteristic, and inverse-time operating time curve is as follows.
Equation 3.18-2
Where:
Uset is residual voltage setting [x.59G2.3U0_Set].
Tp is time setting [x.59G2.TMS].
α is a constant.
U is actual measured residual voltage.
setting [x.59G2.Opt_Curve], and parameters of available characteristics for selection are shown in
the following table.
x.59G2.Opt_Curve Time Characteristic K α C

[x.59G2.Opt_Curve] to “UserDefine” to customize the inverse-time curve characteristic, and

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59G
x.59Gn.U3P x.59Gn.St
x.59Gn.U1P x.59Gn.On
x.59Gn.En1 x.59Gn.Op
x.59Gn.En2
x.59Gn.Blk
3.18.4 I/O Signals

Table 3.18-2 I/O signals of residual overvoltage protection

Three-phase voltage data input for stage n of residual overvoltage protection at
1 x.59Gn.U3P
side x of transformer. (n=1, 2)
Measured residual voltage data input for stage n of residual overvoltage protection
2 x.59Gn.U1P
at side x of transformer. (n=1, 2)
Input signal 1 of enabling stage n of residual overvoltage protection at side x of
3 x.59Gn.En1
4 x.59Gn.En2
Input signal of blocking stage n of residual overvoltage protection at side x of
5 x.59Gn.Blk
1 x.59Gn.St Stage 1 of residual overvoltage protection at side x of transformer starts. (n=1, 2)
Stage 1 of residual overvoltage protection at side x of transformer is enabled. (n=1,
2 x.59Gn.On
2)
Stage 1 of residual overvoltage protection at side x of transformer operates. (n=1,
3 x.59Gn.Op
2)
Stage 1 of residual overvoltage protection at side x of transformer picks up to
4 x.59Gn.TrigDFR
trigger DFR function. (n=1, 2)

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3.18.5 Logic
EN [x.59G1.En]
&
SIG x.59G1.En1
& x.59G1.On
SIG x.59G1.En2
SIG x.59G1.Blk
SIG x.59G1.U3P >=1 &

x.59Gn.St
SIG x.59G1.U1P
[x.59G1.t_Op] 0ms x.59G1.Op
SET [x.59G1.U_Set]
EN [x.59G2.En]
&
SIG x.59G2.En1
& x.59G2.On
SIG x.59G2.En2
Timer
SIG x.59G2.Blk t
x.59G2.Op
t
SIG x.59G2.U3P >=1 &
x.59G2.St
SIG x.59G2.U1P
SET [x.59G2.U_Set]
Figure 3.18-1 Logic diagram of residual overvoltage protection
3.18.6 Settings
Table 3.18-3 Settings of residual overvoltage protection

Voltage setting of stage 1 of residual
1 x.59G1.3U0_Set 2~200 0.001 V
Time delay of stage 1 of residual overvoltage
2 x.59G1.t_Op 0~3600 0.001 s
protection
residual overvoltage protection
3 x.59G1.En 0 or 1
0: disable
1: enable
Residual voltage option for the calculation of
stage 1 of residual overvoltage protection
4 x.59G1.Opt_3U0 0, 1 1
0: Measured residual voltage
1: Calculated residual voltage
Tripping logic setting of stage 1 of residual
5 x.59G1.OutMap 0000~FFFF
Voltage setting of stage 2 of residual
6 x.59G2.3U0_Set 2~200 0.001 V

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Multiplier of the maximum operating residual
7 x.59G2.K_3U0_Max 1~2 0.001 voltage to the pickup setting of stage 2 of
8 x.59G2.t_Op 0~3600 0.001 s
protection
Minimum delay of stage 2 of residual
9 x.59G2.tmin 0~20s 0.001 s
Time multiplier setting of stage 2 of residual
10 x.59G2.TMS 0.05~3.2 0.001
The constant K of stage 2 of residual
11 x.59G2.K 0.0~120 0.001
The constant C stage 2 of residual overvoltage
12 x.59G2.C 0.0~20 0.001
protection
The exponent alpha stage 2 of residual
13 x.59G2.Alpha 0.02~5 0.001
DefTime
IECN
IECV
IECE
IECST
IECLT
14 x.59G2.Opt_Curve
ANSIV residual overvoltage protection
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
15 x.59G2.En 0 or 1
0: disable
1: enable
16 x.59G2.Opt_3U0 0, 1 1
NOTICE!
If the minimum operating time [x.59G2.tmin] is set to “0”, the maximum operating
voltage is valid, and the setting [x.59G2.K_3U0_Max] can be set according to

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3 Operation Theory
requirements. If the residual voltage is greater than [x.59G2.K_3U0_Max] multiplying

[x.59G2.3U0_Set], the operating time of IDMT becomes flat, i.e. the operating time is
equal to the operating time of IDMT at the point residual voltage equal to
[x.59G2.K_3U0_Max] multiplying [x.59G2.3U0_Set]. If [x.59G2.tmin] is not set to “0”,
then maximum operating voltage is not valid and users only can set the setting
[x.59G2.tmin].
3.19 Undervoltage Protection (27P)
3.19.1 Application
The increase of reactive power load leads to voltage decreasing, and voltage quality cannot be
satisfied only through AVR and OLTC. In this situation, undervoltage protection should operate to
shed part of loads to make voltage recovery to the normal level. Undervoltage protection includes
four stages definite-time undervoltage element with independent voltage and time delay settings,
and they can be blocked by the change rate of voltage.
NOTICE!
Three-phase undervoltage caused by the lack of system reactive power is almost symmetrical and
does not change suddenly, so the undervoltage protection adopts the positive-sequence voltage
for the protection calculation. If negative-sequence voltage is greater than 0.15Un or
positive-sequence voltage changes suddenly, the undervoltage protection is blocked.
Undervoltage load shedding protection has the unique capability of fault distinguishing, and its
operating time does not need to coordinate with that of other protections, so undervoltage
protection can operate quickly when system voltage is low.
When a short circuit occurs in the power system, bus voltage will decreases suddenly and
therefore undervoltage protection should be blocked simultaneously. After other protections
operate to clear the fault, the voltage at the relay location recovers quickly. If the voltage cannot
recover to the normal operation value, but greater than the value of setting [x.27P.U_Recov],
blocking of undervoltage protection should be released at once, and the protection can operate to
shed corresponding loads to make voltage recovery. (When system voltage collapses, disappears
or decreases, voltage recovery is the progress that the system voltage recovers to rated voltage.)
In order to prevent undesired operation of undervoltage protection caused by abnormality

contestations such as load back feed, higher harmonics, voltage circuit failure etc., following
blocking criteria are equipped.
1. Undervoltage blocking
If positive-sequence voltage is lower than 0.15Un, undervoltage protection is blocked.

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2. Negative-sequence blocking
If negative-sequence voltage is greater than 0.15Un, undervoltage protection is blocked.
3. Change rate of voltage blocking
If the change rate of voltage (du/dt) is greater than the setting [x.27P.du/dt_Blk], undervoltage
protection is blocked and the blocking is not released until the system voltage greater than the
recovery voltage and above (setting [x.27P.U_Recov])
When any one criterion is met, undervoltage protection is blocked.
27P
x.27P.U3P x.27P.UVn.St
x.27P.En1 x.27P.UVn.On
x.27P.En2 x.27P.UVn.Op
x.27P.Blk x.27P.Alm_Unrecov
3.19.4 I/O Signals

Table 3.19-1 I/O signals of undervoltage protection

Three-phase voltage data input for undervoltage protection at side x of
1 x.27P.U3P
transformer.
Input signal 1 of enabling undervoltage protection at side x of transformer. It is
2 x.27P.En1
3 x.27P.En2
Input signal of blocking undervoltage protection at side x of transformer. It is
4 x.27P.Blk
1 x.27P.UVn.St Stage n of undervoltage protection at side x of transformer starts. (n=1, 2, 3, 4)
Stage n of undervoltage protection at side x of transformer is enabled. (n=1, 2, 3,
2 x.27P.UVn.On
4)
3 x.27P.UVn.Op Stage n of undervoltage protection at side x of transformer operates. (n=1, 2, 3, 4)
The voltage at side x of transformer does not recover to normal level.
4 x.27P.Alm_Unrecov (If the voltage does not recover to the value greater than the setting
[x.27.U_Recov] after the time delay [x.27.t_Recov], alarm signal will be issued.)
Stage n of undervoltage protection at side x of transformer picks up to trigger DFR
5 x.27P.UVn.TrigDFR
function. (n=1, 2, 3, 4)

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3.19.5 Logic
SIG x.27P.En1
&
SIG x.27P.En2 Enable 27P
SIG x.27P.Blk
SIG x.Alm_VTS
>=1
SIG U1<0.15Un
SIG U2>0.15Un
SET -du/dt>[x.27P.du/dt_Blk] & >=1

Block 27P
EN [x.27P.En_du/dt_Blk]
SIG x.In_VT
SIG Enable 27P &
SIG Block 27P

&
SET U1<[x.27P.UV1.U_Set] x.27P.UV1.St
EN [x.27P.UV1.En] [x.27P.UV1.t_Op] 0ms x.27P.UV1.Op

&
x.27P.UV1.On
&

&
x.27P.UV2.On
&

&
x.27P.UV3.On
&

&
x.27P.UV4.On
Figure 3.19-1 Logic diagram of undervoltage protection
Where:
U1 is the positive sequence voltage.

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3 Operation Theory
“x.In_VT” is the input signal indicating that VT at x side of transformer is in service. The signal can
be configured as a binary input according to user requirements, and if the binary input is not
configured, its default value is 1.
3.19.6 Settings
Table 3.19-2 Settings of undervoltage protection

du/dt blocking setting of undervoltage
1 x.27P.du/dt_Blk 0~100 0.001 V/s
protection
2 x.27P.U_Recov 10~100 0.001 V Lowest voltage threshold of fault recovery
Time setting of fault recovery
It should be greater than the operating time of
3 x.27P.t_Recov 0~20 0.001 s backup protection generally. For example, if the
longest operating time of backup protection is 4s,
the setting [x.27.t_Recov] can be set to “4.5s~5s”.
Voltage setting of stage 1 of undervoltage
4 x.27P.UV1.U_Set 10~100 0.001 V
protection
Time delay of stage 1 of undervoltage
5 x.27P.UV1.t_Op 0.05~100 0.001 s
protection
Logic setting of enabling/disabling du/dt
blocking function for stage 1 of undervoltage
6 x.27P.UV1.En_du/dt_Blk 0 or 1 protection
0: disable
1: enable
undervoltage protection
7 x.27P.UV1.En 0 or 1
0: disable
1: enable
Tripping logic setting of stage 1 of undervoltage
8 x.27P.UV1.OutMap 0000~FFFF
protection
9 x.27P.UV2.U_Set 0~100 0.001 V
protection
10 x.27P.UV2.t_Op 0.05~100 0.001 s
protection
11 x.27P.UV2.En_du/dt_Blk 0 or 1 protection.
0: disable
1: enable
undervoltage protection.
12 x.27P.UV2.En 0 or 1
0: disable
1: enable

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protection
14 x.27P.UV3.U_Set 0~100 0.001 V
protection
15 x.27P.UV3.t_Op 0.05~100 0.001 s
protection
16 x.27P.UV3.En_du/dt_Blk 0 or 1 1 protection
0: disable
1: enable
Logic setting of enabling stage 3 of
17 x.27P.UV3.En 0 or 1 1
0: disable
1: enable
protection
19 x.27P.UV4.U_Set 0~100 0.001 V
protection
20 x.27P.UV4.t_Op 0.05~100 0.001 s
protection
21 x.27P.UV4.En 0 or 1 1
0: disable
1: enable
0: disable
1: enable
protection
3.20 Thermal Overload Protection (49)
3.20.1 Application
During overload operation of a power transformer, great current results in greater heat to lead
temperature of transformer increase and if the temperature reaches too high values, the
equipment might be damaged. The insulation within the transformer will have forced ageing. As a
consequence of this, the risk of internal phase-to-phase or phase-to-ground faults will increase.
High temperature will degrade the quality of the transformer oil.

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Thermal overload protection estimates the internal heat content of the transformer (temperature)
continuously. This estimation is made by using a thermal model of the transformer with two time
constants, which is based on current measurement.
NOTICE!
The device provide two methods to fulfill thermal overload protection, one is to calculate thermal
accumulation according the actual measured current, and the other is to calculate temperature
difference between windings temperature and oil temperature to gain winding temperature by oil
temperature acquired by external transducer (PT100).
1. Method 1
Two stages overload protection are available, one stage for alarm purpose and the other stage for
trip purpose. When the temperature increases to the alarm value, thermal overload protection
issues alarm signal to remind the operator for attention, and if the temperature continues to
increase to the trip value, thermal overload protection issues trip command.
There are maximum three thermal overload protection elements equipped at each side of
transformer, and it is recommended to be equipped at the side without OLTC. Thermal overload
protection adopts IEC 60255-8 as thermal time characteristic, and fundamental current or 1st to 7th
harmonic current is used for protection calculation.
The device provides a thermal overload model which is based on the IEC60255-8 standard.
t Refer to IEC60255-8
Ip
P=—
IB
P = 0.0
P = 0.6
P = 0.8
P = 0.9
kIB I
Figure 3.20-1 Characteristic curve of thermal overload protection
There are two types of thermal time characteristic, cold start characteristic and hot start
characteristic. The thermal overload formulas are shown as below.
1. Cold start characteristic

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3 Operation Theory
2
I eq
t    ln Equation 3.20-1
2
I eq  (k  I B ) 2
2. Hot start characteristic
2
I eq  I 2p
t    ln Equation 3.20-2
2
I eq  (k  I B ) 2
Where:
t is the theoretical operate time, following application of the overload current.
τ is the heating thermal time constant of the protected device, i.e. [x.49.Tau].
Ieq is the equivalent heating current, i.e. actual measured current.
IP is the steady-state load current prior to the overload for a duration which would result in
constant thermal level (duration is greater than several time constant τ), which is memory current.
For cold start characteristic, it is zero.
ln is natural logarithm
IB is the base current, i.e. [x.49.Ib_Set].
k is thermal overload coefficient, i.e. [x.49.K_Alm] or [x.49.K_Trp].
The hot start characteristic is adopted in the device. The calculation is carried out at zero of IP, so
users need not to set the value of IP.
Tripping outputs of the protection is controlled by current, even if the thermal accumulation value is
greater than the setting for tripping, the protection drops off instantaneously when current
disappears. Alarm outputs of the protection is not controlled by current, and only if the thermal
accumulation value is greater than the setting for alarm, alarm output contacts, which can be
connected to block the auto-reclosure, will operate.
2. Method 2
The actual windings temperature can be gained by oil temperature, which is measured by external
transducer (PT100), plus temperature difference between windings temperature and oil
temperature, i.e.,
T_windings (windings temperature) = T_oil (oil temperature) + T_Diff (temperature difference

between windings and oil)
The temperature difference can be calculated according to the current, and is changed with the
current. When the current is increased from 0 to I, the temperature accumulation complies with the
following equation.

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Finally, stable temperature difference:
Where:
I is the measured current
α is cooling factor, taking 1.6 or 2
t is time
Tau is time constant
According to the calculated windings temperature, the user can compare it with user-defined
temperature value, and can set stage and time delay to trip or alarm by user-defined logic.
49
x.49.I3P x.49.St
x.49.En1 x.49.On
x.49.En2 x.49.Op
x.49.Blk x.49.Alm
3.20.4 I/O Signals

Table 3.20-1 I/O signals of thermal overload protection

Three-phase current data input for thermal overload protection at side x of
1 x.49.I3P
transformer or reactor.
Clear command of thermal accumulation value for thermal overload protection at
2 x.49.Clr
side x of transformer or reactor.
Input signal 1 of enabling thermal overload protection at side x of transformer or
3 x.49.En1
reactor. It is triggered from binary input or programmable logic etc.
4 x.49.En2
Input signal of blocking thermal overload protection at side x of transformer or
5 x.49.Blk
1 x.49.St Thermal overload protection at side x of transformer or reactor starts.
2 x.49.On Thermal overload protection at side x of transformer or reactor is enabled.
3 x.49.Op Thermal overload protection at side x of transformer or reactor operates to trip.

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4 x.49.Alm Thermal overload protection at side x of transformer or reactor operates to alarm.
Thermal overload protection at side x of transformer or reactor picks up to trigger
5 x.49.TrigDFR
DFR function.
The calculated temperature difference of phase-A between winding temperature
6 x.49.T_Diff_A
and oil temperature.
The calculated temperature difference of phase-B between winding temperature
7 x.49.T_Diff_B
The calculated temperature difference of phase-C between winding temperature
8 x.49.T_Diff_C
3.20.5 Logic
>=1
&
SIG x.49.En1
& x.49.On
SIG x.49.En2
SIG x.49.Blk
&
SIG x.49.I3P x.49.St
& Timer
SET [x.49.Ib_Set] t
x.49.Alm
t
EN [x.49.En_Alm]
& Timer
t
x.49.Op
t
EN [x.49.En_Trp]
SIG x.49.Clr
Figure 3.20-2 Logic diagram of thermal overload protection (method 1)
3.20.6 Settings
Table 3.20-2 Settings of thermal overload protection

Tripping setting of thermal capacity for thermal
1 x.49.K_Trp 1~3 0.001
overload protection
Alarm setting of thermal capacity for thermal
2 x.49.K_Alm 1~3 0.001
overload protection
Base current setting of thermal overload
3 x.49.Ib_Set 0.04~30In 0.001 A
protection
4 x.49.Tau 0.1~100 0.001 min Thermal time constant
The convertor coefficient from the current to the
5 x.49.K_T_Diff 0~200 0.001
temperature
6 x.49.Alpha_Cold 1~2 0.001 The cooling mode of transformer, usually,

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natural cooling: 1.6
forced cooling: 2
Logic setting of enabling/disabling thermal
overload protection operate to trip
7 x.49.En_Trp 0 or 1
0: disable
1: enable
overload protection operate to alarm
8 x.49.En_Alm 0 or 1
0: disable
1: enable
Tripping logic setting of thermal overload
9 x.49.OutMap 0000~FFFF
protection
3.21 Breaker Failure Protection (50BF)
3.21.1 Application
Breaker failure protection is applied to inter-trip each side of transformer when initiation signals of
breaker failure protection from busbar protection or other device are received. When the binary
input of external tripping is energized and current element picks up, a trip command will be issued
with a time delay to trip circuit breakers at each side of transformer. PCS-978 can provide two the
same breaker failure protection modules for two branches application at each side. However, the
second breaker failure protection module is disabled by default, which can be enabled by
PCS-Explorer.
NOTICE!
The device provides four kinds of current criteria including phase current criterion, zero-sequence
current criterion, negative-sequence current criterion and DPFC current criterion. If any current
criterion is satisfied, current element of breaker failure protection picks up.
1. Phase current criterion
IΦ_max>[x.50BF.I_Set] Equation 3.21-1
Where:
IΦ_max is the maximum value of three phase-current of some side.
2. Zero-sequence current criterion

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3I0>[x.50BF.3I0_Set] Equation 3.21-2
Where:
3I0 is three times calculated zero-sequence current of some side.
3. Negative-sequence current criterion
I2>[x.50BF.I2_Set] Equation 3.21-3
Where:
I2 is negative-sequence current of some side.
4. DPFC current criteria
ΔI>1.25×ΔIt+Ith Equation 3.21-4
Where:
ΔIt is the floating threshold value which will arise automatically and gradually according to
increasing of the output of deviation component. In order to ensure the threshold current is slightly
greater than the unbalance current, multiple 1.25 of the deviation component is reasonable.
ΔI is the half-wave calculated of phase-to-phase current.
Ith is the fixed threshold of 0.1p.u. and does not need to be set on site.
50BF
x.50BF.I3P x.50BF.St
x.50BF.Init x.50BF.On_t1
x.50BF.En1 x.50BF.On_t2
x.50BF.En2 x.50BF.Op_t1
x.50BF.Blk x.50BF.Op_t2
x.50BF.Alm_Init
x.50BF.Alm_Curr
3.21.4 I/O Signals

Table 3.21-1 I/O signals of breaker failure protection

1 x.50BF.I3P Three-phase current data input for breaker failure protection at side x of

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transformer.
2 x.50BF.Init Input signal of initiating breaker failure protection at side x of transformer.
Input signal of normally open auxiliary contact of circuit breaker at side x of
3 x.52b
transformer.
Input signal 1 of enabling breaker failure protection at side x of transformer. It is
4 x.50BF.En1
5 x.50BF.En2
Input signal of blocking breaker failure protection at side x of transformer. It is
6 x.50BF.Blk
1 x.50BF.St Breaker failure protection at side x of transformer starts.
2 x.50BF.On_t1 Breaker failure protection with the time delay 1 at side x of transformer is enabled.
3 x.50BF.On_t2 Breaker failure protection with the time delay 2 at side x of transformer is enabled.
4 x.50BF.Op_t1 Breaker failure protection at side x of transformer operates with the time delay 1.
5 x.50BF.Op_t2 Breaker failure protection at side x of transformer operates with the time delay 2.
The duration of input signal of initiating breaker failure protection at side x of
6 x.50BF.Alm_Init
transformer is over 3s.
The current criterion of breaker failure protection at side x of transformer is
7 x.50BF.Alm_Curr
satisfied for over 3s.
8 x.50BF.TrigDFR Breaker failure protection at side x of transformer picks up to trigger DFR function.

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3.21.5 Logic
SIG x.50BF.Init
&
EN [x.50BF.En_CB_Ctrl] &
SIG x.50BF.FD
SIG x.52b
SIG IΦ_max>0.06In
SET [x.50BF.En_Ip] & >=1

>=1 &
SET IΦ_max>[x.50BF.Ip_Set] >=1
EN [x.50BF.En_3I0] &
SET 3I0>[x.50BF.3I0_Set]
EN [x.50BF.En_I2] &
>=1
SET I2>[x.50BF.I2_Set]
EN [x.50BF.En_DPFC] &
SIG ΔI>1.25ΔIt+Ith
SIG x.50BF.Blk [x.50BF.t1_Op] 0ms x.50BF.Op_t1

& &
SIG x.50BF.En1 x.50BF.St
&
SIG x.50BF.En2
x.50BF.On_t1
&
EN [x.50BF.En_t1]
x.50BF.St
&
[x.50BF.t2_Op] 0ms x.50BF.Op_t2
x.50BF.On_t2
EN [x.50BF.En_t2]
Figure 3.21-1 Logic diagram of breaker failure protection
Where:
In is rated secondary current of CT.
IΦ_max is the maximum value of three phase-current of x side.
“x.50BF.FD” means that the fault detector of breaker failure protection of x side picks up.
3.21.6 Settings
Table 3.21-2 Settings of breaker failure protection

1 x.50BF.Ip_Set 0.04~30In 0.001 A Current setting of phase current criterion.
2 x.50BF.3I0_Set 0.04~30In 0.001 A Current setting of residual current criterion.
3 x.50BF.I2_Set 0.04~30In 0.001 A Current setting of negative-sequence current

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criterion.
Logic setting of enabling/disabling phase current
criterion to control breaker failure protection
4 x.50BF.En_Ip 0 or 1
0: disable
1: enable
negative-sequence current criterion to control
5 x.50BF.En_I2 0 or 1 breaker failure protection.
0: disable
1: enable
Logic setting of enabling/disabling DPFC current
criterion to control breaker failure protection.
6 x.50BF.En_DPFC 0 or 1
0: disable
1: enable
residual-sequence current criterion to control
7 x.50BF.En_3I0 0 or 1 breaker failure protection.
0: disable
1: enable
8 x.50BF.t1_Op 0~20 0.001 s Time delay 1 of breaker failure protection.
To enable the criterion of CB position for breaker
failure protection.
9 x. 50BF.En_CB_Ctrl 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling time delay 1
of breaker failure protection.
10 x.50BF.En_t1 0 or 1
0: disable
1: enable
Tripping logic setting of time delay 1 of breaker
11 x.50BF.OutMap_t1 0000~FFFF
failure protection.
13 x.50BF.En_t2 0 or 1
0: disable
1: enable
failure protection
3.22 Pole Disagreement Protection (62PD)
3.22.1 Application
With voltage level involved, the switching equipment usually consists of single pole devices that

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are not mechanically linked, with each pole having an independent operating mechanism. With
such an arrangement, the possibility exists that one pole may not operate coincidentally with the
other poles, thus creating an undesirable imbalance in system voltages or, in case the switching
equipment were called upon to clear a fault, might fail to remove the faulted source from service.
So that if a pole disagreement fault is detected, after a certain delay, the device will initiate a trip
command to trip all poles of the switching equipment.
NOTICE!
There are two current control elements for pole disagreement protection: residual current element
and negative-sequence current element which are configurable by logic settings and are “OR”
relation to release pole disagreement protection. The input signal of pole disagreement position,
“62PD.In_PD_CB”, is used to initiate pole disagreement protection.
62PD
x.62PD.I3P x.62PD.St
x.62PD.In_PD_CB x.62PD.On
x.62PD.En1 x.62PD.Op
x.62PD.En2 x.62PD.Alm
x.62PD.Blk
3.22.4 I/O Signals

Table 3.22-1 I/O signals of pole disagreement protection

Three-phase current data input for pole disagreement protection at side x of
1 x.62PD.I3P
transformer.
2 x.62PD.In_PD_CB Input signal of indicating pole disagreement state at side x of transformer.
Input signal 1 of enabling pole disagreement protection at side x of transformer. It
3 x.62PD.En1
Input signal 2 of enabling pole disagreement protection at side x of transformer. It
4 x.62PD.En2
Input signal of blocking pole disagreement protection at side x of transformer. It is
5 x.62PD.Blk
1 x.62PD.St Pole disagreement protection at side x of transformer starts.
2 x.62PD.On Pole disagreement protection at side x of transformer is enabled.

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3 x.62PD.Op Pole disagreement protection at side x of transformer operates to trip.
4 x.62PD.Alm Pole disagreement protection at side x of transformer operates to alarm.
Pole disagreement protection at side x of transformer picks up to trigger DFR
5 x.62PD.TrigDFR
function.
3.22.5 Logic
SIG 62PD.In_PD_CB
SET 3I0>[x.62PD.3I0_Set] &
EN [x.62PD.En_3I0]
>=1 >=1 &
x.62PD.St
[x.62PD.t_Op] 0ms x.62PD.Op

SET I2>[x.62PD.I2_Set] &
EN [x.62PD.En_I2]
SIG x.62PD.Blk
&
SIG x.62PD.En1 &
x.62PD.On
SIG x.62PD.En2
EN [x.62PD.En]
SIG x.62PD.In_PD_CB [x.62PD.t_Alm] 0ms x.62PD.Alm
Figure 3.22-1 Logical diagram of pole disagreement protection
Where:
3.22.6 Settings
Table 3.22-2 Settings of pole disagreement protection

Residual current setting of pole disagreement
1 x.62PD.3I0_Set 0.04~30In 0.001 A
protection
Negative-sequence current setting of pole
2 x.62PD.I2_Set 0.04~30In 0.001 A
disagreement protection
Time delay of pole disagreement protection for
3 x.62PD.t_Op 0~20 0.001 s
trip purpose
4 x.62PD.t_Alm 0~20 0.001 s
alarm purpose
5 x.62PD.En_3I0 0 or 1 1 Logic setting of enabling/disabling residual

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current criterion to control pole disagreement
protection
0: disable
1: enable
6 x.62PD.En_I2 0 or 1 1 breaker failure protection
0: disable
1: enable
Logic setting of enabling/disabling pole
7 x.62PD.En_PD 0 or 1 1
0: disable
1: enable
Tripping logic setting of pole disagreement
8 x.62PD.OutMap 0000~FFFF
protection
3.23 Phase Overcurrent Alarm (51PAlm)
3.23.1 Application
During overload operation of a power transformer, great current results in greater heat to lead
temperature of transformer increase and if the temperature reaches certain values, the
transformer might be damaged. The insulation within the transformer will have forced ageing.
Phase overcurrent alarm is equipped to monitor the load of transformer winding, and when load
current exceeds the transformer limit load current, phase overcurrent alarm can be applied to
issue alarm signal to remind field operators. Besides, during overload of transformer, it is needed
to initiate cooling system (such as cooling fan) and blocking OLTC. Therefore phase overcurrent
alarm can also be applied to initiate cooling system and block OLTC.
NOTICE!
Phase overcurrent alarm provides two-stage definite-time phase overcurrent alarm elements with
independent logic, current and time delay settings. Phase overcurrent alarm is only applied for
alarm signals. Fundamental current or 1st to 7th harmonic current is used for protection
calculation.
The operation criterion:
IP>[51PAlmn.I_Set] Equation 3.23-1

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Where:
IP is phase current.
51PAlm
x.51PAlmn.I3P x.51PAlmn.St
x.51PAlmn.En1 x.51PAlmn.On
x.51PAlmn.En2 x.51PAlmn.Alm
x.51PAlmn.Blk
3.23.4 I/O Signals

Table 3.23-1 I/O signals of phase overcurrent alarm

Three-phase current data input for stage n of phase overcurrent alarm at side x of
1 x.51PAlmn.I3P
transformer. (n=1, 2)
Input signal 1 of enabling stage n of phase overcurrent alarm at side x of
2 x.51PAlmn.En1
3 x.51PAlmn.En2
Input signal of blocking stage n of phase overcurrent alarm at side x of transformer.
4 x.51PAlmn.Blk
It is triggered from binary input or programmable logic etc. (n=1, 2)
1 x.51PAlmn.St Stage n of phase overcurrent alarm at side x of transformer starts. (n=1, 2)
2 x.51PAlmn.On Stage n of phase overcurrent alarm at side x of transformer is enabled. (n=1, 2)
Stage n of phase overcurrent alarm at side x of transformer operates to alarm.
3 x.51PAlmn.Alm
(n=1, 2)
3.23.5 Logic
EN [x.51PAlmn.En]
&
SIG x.51PAlmn.En1
& x.51PAlmn.On
SIG x.51PAlmn.En2
SIG x.51PAlmn.Blk
&
SIG x.51PAlmn.I3P x.51PAlmn.St
[x.51PAlmn.t_Op] 0ms x.51PAlmn.Alm

SET [x.51PAlmn.I_Set]
Figure 3.23-1 Logic diagram of phase overcurrent alarm (n=1, 2)

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3.23.6 Settings
Table 3.23-2 Settings of phase overcurrent alarm

Current setting of stage n of phase overcurrent
1 x.51PAlmn.I_Set 0.04A~30In 0.001 A
alarm (n=1, 2)
Time delay of stage n of phase overcurrent
2 x.51PAlmn.t_Op 0~3600 0.001 s
alarm (n=1, 2)
Drop off ratio of stage n of phase overcurrent
3 x.51PAlmn.K_DropOut 0.7~1.0 0.001
alarm (n=1, 2)
Logic setting of enabling/disabling stage n of
phase overcurrent alarm (n=1, 2)
4 x.51PAlmn.En 0 or 1
0: disable
1: enable
3.24 Residual Overvoltage Alarm (59GAlm)
3.24.1 Application
A single phase earth fault occurrence in ungrounded system will result in high residual overvoltage,
so residual overvoltage alarm is equipped to issue alarm signal to remind the operators in this
condition.
NOTICE!

Only one-stage residual overvoltage alarm is equipped, it can be selected as definite-time or
inverse-time characteristic. The inverse-time characteristic is selectable among IEC and
ANSI/IEEE standard inverse-time characteristics and a user-defined inverse-time curve.
3U0>[x.59GAlm.3U0_Set] Equation 3.24-1
Where:
3U0 is measured residual voltage.
3.24.2.2 Time Curve
Residual overvoltage alarm can be selected as definite-time or inverse-time characteristic, and

inverse-time operating time curve is as follows.

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Equation 3.24-2
Where:
Uset is residual voltage setting [x.59GAlm.3U0_Set].
Tp is time setting [x.59GAlm.TMS].
α is a constant
U is actual measured residual voltage.
setting [x.59GAlm.Opt_Curve], and parameters of available characteristics for selection are shown
in the following table.
x.59GAlm.Opt_Curve Time Characteristic K α C

If all available curves do not comply with user application, user may configure setting [x.
59GAlm.Opt_Curve] to “UserDefine” to customize the inverse-time curve characteristic, and

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59GAlm
x.59GAlm.U3P x.59GAlm.St
x.59GAlm.U1P x.59GAlm.On
x.59GAlm.En1 x.59GAlm.Alm
x.59GAlm.En2
x.59GAlm.Blk
3.24.4 I/O Signals

Table 3.24-2 I/O signals of residual overvoltage alarm

Three-phase voltage data input for residual overvoltage alarm at side x of
1 x.59GAlm.U3P
transformer.
Measured residual voltage data input for residual overvoltage alarm at side x of
2 x.59GAlm.U1P
transformer.
Input signal 1 of enabling residual overvoltage alarm at side x of transformer. It is
3 x.59GAlm.En1
Input signal 2 of enabling residual overvoltage alarm at side x of transformer. It is
4 x.59GAlm.En2
Input signal of blocking residual overvoltage alarm at side x of transformer. It is
5 x.59GAlm.Blk
1 x.59GAlm.St Residual overvoltage alarm at side x of transformer starts.
2 x.59GAlm.On Residual overvoltage alarm at side x of transformer is enabled.
3 x.59GAlm.Alm Residual overvoltage alarm at side x of transformer operates to alarm.
3.24.5 Logic
EN [x.59GAlm.En]
&
SIG x.59GAlm.En1
& x.59GAlm.On
SIG x.59GAlm.En2
SIG x.59GAlm.Blk
SIG x.59GAlm.U3P >=1 &

x.59GAlm.St
SIG x.59GAlm.U1P Timer
t x.59GAlm.Alm
t
SET [x.59GAlm.3U0_Set]
Figure 3.24-1 Logic diagram of residual overvoltage alarm

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3.24.6 Settings
Table 3.24-3 Settings of residual overvoltage alarm

1 x.59GAlm.3U0_Set 2~200 0.001 V Voltage setting of residual overvoltage alarm
2 x.59GAlm.t_Alm 0~3600 0.001 s Time delay of residual overvoltage alarm
3 x.59GAlm.K_3U0_Max 1~2 0.001 voltage to the pickup setting of residual
overvoltage alarm
4 x. 59GAlm.tmin 0~20 0.001 s Minimum delay of residual overvoltage alarm
Time multiplier setting of residual overvoltage
5 x. 59GAlm.TMS 0.05~3.2 0.001
alarm
6 x. 59GAlm.K 0.0~120 0.001 The constant K of residual overvoltage alarm
7 x. 59GAlm.C 0.0~20 0.001 s The constant C of residual overvoltage alarm
The exponent alpha of residual overvoltage
8 x. 59GAlm.Alpha 0.02~5 0.001
alarm
DefTime
IECN
IECV
IECE
IECST
IECLT
ANSIE Option of characteristic curve for residual
9 x. 59GAlm.Opt_Curve
ANSIV overvoltage alarm
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
Logic setting of enabling/disabling residual
overvoltage alarm
10 x.59GAlm.En 0 or 1
0: disable
1: enable
Option of residual voltage for residual
overvoltage alarm
11 x.59GAlm.Opt_3U0 0, 1 1
3.25 Mechanical Protection (MR)
3.25.1 Application
If there is a fault in transformer body, winding temperature relay, oil temperature relay and

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Buchholz relay (or called gas relay) integrated in transformer will operate to send signals to
PCS-978. Mechanical protection will repeat these signals to send alarm signals, or send tripping
command directly or send tripping command with time delay to prevent transformer from damage.
Inputs of mechanical protection are operation signals of transformer's integrated relay, and it is
generally required to repeat those signals through high-power relays to improve the anti-inference
ability of the protection.
Mechanical protection provides 4 mechanical signal input channels for tripping directly or with time
delay. It adopts high-power relays d to improve the anti-interference ability of mechanical
protection. If 110Vac (or 220Vac) voltage is connected to the signal input terminal of mechanical
relay, mechanical protection does not maloperate by mistake.
Mechanical relay repeats external signal through high-power relays and send them to CPU
through opto-coupler circuits. After CPU receives those signals, the device will record them as
events and send tripping command with settable time delays. Because the dropoff time of
mechanical input signals is usually too long, the setting [MR.t_PW_n] (n=1, 2, 3, and 4) can be set
to avoid mechanical relay sending long-time tripping command.
MR
MR.Input1 MR.Sig1
MR.Input2 MR.Sig2
MR.Input3 MR.Sig3
MR.Input4 MR.Sig4
MR.En1 MR.On1
MR.En2 MR.On2
MR.Blk MR.On3
MR.On4
MR.Op1
MR.Op2
MR.Op3
MR.Op4

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3.25.4 I/O Signals

Table 3.25-1 I/O signals of mechanical protection

1 MR.Input1 Input signal 1 of mechanical relay.
Input signal 1 of enabling mechanical protection. It is triggered from binary input or
5 MR.En1
Input signal 2 of enabling mechanical protection. It is triggered from binary input or
6 MR.En2
Input signal of blocking mechanical protection. It is triggered from binary input or
7 MR.Blk
1 MR.Sig1 Repeating output signal 1 of mechanical relay.
5 MR.On1 Input signal 1 of mechanical relay is enabled.
9 MR.Op1 Input signal 1 of mechanical relay operates.
3.25.5 Logic
EN [MR.En_1]
&
SIG MR.En1
& MR.On1
SIG MR.En2
&
SIG MR.Blk
[MR.t_PW_1] MR.Op1
SIG MR.Input1
EN [MR.En_2]
&
SIG MR.En1
& MR.On2
SIG MR.En2
&
SIG MR.Blk
[MR.t_PW_2] MR.Op2
SIG MR.Input2

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EN [MR.En_3]
&
SIG MR.En1
& MR.On3
SIG MR.En2
&
SIG MR.Blk
[MR.t_PW_3] MR.Op3
SIG MR.Input3
EN [MR.En_4]
&
SIG MR.En1
& MR.On4
SIG MR.En2
&
SIG MR.Blk
[MR.t_PW_4] MR.Op4
SIG MR.Input4
Figure 3.25-1 Logic diagram of mechanical protection
3.25.6 Settings
Table 3.25-2 Settings of mechanical protection

Delay pickup time of tripping command of
1 MR.t_DPU_1 0~3600 0.001 s
mechanical relay 1
Pulse width of tripping command of mechanical
2 MR.t_PW_1 0~10 0.001 s
relay 1
Logic setting of enabling/disabling mechanical
relay 1
3 MR.En_1 0 or 1
0: disable
1: enable
4 MR.OutMap_1 0000~FFFF Tripping logic setting of mechanical relay 1
5 MR.t_DPU_2 0~3600 0.001 s
mechanical relay 2
6 MR.t_PW_2 0~10 0.001 s
relay 2
relay 2
7 MR.En_2 0 or 1
0: disable
1: enable
9 MR.t_DPU_3 0~3600 0.001 s
mechanical relay 3
10 MR.t_PW_3 0~10 0.001 s
relay 3
11 MR.En_3 0 or 1 Logic setting of enabling/disabling mechanical

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relay 3
0: disable
1: enable
13 MR.t_DPU_4 0~3600 0.001 s
mechanical relay 4
14 MR.t_PW_4 0~10 0.001 s
relay 4
relay 4
15 MR.En_4 0 or 1
0: disable
1: enable
3.26 Temperature Protection (26)
3.26.1 Application
Temperature protection is applied for protecting transformer or reactor from being damaged by
over temperature due to overloads or other reasons.

It can receive 6 DC signals (0~20mA or 0~5V) from external temperature transducers to convert to
temperature values.
NOTICE!
Analog inputs between 0~4mA DC can also be processed, and all the analog inputs
between 0~4mA DC will be processed as 4mA. Therefore, 0~20mA analog DC input
can be processed.
The device can receive signals from external temperature transducers and convert these signals
into digital data as required via DC plug-in module NR1410B. The actual operation temperature of
a transformer can be calculated with the following equation after setting the range of temperature
measurement (minimum temperature setting corresponds to 4mA or 0V, and maximum
temperature setting corresponds to 20mA or 5V).
Equation 3.26-1
Where:
Cmin is the minimum measured value.

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3 Operation Theory
Tmin is the temperature corresponding to minimum measured value.
CC is actual measured value.
Cmax and Tmax are maximum measured value and the temperature corresponding to it respectively.
K is the slope of temperature converting
T is the actual temperature after converting.
When the maximum value, among three phase temperature values of transformer corresponding
to three transducer inputs, is greater than the setting for trip purpose, temperature protection
operate to trip circuit breakers. The operation criterion is as follows.
T>[26.T_Trp] Equation 3.26-2
Where:
T is maximum value among three phase temperature values of transformer corresponding to three
transducer inputs.
[26.T_Trp] is the temperature setting for tripping of temperature protection.
When the maximum value, among three phase temperature values of transformer corresponding
to three transducer inputs, is greater than the setting for alarm purpose, temperature protection
operates to issue the related alarm signal. The operation criterion is as follows.
T>[26.T_Alm] Equation 3.26-3
Where:
T is maximum value among three phase temperature values of transformer corresponding to three
transducer inputs.
[26.T_Alm] is the temperature setting for alarming of temperature alarm element.
26
26.Input_PhA 26.T_PhA
26.Input_PhB 26.T_PhB
26.Input_PhC 26.T_PhC
26.En1 26.St
26.En2 26.On
26.Blk 26.Op
26.Alm

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3 Operation Theory
3.26.4 I/O Signals

Table 3.26-1 I/O signals of temperature protection

1 26.Input_PhA DC input signal of phase A from external transducer.
2 26.Input_PhB DC input signal of phase B from external transducer.
3 26.Input_PhC DC input signal of phase C from external transducer.
Input signal 1 of enabling temperature protection. It is triggered from binary input or
4 26.En1
Input signal 2 of enabling temperature protection. It is triggered from binary input or
5 26.En2
Input signal of blocking temperature protection. It is triggered from binary input or
6 26.Blk
1 26.T_PhA Calculated temperature of phase-A signal from external transducer.
2 26.T_PhB Calculated temperature of phase-B signal from external transducer.
3 26.T_PhC Calculated temperature of phase-C signal from external transducer.
4 26.St Temperature protection starts.
5 26.On Temperature protection is enabled.
6 26.Op Temperature protection operates to trip.
7 26.Alm Temperature protection operates to alarm.
8 26.TrigDFR Temperature protection picks up to trigger DFR function.
3.26.5 Logic
SIG T_PhA>[26.T_Trp]
>=1
SIG T_PhB>[26.T_Trp] &
[26.t_Trp] 0s 26.Op
SIG T_PhC>[26.T_Trp]
26.St
EN [26.En_Trp]
&
SIG 26.En1
& 26.On
SIG 26.En2
SIG 26.Blk &

26.On
EN [26.En_Alm]
SIG 26.Blk
&
SIG T_PhA>[26.T_Alm]
>=1 [26.t_Alm] 0s 26.Alm
SIG T_PhB>[26.T_Alm]
SIG T_PhC>[26.T_Alm]
Figure 3.26-1 Logic diagram of temperature protection

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3 Operation Theory
3.26.6 Settings
Table 3.26-2 Settings of temperature protection

Temperature setting corresponding to the
1 26.Tmax 0~200 0.01 °C
maximum input
2 26.Tmin 0~200 0.01 °C
minimum input
Temperature setting for trip purpose of
3 26.T_Trp 0~200 0.01 °C
temperature protection
Temperature setting for alarm purpose of
4 26.T_Alm 0~200 0.01 °C
temperature alarm element
Time delay for trip purpose of temperature
5 26.t_Trp 0.01~4800 0.001 s
protection
Time delay for alarm purpose of temperature
6 26.t_Alm 0.01~4800 0.001 s
protection
Logic setting of enabling/disabling temperature
7 26.En_Trp 0 or 1
0: disable
1: enable
8 26.En_Alm 0 or 1
0: disable
1: enable
9 26.OutMap 0000~FFFF Tripping logic setting of temperature protection
Input option of temperature transducer
0~5V Input signal from Pt100 sensors, i.e., the nominal
10 26.Opt_Input_T 0~20mA 1 resistance of 100 ohms at 0 °C (Pt is the symbol
Pt100 for platinum, 100 for the resistance in ohm at
0 °C).
3.27 Output Map (OutMap)
3.27.1 Application
Output map controls tripping outputs of protection elements and programmable logics. Each
protection element has its corresponding tripping logic setting used to configure tripping output
contacts, and 10 tripping outputs of programmable logics are equipped for visual logic
programming.

All tripping output contacts are with a dwell time of 120ms (fixed in program) to ensure sufficient
time of tripping command to open the circuit breaker.

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3 Operation Theory
3.27.2.1 Protection Element Trip Output
For default configuration, each protection element can control total 10 groups of tripping output
contacts by tripping logic settings. Therefore, the user can configure the tripping output contacts of
each protection element individually though the corresponding tripping logic setting. 10 groups of
independent tripping output contacts can be defined to trip HV side, MV side, and LVS side etc.
Each group of tripping contacts can correspond to certain amount of contacts on binary output
plug-in modules.
Tripping logic settings are used to specify which breakers will be tripped when some protection
element operates. This logic setting comprises 16 binary bits as follows and is expressed by a
hexadecimal number of 4 digits from 0000H to FFFFH. The tripping logic setting is specified as
follows:
Bit Definition Bit Definition

0 TrpOutput01 8 TrpOutput09
“TrpOutput01” just means to drive 1st group of tripping output contacts and please refer to Chapter
“Hardware”. The tripping outputs are recorded as “T01~T16” by the device when they operate, and
“Txx” (xx=01, 02…16) represents “trip output xx” (xx=01, 02…16). The circuit breaker
corresponding with bit which is set as “1” will be tripped. Tripping output logic settings should be
set on basis of application-specific drawings.
For example, if transformer differential protection operates to make “TrpOutput01”, “TrpOutput02”,

“TrpOutput03” contacts pickup, bit “0”, bit “1” and bit “2” shall be filled with “1” and other bits shall
be filled with “0”. Then a hexadecimal number 0007H is formed as the tripping output logic setting,
i.e. [87T.OutMap] shall be set as “0007H”.
3.27.2.2 Programmable Trip Output
The device provides 10 programmable trip output with I/O signals and settings for users used by
visualization programming. Users can set trip output of programming logic if trip output of
protection element provided by the device cannot meet application requirements completely.
For example, if it is required to set stage 1 of phase overcurrent protection at HV side of the
transformer operate to issue trip command after its operation criterion is satisfied “AND” receiving
a binary input which can be a blocking signal from other device, programmable trip output can
complete the function configuration as following steps.
1. Set tripping logic setting of stage 1 of phase overcurrent protection at HV side of the
transformer as “0000H”, i.e., [HVS.50/51P.OutMap]=0000H.

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3 Operation Theory
2. Finish required programming logic by PCS-Explorer.
3. Connect final output of programming logic to input signal of programmable trip output.
4. Set corresponding tripping logic setting of programmable trip output to complete the function
configuration.
3.27.3 I/O Signals

Table 3.27-1 I/O signals of programmable trip output

1 Sig_ProgTrp01 Input signal of programmable tripping output element 1.
3.27.4 Settings
Table 3.27-2 Settings of programmable trip output

Tripping logic setting of programmable trip output
1 OutMap_ProgTrp01 0000~FFFF
01
02
03
04
05
06
07
08
09
10 OutMap_ProgTrp10 0000~FFFF Tripping logic setting of programmable trip output

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3 Operation Theory

10
3.28 Intermediate Variable Element
In order to better support logic programming function, 20 intermediate variables are provided. The
user can distribute the middle results of logic programming to intermediate variables, and use the
intermediate variables to carry out other logic programming. Not only intermediate variable display
is supported by the device, but also its state change report is recorded by the device.
For example, if LED 10 is needed to be lit when stage 1 of phase overcurrent protection at HV side
of transformer or stage 1 of phase overcurrent protection at LV side of transformer operates, then
the following logic can be programmed through PCS-Explorer.
SIG HVS.50/51P1.Op >=1

Sig_Spare01
SIG LVS.50/51P1.Op
SIG Sig_Spare01 LED 10
Figure 3.28-1 An example of programmable logic
3.28.2 I/O Signals
The following signals of intermediate variable are used to transfer signals, so they are input
signals and the corresponding output signals at the same time.
Table 3.28-1 Signals of intermediate variable element
No. Item Description
1 Sig_Spare01 Signal of intermediate variable 1 for logic programming

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3 Operation Theory

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3 Operation Theory

Date: 2016-06-22
4 Supervision
4 Supervision
Table of Contents
4.1 Overview ........................................................................................................... 4-1
4.2 Relay Self-supervision .................................................................................... 4-1
4.2.1 Relay Hardware Supervision ................................................................................................ 4-1
4.2.2 Output Tripping Circuit Supervision...................................................................................... 4-1
4.2.3 Setting Checking .................................................................................................................. 4-1
4.2.4 Memory Checking ................................................................................................................ 4-1
4.2.5 Opto-coupler Power Supervision ......................................................................................... 4-2
4.2.6 Fault Detector Element Supervision .................................................................................... 4-2
4.2.7 Test Mode Supervision ......................................................................................................... 4-2
4.2.8 Hardware Configuration Supervision ................................................................................... 4-2
4.3 CT Circuit Supervision (CTS).......................................................................... 4-2

4.4 Voltage Circuit Supervision (VTS) .................................................................. 4-2
4.5 Frequency Supervision ................................................................................... 4-2
4.6 Failure and Abnormality Alarms ..................................................................... 4-3
4.6.1 Hardware Self-supervision Alarms ....................................................................................... 4-3
4.6.2 Protection Function Alarms .................................................................................................. 4-6
List of Tables
Table 4.6-1 Alarm message description ...................................................................................... 4-3
Table 4.6-2 Troubleshooting ...................................................................................................... 4-4
Table 4.6-3 Alarm message description ................................................................................... 4-7
Table 4.6-4 Troubleshooting ...................................................................................................... 4-7

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4 Supervision

Date: 2015-06-26
4 Supervision
4.1 Overview
Though the protection system is in non-operating state under normal conditions, it is waiting for a
power system fault to occur at any time and must operate for the fault without fail. When
equipment is in energizing process before the LED “HEALTHY” is on, the equipment needs to be
checked to ensure no errors. Therefore, the automatic supervision function, which checks the
health of the protection system when startup and during normal operation, plays an important role.
The numerical relay based on the microprocessor operations is suitable for implementing this
automatic supervision function of the protection system.
In case a fatal fault is detected during automatic supervision, the equipment will be blocked. It
means that relay is out of service. Before you must re-energize the relays to make relay back into
service, please find out the cause and inform the manufacturer.
When a failure is detected by the automatic supervision, it is followed with an LCD message, LED
indication and alarm contact outputs. At the same time event recording will record the failure alarm
which can be viewed in event recording report and be printed.
4.2 Relay Self-supervision
4.2.1 Relay Hardware Supervision
All chips on each module are monitored to ensure whether they are damaged or have errors. If
any one of them is detected damaged or having error, the corresponding alarm signal
[ProtBrd.Fail_DSP] or [FDBrd.Fail_DSP] is issued with equipment being blocked.
AC current and voltage samplings of protection DSP module and fault detector DSP module are
monitored and if the samples are detected to be wrong or inconsistent, an alarm
[ProtBrd.Fail_Sample] or [FDBrd.Fail_Sample] will be issued and the relay will be blocked.
4.2.2 Output Tripping Circuit Supervision

States of binary outputs are continuously monitored. If any abnormality of the BO module at slot
Bxx (Bxx is the slot number) is detected, the alarm signal [Bxx.Alm_Output] will be issued.
4.2.3 Setting Checking

This relay has 30 setting groups, while only one is active at the same time. The settings of active
setting group are checked to ensure they are reasonable. If settings are checked to be
unreasonable or out of setting scopes, a corresponding alarm signal will be issued, and the
protective device will also be blocked.
4.2.4 Memory Checking

Data in non-volatile memory, which are not changed after device energized, are always checked
during device normal operation, such as settings, pointers, etc. If these data changed abnormally,
the corresponding alarm [ProtBrd.Memory] or [FDBrd.Memory] will be issued.

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4 Supervision
4.2.5 Opto-coupler Power Supervision

Positive power supply of opto-coupler on each BI module at slot xx (Bxx is the slot number) is
continuously monitored, and if a failure or damage on the module is detected, then the alarm
signal [Bxx.Alm_OptoDC] will be issued.
4.2.6 Fault Detector Element Supervision

If any fault detector picks up to trigger oscillography function, the corresponding binary input
changing report will be recorded in “IO Events” menu with tripping report [TrigDFR] being issued.
If a fault detector on protection or fault detector DSP module keeps picking up for 500s, the
corresponding alarm signal [ProtBrd.Alm_Pkp] or [FDBrd.Alm_Pkp] will be issued without
equipment being blocked.
4.2.7 Test Mode Supervision
When protection equipment is in communication test mode the alarm signal [Alm_CommTest] is
issued without blocking equipment.
4.2.8 Hardware Configuration Supervision
Module configuration is checked automatically during equipment initialization, if plug-in module

configuration is not consistent to the design drawing of an applied-specific, the alarm signal
[Fail_BoardConfig] is issued with the equipment being blocked.
4.3 CT Circuit Supervision (CTS)
CTS is designed to detect the CT secondary circuit to ensure that current measurement is the
actual value of power system. The main purpose of the function is to ensure the integrity of CT
circuits maintaining the performance of the device.
4.4 Voltage Circuit Supervision (VTS)
VTS is designed to detect the VT secondary circuit to ensure that voltage measurement is the
actual value of power system. When VT failure is detected, the device can automatically adjust the
configuration of protection elements of which the stability would be affected and might lead to
mal-operation.
4.5 Frequency Supervision
If system frequency detected is too high or low, the device will issue an alarm signal [Alm_Freq]
instantly to reminding operators for attention. The device provides two settings [f_High_FreqAlm]
and [f_Low_FreqAlm] to set the threshold of frequency alarm.

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4 Supervision
4.6 Failure and Abnormality Alarms
NOTICE!
Following alarm messages and corresponding LED indicators are fixed in device.
Besides, there are other programmable LED indicators configured according to different
project requirement.
4.6.1 Hardware Self-supervision Alarms
Equipment hardware circuits and software working conditions are always monitored by the relay. If
any abnormality occurs, the corresponding alarm message will be issued on the LCD of the
equipment.
When some light failures are detected, part of protection functions probably be disabled and
others can still work. Some severe failures of hardware or software will result in the equipment
being blocked and the contacts of equipment failure will operate at same time. During that
condition, the protection relay has to be out of service for maintenance.
NOTICE!
If alarm signal is issued with equipment being blocked, please try to make a fault
diagnosis by referring the issued alarm messages but not simply reboot or re-power the
relay. If user cannot find the failure reason on site, please inform the manufacturer or
the agent for maintenance.
Table 4.6-1 Alarm message description

Failure Signals: Blocke device, “HEALTHY” LED off, “ALARM” LED on
1 Fail_Device The device fails.
2 Fail_Setting_OvRange Setting values are out of range.
Mismatch between the configuration of plug-in modules and the designing
3 Fail_BoardConfig
drawing of an applied-specific project.
After configuration file is updated, settings of the file and settings saved on
4 Fail_SettingItem_Chgd
the device are not matched.
5 ProtBrd.Fail_Settings Error is found during checking settings on protection module.
6 FDBrd.Fail_Settings Error is found during checking settings on fault detector module.
7 ProtBrd.Fail_Memory Error is found during checking the memory data on protection module.
8 FDBrd.Fail_Memory Error is found during checking the memory data on fault detector module.
9 ProtBrd.Fail_Sample Sample values on protection module are abnormal.
10 FDBrd.Fail_Sample Sample values on fault detector module are abnormal.
11 ProtBrd.Fail_Config Software configuration error on protection module is found.
12 FDBrd.Fail_Config Software configuration error on fault detector module is found.
13 ProtBrd.Fail_DSP DSP chip on protection module is damaged.
14 FDBrd.Fail_DSP DSP chip on fault detector module is damaged.
15 ProtBrd.Fail_QF_SV The quality factor of sample values on protection module is abnormal.

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4 Supervision

16 FDBrd.Fail_QF_SV The quality factor of sample values on fault detector module is abnormal.
Alarm Signals: Not block device, “HEALTHY” LED on, “ALARM” LED on
17 Alm_Device The device is abnormal.
18 Alm_CommTest The device is in the communication test mode.
19 Alm_TimeSyn Time synchronization abnormality alarm.
The error is found during checking the version of software downloaded to
20 Alm_Version
the device.
21 Alm_Settings_MON The error is found during MON module checking settings of device.
22 BI_Maintenance The device is in maintenance state.
The active setting group configured by settings in device and that configured
23 Alm_BI_SettingGrp
by binary input are not matched.
24 Bxx.Alm_OptoDC The power supply of Bxx binary input module is abnormal.
The duration of pickup of any fault detector on protection module is in
25 ProtBrd.Alm_Pkp
excess of 10s.
The duration of pickup of any fault detector on fault detector module is in
26 FDBrd.Alm_Pkp
excess of 10s.
27 Alm_Insuf_Memory The memory of MON module is insufficient.
28 Bxx.Alm_Output BO module at slot xx (Bxx is the slot number) is abnormal.
29 Bxx.Alm_Board The board at slot xx (Bxx is the slot number) is abnormal.
Table 4.6-2 Troubleshooting
No. Item Handling suggestion

Failure Signals: Blocke device, “HEALTHY” LED off, “ALARM” LED on
The signal is always issued with other specific failure signals.
1 Fail_Device
Please refer to the handling suggestion of other specific fail signals.
Please reset setting values according to the range described in the
instruction manual, then re-power or reboot the equipment and the alarm
2 Fail_Setting_OvRange
message will disappear and the equipment will restore to normal operation
state.
Step 1: Go to the menu “Information”->”Board Info”, check the abnormality
information.
Step 2: For the module with abnormality, if the module is not used, then
3 Fail_BoardConfig remove, and if the module is used, then check whether the module is
installed properly and work normally.
After the abnormality is removed, re-power or reboot the equipment and the
equipment will restore to normal operation state.
Please check the settings mentioned in the prompt message on the LCD,
4 Fail_SettingItem_Chgd and go to the menu “Settings” and select “Confirm Settings” item to
confirm settings. Then the equipment will restore to normal operation stage.
Step 1: Check CT ratio settings of each side of transformer to be set in
5 ProtBrd.Fail_Settings
proper range, and if needed, please reset those settings and reboot or
6 FDBrd.Fail_Settings re-power the equipment.

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4 Supervision

Step 2: Check overexcitation settings to be set reasonable, and if needed,
please reset those settings and reboot or re-power the equipment.
Step 3: After above two steps, abnormality may disappear. Otherwise, a
hardware failure probably occurs and please inform the manufacturer or the
agent
7 ProtBrd.Fail_Memory
Please inform the manufacturer or the agent for maintenance.
8 FDBrd.Fail_Memory
Step 1: Please make the equipment out of service.
9 ProtBrd.Fail_Sample Step 2: Then check if the analog input modules and wiring connectors
connected to those modules are installed at the position.
Step 3: Re-power the equipment and the equipment will restore to normal
10 FDBrd.Fail_Sample
operation state.
11 ProtBrd.Fail_Config Please inform configuration engineers to check and confirm visualization
12 FDBrd.Fail_Config functions of the device.
13 ProtBrd.Fail_DSP Chips are damaged and please inform the manufacturer or the agent to
14 FDBrd.Fail_DSP replace the module.
15 ProtBrd.Fail_QF_SV These alarms may be issued for electric transformer applied projects. If
alarms are issued, please check working state of merging units and the
16 FDBrd.Fail_QF_SV
connection between merging units and the protection device.
The signal is always issued with other specific alarm signals.
17 Alm_Device
Please refer to the handling suggestion of other specific alarm signals.
No special treatment is needed. Just wait the completion of communication
18 Alm_CommTest
test or exit the test.
Step1: Check whether the selected clock synchronization mode matches
the clock synchronization source.
Step 2: Check whether the wiring connection between the equipment and
the clock synchronization source is correct.
Step 3: Check whether the setting for selecting clock synchronization (i.e.
19 Alm_TimeSyn
[Opt_TimeSyn]) is set correctly. If there is no clock synchronization, please
set the setting [Opt_TimeSyn] as “No TimeSyn”.
After the abnormality is removed, the “ALARM” LED will be extinguished
and the corresponding alarm message will disappear and the equipment will
restore to normal operation state.
Users may pay no attention to the alarm signal in the project commissioning
stage, but it is needed to download the latest package file (including correct
20 Alm_Version version checksum file) provided by R&D engineer to make the alarm signal
disappear. Then users get the correct software version. It is not allowed that
the alarm signal is issued on the device already has been put into service.
21 Alm_Settings_MON Please inform the manufacturer or the agent for maintenance.
After maintenance is finished, please de-energized the binary input
22 BI_Maintenance [BI_Maintenance] and then the alarm will disappear and the equipment

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4 Supervision

Please check the value of setting [Active_Grp] and binary input of indicating
active group, and make them matched. Then the “ALARM” LED will be
23 Alm_BI_SettingGrp
extinguished and the corresponding alarm message will disappear and the
equipment will restore to normal operation state.
Step 1: Check whether the binary input module is connected to the power
supply.
Step 2: check whether the voltage of power supply is in the required range.
24 Bxx.Alm_OptoDC
After the voltage for binary input module restores to normal range, the
“ALARM” LED will be extinguished and the corresponding alarm message
will disappear and the equipment will restore to normal operation state.
Please check secondary values and protection settings. If settings are not
set reasonable to make fault detectors pick up, please reset settings, and
then the alarm message will disappear and the equipment will restore to
25 ProtBrd.Alm_Pkp normal operation state.
NOTICE!
Tripping out contacts will be blocked in 1s after the device is

energized with “HEALTHY” LED indicator being lit. This situation
is decided as a relay fault, and the alarm signal [ProtBrd.Alm_Pkp]
26 FDBrd.Alm_Pkp
and [FDBrd.Alm_Pkp] will be issued after tripping output contacts
keeps on picking up over 10s.
Please replace the MON module on device with another one with greater
27 Alm_Insuf_Memory
memory.
Please re-insert corresponding binary output module and re-power or reboot
28 Bxx.Alm_Output the equipment after the completion of insertion, and then the equipment will
29 Bxx.Alm_Board Please check the module located in slot xx.
NOTICE!
If the equipment still cannot restore to normal operation state after suggested
procedures, please inform the manufacturer or the agent for maintenance.
4.6.2 Protection Function Alarms

During the device's normal operation, VT and CT circuit and some binary input circuits are always
monitored by the device. If any abnormality of them occurs or any alarm element operates, the
corresponding alarm message will be issued on the LCD without blocking the device and
“ALARM” LED is lit at the same time.
When this kind of alarm messages are issued, the operators need to find the abnormality reason,
and then take corresponding measures to eliminate the alarm message to make the device return
to the normal operation state.

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4 Supervision
Table 4.6-3 Alarm message description

Whether the corresponding biased differential protection is blocked is decided by the corresponding
logic setting.
1 87T.Alm_CTS CT secondary circuit for transformer differential protection fails.
3 x.64REF.Alm_CTS CT secondary circuit for restricted earth fault protection of side x fails.
5 x.AlmH_CTS CT secondary circuit at side x fails.
Differential current of restricted earth-fault protection at side x of transformer
8 x.64REF.Alm_Diff
is abnormal.
10 x.Alm_VTS VT secondary circuit at x side is abnormal.
11 x.AlmL_CTS CT secondary circuit at x side is abnormal.
12 x.49.Alm Thermal overload protection operates to issue alarm signal.
13 24DT2.Alm Definite-time overexcitation alarm element operates.
14 24IDMT.Alm Inverse-time overexcitation alarm element operates.
15 x.62PD.Alm Pole disagreement protection of x side operates to issue alarm signal.
16 Alm_Freq System frequency abnormality alarm signals.
17 26.Alm Alarm element of temperature protection operates.
Alarm Signals: Not block device, “HEALTHY” LED on, “ALARM” LED off
18 x.51PAlm1.Alm Stage 1 overload alarm element of x side operates.
19 x.51PAlm2.Alm Stage 2 overload alarm element of x side operates.
20 x.59GAlm.Alm Residual overvoltage alarm element of x side operates.
Table 4.6-4 Troubleshooting

Whether the corresponding biased differential protection is blocked is decided by the corresponding
logic setting.
1 87T.Alm_CTS
2 87R Alm_CTS Please check the corresponding CT secondary circuit. After the abnormality
3 x.64REF.Alm_CTS is eliminated, equipment can return to normal operation state by energizing
4 87W.Alm_CTS the binary input [BI_RstTarg]
5 x.AlmH_CTS
6 87T.Alm_Diff Please check the corresponding sampling values and CT secondary circuit
7 87R Alm_Diff to find out the reason resulting in the abnormality. If sample values of the
8 x.64REF.Alm_Diff equipment are not correct, please inform the manufacturer or agent for

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4 Supervision

maintenance, and if it is caused by the failure of the CT secondary circuit or
9 87W.Alm_Diff primary system, please finish troubleshooting according to the operating
instructions of protection relay.
Please check the corresponding CT secondary circuit. After the abnormality
10 x.Alm_VTS
is eliminated, “ALARM” LED will go off automatically and equipment returns
11 x.AlmL_CTS to normal operation state.
12 x.49.Alm
13 24DT2.Alm
14 24IDMT.Alm
15 x.62PD.Alm Please treat according to the specific application requirements
16 x.51PAlm1.Alm
17 x.51PAlm2.Alm
18 26.Alm
Please check device measured frequency with system actual frequency. If
19 Alm_Freq device measured frequency is inconsistent with the system actual
frequency, please check the device.
Alarm Signals: Not block device, “HEALTHY” LED on, “ALARM” LED off
20 x.51PAlm1.Alm
21 x.51PAlm2.Alm Please treat according to the specific application requirements
22 x.59GAlm.Alm
NOTICE!

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5 Management
5 Management
Table of Contents
5 Management ...................................................................................... 5-a
5.1 Measurement ................................................................................................... 5-1
5.1.1 Measurements1 & Measurements2..................................................................................... 5-1
5.1.2 Power Value ......................................................................................................................... 5-8
5.1.3 Temperature Value ............................................................................................................... 5-8
5.2 Recording ........................................................................................................ 5-8

5.2.1 Overview .............................................................................................................................. 5-8
5.2.2 Event Recording .................................................................................................................. 5-9
5.2.3 Disturbance Recording ........................................................................................................ 5-9
5.2.4 Present Recording ............................................................................................................. 5-10

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5.1 Measurement
This device performs continuous measurement of the analogue input quantities. The current full
scale of relay is 40 times of rated current, and there is no effect to the performance of IED due to
overflowing of current full scale. The device samples 24 points per cycle and calculates the RMS
value in each interval and updated the LCD display in every 0.5 second. The measurement data
can be displayed on the LCD of the relay front panel or on the local/remote PC via software tool.
Navigate the menu to view the sampling value through LCD screen.
NOTICE!
This device can be configured to support single circuit breaker application or double
circuit breakers application by PCS-Explorer.
5.1.1 Measurements1 & Measurements2

Access path:
MainMenu  “Measurements”  “Measurements1” or  “Measurements2”
The contents of “Measurements1” are as same as that of “Measurements2”. “Measurements1”

is used to display measured values from protection calculation DSP (displayed in secondary
value), while “Measurements2” is used to display measured values from fault detector DSP
(displayed in secondary value).
5.1.1.1 HVS/MVS/LVS Measurements
Access path:
MainMenu  “Measurements”  “Measurements1”  “HVS Measurements”
MainMenu  “Measurements”  “Measurements1”  “MVS Measurements”
MainMenu  “Measurements”  “Measurements1”  “LVS Measurements”
“HVS Measurements” is used to display measured values and corresponding phase angles of HV
side.
“MVS Measurements” is used to display measured values and corresponding phase angles of
MV side.
“LVS Measurements” is used to display measured values and corresponding phase angles of LV
side.
Secondary voltages/currents are displayed in this device by default. If the setting

[Opt_Display_Status] of the submenu “Settings”  “Device Setup”  “Comm Settings” is
modified to “PriValue”, primary voltages/currents will be displayed in this device.
No. Symbol Definition Resolution Unit
1 x.Ua Phase-A voltage of x side. 0.000 V/kV
2 x.Ub Phase-B voltage of x side. 0.000 V/kV

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3 x.Uc Phase-C voltage of x side. 0.000 V/kV
4 x.3U0Cal Calculated residual voltage of x side. 0.000 V/kV
5 x.U1 Positive-sequence voltage of x side. 0.000 V/kV
6 x.U2 Negative-sequence voltage of x side. 0.000 V/kV
7 x.Uab Phase-AB voltage of x side. 0.000 V/kV
8 x.Ubc Phase-BC voltage of x side. 0.000 V/kV
9 x.Uca Phase-CA voltage of x side. 0.000 V/kV
10 x.Ang(Ua-Ub) Angle between phase-A and phase-B voltages of x side. 0 deg
11 x.Ang(Ub-Uc) Angle between phase-B and phase-C voltages of x side. 0 deg
12 x.Ang(Uc-Ua) Angle between phase-C and phase-A voltages of x side. 0 deg
13 x.3U0Ext Measured external residual voltage of x side. 0.000 V/kV
14 x.Ia Phase-A current of x side. 0.000 A
15 x.Ib Phase-B current of x side. 0.000 A
16 x.Ic Phase-C current of x side. 0.000 A
17 x.3I0Cal Calculated residual current of x side. 0.000 A
18 x.I1 Positive-sequence current of x side. 0.000 A
19 x.I2 Negative-sequence current of x side. 0.000 A
20 x.Ang(Ia-Ib) Angle between phase-A and phase-B currents of x side. 0 deg
21 x.Ang(Ia-Ic) Angle between phase-B and phase-C currents of x side. 0 deg
22 x.Ang(Ic-Ia) Angle between phase-C and phase-A currents of x side. 0 deg
23 x.3I0Ext Measured external residual current of x side. 0.000 A
24 x.Ang(Ua-Ia) Angle between phase A voltage and current of x side. 0 deg
25 x.Ang(Ub-Ib) Angle between phase B voltage and current of x side. 0 deg
26 x.Ang(Uc-Ic) Angle between phase C voltage and current of x side. 0 deg
Phase A thermal state of thermal overload protection.

27 x.49.Accu_A When the value is “1”, thermal overload protection 0.000 %
operates.
Phase B thermal state of thermal overload protection.

28 x.49.Accu_B When the value is “1”, thermal overload protection 0.000 %
operates.
Phase C thermal state of thermal overload protection.

29 x.49.Accu_C When the value is “1”, thermal overload protection 0.000 %
operates.
NOTICE!
The symbol ”x” represents some side of transformer defined by the user through
PCS-Explorer software, which may be “HVS”, “MVS”, “LVS”, “CWS”, etc. If only one
protection element is equipped, the prefix “x.” may disappear.

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5.1.1.2 CWS Measurements
Access path:
MainMenu  “Measurements”  “Measurements1”  “CWS Measurements”
“CWS Measurements” is used to display measured values of common winding side.
Secondary currents are displayed in this device by default. If the setting [Opt_Display_Status] of
the submenu “Settings”  “Device Setup”  “Comm Settings” is modified to “PriValue”,
primary currents will be displayed in this device.
1 CWS.Ia Phase-A current of common winding side. 0.000 A
2 CWS.Ib Phase-B current of common winding side. 0.000 A
3 CWS.Ic Phase-C current of common winding side. 0.000 A
4 CWS.3I0Cal Calculated residual voltage of common winding side. 0.000 A
5 CWS.I1 Positive-sequence current of common winding side. 0.000 A
6 CWS.I2 Negative-sequence current of common winding side. 0.000 A
Angle between phase-A and phase-B currents of

7 CWS.Ang(Ia-Ib) 0 deg
common winding side.
Angle between phase-B and phase-C currents of

8 CWS.Ang(Ia-Ic) 0 deg
common winding side
Angle between phase-C and phase-A currents of

9 CWS.Ang(Ic-Ia) 0 deg
common winding side
Measured external residual current of common winding

10 CWS.3I0Ext 0.000 A
side.
5.1.1.3 OvExc Measurements
Access path:
MainMenu  “Measurements”  “Measurements1”  “OvExc Measurements”
“OvExc Measurements” is used to display measured values of overexcitation protection.
1 f Measured system frequency 0.000 Hz
Overexcitation multiple of definite-time overexcitation

2 24.U/f 0.000 /
protection.
Thermal state of inverse-time overexcitation protection.

3 24IDMT.ThermAccu When the value is “100%”, inverse-time overexcitation 0.000 %
5.1.1.4 Diff Measurements
Access path:

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MainMenu  “Measurements”  “Measurements1”  “Diff Measurements”
“Diff Measurements” is used to display currents for current differential protection and
corresponding phase angles.
1 87T.Ida Phase-A differential current. 0.000 p.u.
2 87T.Idb Phase-B differential current. 0.000 p.u.
3 87T.Idc Phase-C differential current. 0.000 p.u.
4 87T.Ira Phase-A restraint current. 0.000 p.u.
5 87T.Irb Phase-B restraint current. 0.000 p.u.
6 87T.Irc Phase-C restraint current. 0.000 p.u.
7 87T.Ia_Th Threshold value of phase-A restraint current. 0.000 p.u.
8 87T.Ib_Th Threshold value of phase-B restraint current. 0.000 p.u.
9 87T.Ic_Th Threshold value of phase-C restraint current. 0.000 p.u.
Phase-A 2nd harmonic percentage of total differential

10 87T.Ida_Hm2_Pcnt 0.000 %
current.
Phase-B 2nd harmonic percentage of total differential

11 87T.Idb_Hm2_Pcnt 0.000 %
current.
Phase-C 2nd harmonic percentage of total differential

12 87T.Idc_Hm2_Pcnt 0.000 %
current.
Phase-A 3rd harmonic percentage of total differential

13 87T.Ida_Hm3_Pcnt 0.000 %
current.
Phase-B 3rd harmonic percentage of total differential

14 87T.Idb_Hm3_Pcnt 0.000 %
current.
Phase-C 3rd harmonic percentage of total differential

15 87T.Idc_Hm3_Pcnt 0.000 %
current.
Phase-A 5th harmonic percentage of total differential

16 87T.Ida_Hm5_Pcnt 0.000 %
current.
Phase-B 5th harmonic percentage of total differential

17 87T.Idb_Hm5_Pcnt 0.000 %
current.
Phase-C 5th harmonic percentage of total differential

18 87T.Idc_Hm5_Pcnt 0.000 %
current.
Phase-A corrected current of branch m (m= 1,2, 3, 4,

19 87T.Ia_Cr_Brm 0.000 p.u.
5, 6) for differential protection.
Phase-B corrected current of branch m (m= 1,2, 3, 4,

20 87T.Ib_Cr_Brm 0.000 p.u.
Phase-C corrected current of branch m (m= 1,2, 3, 4,

21 87T.Ic_Cr_Brm 0.000 p.u.
22 87T.Ang(Ia)_Br1-Brm Angle between phase-A currents of branch 1 and 0 deg

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branch m (m= 2, 3, 4, 5, 6).
Angle between phase-B currents of branch 1 and

23 87T.Ang(Ib)_Br1-Brm 0 deg
branch m (m= 2, 3, 4, 5, 6).
Angle between phase-C currents of branch 1 and

24 87T.Ang(Ic)_Br1-Brm 0 deg
branch m (m= 2, 3, 4, 5, 6).
Reference current of branch m (m=1, 2, 3, 4, 5, 6) of

25 87T.Ib_Brm 0.000 A
power transformer for differential protection.
26 87R.Ia_Cr_Br1 Corrected values of phase-A current of branch 1. 0.000 p.u.
27 87R.Ib_Cr_Br1 Corrected values of phase-B current of branch 1. 0.000 p.u.
28 87R.Ic_Cr_Br1 Corrected values of phase-C current of branch 1. 0.000 p.u.
Corrected values of calculated residual current of

29 87R.3I0_Cr_Br1 0.000 p.u.
branch 1.
30 87R.Ia_Cr_Br2 Corrected values of phase-A current of branch 2. 0.000 p.u.
31 87R.Ib_Cr_Br2 Corrected values of phase-B current of branch 2. 0.000 p.u.
32 87R.Ic_Cr_Br2 Corrected values of phase-C current of branch 2. 0.000 p.u.
Corrected values of calculated residual current of

33 87R.3I0_Cr_Br2 0.000 p.u.
branch 2.
Phase angles of phase-A current between branch 1

34 87R.Ang(Ia)_Br1-Br2 0 deg
and branch 2.
Phase angles of phase-B current between branch 1

35 87R.Ang(Ib)_Br1-Br2 0 deg
and branch 2.
Phase angles of phase-C current between branch 1

36 87R.Ang(Ic)_Br1-Br2 0 deg
and branch 2.
Phase angles of calculated residual between branch 1

37 87R.Ang(3I0)_Br1-Br2 0 deg
and branch 2.
38 87R.Ida Phase-A differential current 0.000 p.u.
39 87R.Idb Phase-B differential current 0.000 p.u.
40 87R.Idc Phase-C differential current 0.000 p.u.
41 87R.3I0d Zero-sequence differential current 0.000 p.u.
42 87R.Ira Phase-A restraint current 0.000 p.u.
43 87R.Irb Phase-B restraint current 0.000 p.u.
44 87R.Irc Phase-C restraint current 0.000 p.u.
45 87R.3I0r Zero-sequence restraint current 0.000 p.u.
46 87R.Ia_Th Threshold value of phase-A restraint current. 0.000 p.u.
47 87R.Ib_Th Threshold value of phase-B restraint current. 0.000 p.u.
48 87R.Ic_Th Threshold value of phase-C restraint current. 0.000 p.u.
Threshold value of calculated residual restraint

49 87R.3I0_Th 0.000 p.u.
current.

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Second harmonic percentage of phase-A differential

50 87R.Ida_Hm2_Pcnt 0.000 %
current.
Second harmonic percentage of phase-B differential

51 87R.Idb_Hm2_Pcnt 0.000 %
current.
Second harmonic percentage of phase-C differential

52 87R.Idc_Hm2_Pcnt 0.000 %
current.
Third harmonic percentage of phase-A differential

53 87R.Ida_Hm3_Pcnt 0.000 %
current.
Third harmonic percentage of phase-B differential

54 87R.Idb_Hm3_Pcnt 0.000 %
current.
Third harmonic percentage of phase-C differential

55 87R.Idc_Hm3_Pcnt 0.000 %
current.
5.1.1.5 REF Measurements
Access path:
MainMenu  “Measurements”  “Measurements1”  “REF Measurements”
“REF Measurements” is used to display corrected currents for restricted earth fault protection and
corresponding phase angles.
Residual differential current of x side REF

1 x.64REF.3I0d 0.000 In
protection.
Residual restraint current of x side REF

2 x.64REF.3I0r 0.000 In
protection.
Threshold of residual restraint current of x side

3 x.64REF.3I0_Th 0.000 In
REF protection.
Corrected calculated residual current for branch

4 x.64REF.3I0_Cr_Brm 0.000 In
m of x side REF protection (m=1, 2, 3, 4).
Corrected residual current from neutral CT of x

5 x.64REF.3I0_Cr_NP 0.000 In
side REF protection.
Angle of calculated residual current between

6 x.64REF.Ang(3I0)_Br1-Brm branch 1 and branch m of x side REF protection 0 deg
(m=2, 3, 4).
Angle between calculated residual current of

7 x.64REF.Ang(3I0)_Br1-NP branch 1 and current from neutral CT of x side 0 deg
REF protection.
Corrected coefficient of current for branch m of

8 x.64REF.K_Brm 0.000 /
x side REF protection (m=1, 2, 3, 4).
Corrected coefficient of current from neutral CT

9 x. 64REF.K_NP 0.000 /
of x side REF protection

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5.1.1.6 WDIF Measurements
Access path:
MainMenu  “Measurements”  “Measurements1”  “WDIF Measurements”
“WDIF Measurements” is used to display measured values and corresponding phase angles of
winding differential protection.
Phase-A differential current of winding differential

1 87W.Ida 0.000 In
protection.
Phase-B differential current of winding differential

2 87W.Idb 0.000 In
protection.
Phase-C differential current of winding differential

3 87W.Idc 0.000 In
protection.
Residual differential current of winding differential

4 87W.3I0d 0.000 In
protection.
Phase-A restraint current of winding differential

5 87W.Ira 0.000 In
protection.
Phase-B restraint current of winding differential

6 87W.Irb 0.000 In
protection.
Phase-C restraint current of winding differential

7 87W.Irc 0.000 In
protection.
Residual restraint current of winding differential

8 87W.3I0r 0.000 In
protection.
Threshold of phase-A restraint current of winding

9 87W.Ia_Th 0.000 In
Threshold of phase-B restraint current of winding

10 87W.Ib_Th 0.000 In
Threshold of phase-C restraint current of winding

11 87W.Ic_Th 0.000 In
Threshold of residual restraint current of winding

12 87W.3I0_Th 0.000 In
Phase-A corrected current of branch m (m= 1,2, 3,

13 87W.Ia_Cr_Brm 0.000 In
Phase-B corrected current of branch m (m= 1,2, 3,

14 87W.Ib_Cr_Brm 0.000 In
Phase-C corrected current of branch m (m= 1,2, 3,

15 87W.Ic_Cr_Brm 0.000 In
Corrected calculated residual current for branch m

16 87W.3I0_Cr_Brm 0.000 In
(m=1, 2, 3, 4, 5) of winding differential protection.

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Angle between phase-A currents of branch 1 and

17 87W.Ang(Ia)_Br1-Brm branch m (m= 2, 3, 4, 5) of winding differential 0 deg
protection.
Angle between phase-B currents of branch 1 and

18 87W.Ang(Ib)_Br1-Brm branch m (m= 2, 3, 4, 5) of winding differential 0 deg
protection.
Angle between phase-C currents of branch 1 and

19 87W.Ang(Ic)_Br1-Brm branch m (m= 2, 3, 4, 5) of winding differential 0 deg
protection.
Angle between calculated residual current of

20 87W.Ang(3I0)_Br1-Brm branch 1 and branch m (m= 2, 3, 4, 5) of winding 0 deg
Corrected coefficient of current for branch m of

21 87W.K_Brm 0.000 /
winding differential protection. (m=1, 2, 3, 4, 5).
5.1.2 Power Value

Access path:
MainMenu  “Measurements”  “Measurements3”  “Power Measurements”
“Power Measurements” is used to display power values.
No. Symbol Definition Unit
1 x.P The primary value of active power (P) MW
2 x.Q The primary value of reactive power (Q) MVAr
3 x.S The primary value of apparent power (S) MVA
4 x.Cos The value of power factor (Cos) -
5.1.3 Temperature Value

Access path:
MainMenu  “Measurements”  “Measurements3”  “Temp Measurements”
“Temp Measurements” is used to display temperature values.
No. Symbol Definition Unit
1 26.T_PhA Calculated temperature of phase A. deg
2 26.T_PhB Calculated temperature of phase B. deg
3 26.T_PhC Calculated temperature of phase C. deg
5.2 Recording
5.2.1 Overview
This device provides the following recording functions:

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5 Management
1. Event recording
2. Disturbance recording
3. Present recording
All the recording information except waveform can be viewed on local LCD or by printing.
Waveform could only be printed or extracted with PCS-Explorer software tool and a waveform
analysis software.
5.2.2 Event Recording

5.2.2.1 Overview
The device can store the latest 1024 disturbance records, 1024 binary events, 1024 supervision
events and 1024 device logs. All the records are stored in non-volatile memory, and when the
available space is exhausted, the oldest record is automatically overwritten by the latest one.
5.2.2.2 Disturbance Records
When any protection element operates or drops off, such as fault detector, distance protection etc.,
they will be logged in event records.
5.2.2.3 Supervision Events
The device is under automatic supervision all the time. If there are any failure or abnormal
condition detected, such as, chip damaged, VT circuit failure and so on, it will be logged in event
records.
5.2.2.4 Binary Events
When there is a binary input is energized or de-energized, i.e., its state has changed from “0” to “1”
or from “1” to “0”, it will be logged in event records.
5.2.2.5 Device Logs
If an operator implements some operations on the device, such as reboot protective device,
modify setting, etc., they will be logged in event records.
5.2.3 Disturbance Recording

5.2.3.1 Application
Disturbance records can be used to have a better understanding of the behavior of the power
network and related primary and secondary equipment during and after a disturbance. Analysis of
the recorded data provides valuable information that can be used to improve existing equipment.
This information can also be used when planning for and designing new installations.
5.2.3.2 Design
A disturbance record consists of fault record and fault waveform. The disturbance record can be
initiated by fault detector element, tripping element or configurable signal [BI_TrigDFR].

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5 Management
5.2.3.3 Capacity and Information of Disturbance Records
The device can store up to 32 disturbance records with waveform in non-volatile memory. It is
based on first in first out queue that the oldest disturbance record will be overwritten by the latest
one.
For each disturbance record, the following items are included:
1. Sequence number
Each operation will be recorded with a sequence number in the record and displayed on LCD
screen.
2. Date and time of fault occurrence
The time resolution is 1ms using the relay internal clock synchronized via clock synchronized
device if connected. The date and time is recorded when a system fault is detected.
3. Relative operating time
An operating time (not including the operating time of output relays) is recorded in the record.
4. Faulty phase
5. Protection elements
5.2.3.4 Capacity and Information of Fault Waveform
MON module can store 32 pieces of fault waveform oscillogram in non-volatile memory. If a new
fault occurs when 32 fault waveform have been stored, the oldest will be overwritten by the latest
one.
Each fault record consists of all analog and digital quantities related to protection, such as original
current and voltage, differential current, alarm elements, and binary inputs and etc.
Each waveform recording includes pre-fault waveform that is determined by the setting
[Num_Cyc_PreTrigDFR] and post-fault waveform that is 250 cycles at least, and a completed
waveform recording can record 400 cycles at most. Each cycle waveform is high-frequency
recording at a rate of 1200Hz or 1440Hz (24 points per cycle).
5.2.4 Present Recording

Present recording is a waveform triggered manually on on the device′s LCD or remotely through
PCS-Explorer software. Recording content of present recording is same to that of disturbance
recording.
Each waveform recording includes pre-fault waveform that is determined by the setting
[Num_Cyc_PreTrigDFR] and 250-cycles post-fault waveform. Each cycle waveform is
high-frequency recording at a rate of 1200Hz or 1440Hz (24 points per cycle).

Date: 2015-06-26
6 Hardware Description
Table of Contents
6.1 Overview ........................................................................................................... 6-1
6.2 Typical Wiring .................................................................................................. 6-3
6.2.1 Conventional CT/VT Wiring (For Reference Only)............................................................... 6-3
6.2.2 ECT/EVT Wiring (For Reference Only) ................................................................................ 6-5
6.2.3 CT Requirement ................................................................................................................... 6-7
6.3 Plug-in Module Description ............................................................................ 6-8

6.3.1 PWR Plug-in Module (Power Supply) .................................................................................. 6-9
6.3.2 MON Plug-in Module (Monitor & Management) ................................................................. 6-11
6.3.3 AI Plug-in Module (AC Analog Input) ................................................................................. 6-14
6.3.4 DSP Plug-in Module (Protection Calculation) .................................................................... 6-59
6.3.5 DSP Plug-in Module (Fault Detector) ................................................................................. 6-60
6.3.6 BI Plug-in Module (Binary Input) ........................................................................................ 6-60
6.3.7 BO Plug-in Module (Binary Output).................................................................................... 6-67
6.3.8 DI Plug-in Module (DC Analog Input) ................................................................................. 6-71
6.3.9 MR Plug-in Module (Mechanical Relay Input/Output)........................................................ 6-74
6.3.10 NET-DSP module (Optional) ............................................................................................ 6-75
6.3.11 HMI Module ...................................................................................................................... 6-79
6.4 Tripping Output Group .................................................................................. 6-79
List of Figures
Figure 6.1-1 Hardware diagram .................................................................................................. 6-1
Figure 6.1-2 Front view of PCS-978 ........................................................................................... 6-3
Figure 6.1-3 Typical rear view of PCS-978 ................................................................................ 6-3
Figure 6.2-1 Typical wiring of PCS-978 (conventional CT/VT) ............................................... 6-4
Figure 6.2-2 Typical wiring of PCS-978 (ECT/EVT) .................................................................. 6-6

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Figure 6.3-1 View of PWR plug-in module ................................................................................ 6-9
Figure 6.3-2 Output contacts of PWR plug-in module .......................................................... 6-10
Figure 6.3-3 View of MON plug-in module .............................................................................. 6-11
Figure 6.3-4 Connection of communication terminal ............................................................ 6-13
Figure 6.3-5 Jumpers of clock synchronization port ............................................................ 6-13
Figure 6.3-6 Schematic diagram of CT circuit automatically closed ....................................... 6-14
Figure 6.3-7 View of AI plug-in module (NR1401) .................................................................. 6-15
Figure 6.3-8 Typical CT/VT connection 1 for two-windings transformer ............................ 6-16
Figure 6.3-9 Typical CT/VT connection 2 for two-windings transformer ............................ 6-18
Figure 6.3-10 Typical CT/VT connection 3 for two-windings transformer .......................... 6-20
Figure 6.3-13 Typical CT/VT connection 1 for three-windings transformer........................ 6-27
Figure 6.3-16 Typical CT/VT connection 1 for auto-transformer.......................................... 6-36
Figure 6.3-17 Typical CT/VT connection 2 for auto-transformer.......................................... 6-40
Figure 6.3-18 View of AI plug-in module (NR1408) ................................................................ 6-43
Figure 6.3-21 Typical CT/VT connection for three-windings transformer........................... 6-49
Figure 6.3-22 View of AI plug-in module (NR1409) ................................................................ 6-52
Figure 6.3-23 Typical CT/VT connection for two-windings transformer ............................. 6-53
Figure 6.3-24 Typical CT/VT connection for three-windings transformer........................... 6-56
Figure 6.3-25 View of DSP plug-in module ............................................................................. 6-59
Figure 6.3-26 View of DSP plug-in module ............................................................................. 6-60
Figure 6.3-27 Voltage dependence for binary inputs ............................................................ 6-61
Figure 6.3-28 Debouncing technique ...................................................................................... 6-61
Figure 6.3-29 View of BI plug-in module (NR1503) ................................................................ 6-62
Figure 6.3-30 View of BI plug-in module (NR1504) ................................................................ 6-63

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Figure 6.3-31 View of BI plug-in module (NR1508A) ............................................................. 6-65
Figure 6.3-32 View of BO plug-in module (NR1521A) ............................................................ 6-68
Figure 6.3-33 View of BO plug-in module (NR1521H) ............................................................ 6-68
Figure 6.3-34 View of BO plug-in module (NR1580A) ............................................................ 6-69
Figure 6.3-35 View of BO plug-in module (NR1523B) ............................................................ 6-70
Figure 6.3-36 View of BO plug-in module (NR1521C) ............................................................ 6-71
Figure 6.3-37 View of DI plug-in module (NR1410A) ............................................................. 6-72
Figure 6.3-38 View of DI plug-in module (NR1410B) ............................................................. 6-73
Figure 6.3-39 View of MR plug-in module (NR1536A/NR1536B) .......................................... 6-74
Figure 6.3-40 View of the NET-DSP module ........................................................................... 6-75
List of Tables
Table 6.1-1 module configuration .............................................................................................. 6-2
Table 6.3-1 Terminal definition and description of PWR plug-in module ........................... 6-10
Table 6.3-2 Encoding of IEC 61850-7-3 quality....................................................................... 6-76
PCS-978 Transformer Relay 6-c

Date: 2016-06-22
6-d PCS-978 Transformer Relay

Date: 2016-06-22
6.1 Overview
The PCS-978 adopts 32-bit microchip processor CPU as control core for logic calculation and
management function, meanwhile, adopts high-speed digital signal processor DSP to be in charge
of all the protection calculation. 24 points are sampled in every cycle and parallel processing of
sampled data can be realized in each sampling interval to ensure ultra-high reliability and safety of
the device.
Output Relay
Binary Input
External
Protection
Conventional CT/VT A/D Calculation
DSP
ECVT
Fault
A/D Detector Pickup
DSP Relay
ECVT
ETHERNET
LCD +E
GPS
Power
Uaux LED CPU
Supply
RJ45
Keypad
PRINT
Figure 6.1-1 Hardware diagram
The working process of the device is as follows: firstly, the current and voltage is converted into
small voltage signal and sent to DSP module after being filtered and converted by AD for
protection calculation and fault detector respectively. When DSP module completes all the
protection calculation, the result will be sent to 32-bit CPU on MON module to be recorded.
Protection DSP module carries out protection logic calculation, tripping output, and MON module
completes SOE (sequence of event) record, waveform recording, printing, communication
between protection and SAS and communication between HMI and CPU. The work process of
fault detector DSP module is similar to that of protection DSP module, and the only difference is,
when fault detector DSP module decides a fault detector picks up, only positive power supply of
output relay will be switched on.
The PCS-978 is comprised of intelligent modules, except that few particular modules’ (MON
module DSP module, and PWR module) position cannot be changed in the whole device, the
others like AI (analog input) module such as AC current, AC voltage, DC current, and etc., and IO
(input and output) module such as binary input, tripping output, signal output, and etc can be
flexibly configured according to the remained slot positions.

Date: 2016-06-22
Table 6.1-1 module configuration
No. ID Module description Remark

1 NR1101/NR1102 Management module (MON module) standard
2 NR1156 Protection calculation module (DSP module) standard
3 NR1156 Fault detector calculation module (DSP module) standard
4 NR1401 Analog input module (AI module) standard
5 NR1410 DC analog input module (DI module) option
6 NR1503/NR1504/NR1508 Binary input module (BI module) standard
7 NR1536 Mechanical relay module (MR module) option
8 NR1521/NR1523/NR1580 Binary output module (BO module) standard
9 NR1301 Power supply module (PWR module) standard
GOOSE and SV from merging unit by IEC61850-9-2
10 NR1136 option
(NET-DSP module)
11 Human machine interface module (HMI module) standard
 MON module provides functions like management function, completed event record, setting
management, and etc.
 DSP modules are totally the same, to carry out filtering, sampling and protection calculation
and fault detector calculation respectively.
 AI module converts AC current and voltage to low voltage signals with current transformers
and voltage transformers respectively.
 BI module provides binary input via opto-couplers with rating voltage among
24V/48V/110V/125V/220V/250V opto-coupler (configurable).
 BO module provides output contacts for tripping, and signal output contact for annunciation
signal, remote signal, fault and disturbance signal, operation abnormal signal etc.
 PWR module converts DC 250/220/125/110V into different DC voltage levels for various
modules of the equipment
 HMI module is comprised of LCD, keypad, LED indicator and test serial ports, and it is
convenient for user to perform human-machine interaction with equipment.
 NET-DSP module receives and sends GOOSE messages, sampled values (SV) from
merging unit by IEC61850-9-2 protocol.
PCS-978 is made of a 4U height 19” chassis for flush mounting. Components mounted on its front
include a 320×240 dot matrix LCD, a 9 button keypad, 20 LED indicators and a multiplex RJ45
port. A monolithic micro controller is installed in the equipment for these functions.
Following figures show front and rear views of PCS-978 respectively.

Date: 2016-06-22
1
HEALTHY
11
PCS-978
2 12
ALARM TRANSFORMER RELAY
3 13
4 14
C GRP
5 15
6 16
ENT
ES
7 17
8 18
9 19
10 20
Figure 6.1-2 Front view of PCS-978
20 LED indicators are, from top to bottom, operation (HEALTHY), self-supervision (ALARM),
others are configurable. For the 9-button keypad, “ENT” is “enter”, “GRP” is “group number” and
“ESC” is “escape”.
NR1102M NR1156 NR1156 NR1401 NR1401 NR1504 NR1521 NR1521 NR1523B NR1301
1 2 3 1 2 3 5V OK ALM
ETHERNET
4 5 6 4 5 6 BO_ALM BO_FAIL
ON
OFF
DANGER DANGER
1 BO_COM1
2 BO_FAIL
3 BO_ALM
4 BO_COM2
5 BO_FAIL
6 BO_ALM
7 OPTO+
8 OPTO-
9
10 PWR+
11 PWR-
12 GND
Figure 6.1-3 Typical rear view of PCS-978
6.2 Typical Wiring
6.2.1 Conventional CT/VT Wiring (For Reference Only)
NR1102 NR1156 NR1156 NR1401 NR1401 NR1504 NR1521 NR1521 NR1523 NR1301
MON module
PWR module
DSP module
DSP Module
BO module
BO module
BO module
AI module
AI module
BI module
Slot No.
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 P1

Date: 2016-06-22
The following typical wiring is given based on above hardware configuration
0401
0402
0403
0404
0405
0406
0407
0408
0409
0410
0411
0412
0413
0414
0415
0416
0417
0418
0419
0420
0421
0422
0423
0424
Ua
Ub
Uc
Ia
Ib
Ia
Ib
Ia
Ib
Ic
Ic
Ic
AI plug-in module
1201 Power supply supervision 1301

BO_01
1302
1202 + BI_01 1303

BO_02
1304
*BI plug-in module can be independent common terminal

1305
…
BO_03
1306
1207 + BI_06 ……
1208 1317
Not used BO_09
1318
1209 + BI_07 1319
BO_10
BO plug-in module for trip

1320
…
1321
BO_11
1214 + BI_12 1322
1215 1401
Not used BO_01
1402
1216 + BI_13 1403
BO_02
1404
…
1405
BO_03
1221 + BI_18 1406
……
1222 - 1417
BO_09
1418
PWR+ P110 1419
External DC power Power BO_10
supply P111 Supply 1420
PWR-
P107 1421
OPTO+ BO_11
Power supply for 1422
opto-coupler (24V) P108
OPTO-
P102 BO_FAIL
P103 1501
BO_ALM BO_01
P101 1502
COM
P105 1503
BO_FAIL BO_02
BO plug-in module for signal
P106 1504
BO_ALM
P104 1505
COM BO_03
P112 1506
Transducer_24V_Return
……
To_Transducer_24V
Grounding Screw 1517

Grounding Bus BO_09
1518
1519
Optional optical or electrical Ethernet to SCADA
COM(optonal)
485-1A 0101 BO_10

1520
cable with single point earthing
To the screen of other coaxial
485-1B 0102
1521
SGND 0103 BO_11
1522
0104
SYN+ 0101 S3
Clock SYN
Input_-
Jumper
SYN- 0102 0-20mA

SGND 0103 Input_+ or 0-5V
S1
0104
Current input+
RTS 0105
PRINT
PT100
Current input-
TXD 0106
Measurement input+
SGND 0107 Multiplex RJ45 (Front) Measurement input-
AI plug-in module
3I0
3I0
3I0
Ub
Ua
Uc
Reserved voltage input

Ib
Ia
Ic
0624
0623
0622
0621
0620
0619
0618
0617
0616
0615
0614
0613
0612
0611
0610
0609
0608
0607
0606
0605
0604
0603
0602
0601
Figure 6.2-1 Typical wiring of PCS-978 (conventional CT/VT)

Date: 2016-06-22
PCS-978 (conventional CT/VT and conventional binary output)
Slot No. 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 P1
Module ID NR1102 NR1156 NR1156 NR1401 NR1401 NR1504 NR1521 NR1521 NR1523B NR1301
MON DSP DSP AI AI BI BO BO BO PWR
PCS-978 (conventional CT/VT and GOOSE binary output)
Slot No. 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 P1
Module ID NR1102 NR1156 NR1156 NR1401 NR1401 NR1136 NR1504 NR1521 NR1521 NR1523B NR1301
NET-
MON DSP DSP AI AI BI BO BO BO PWR
DSP
6.2.2 ECT/EVT Wiring (For Reference Only)
Typical configuration of PCS-978 connected to ECT/EVT configuration is given as below for

reference.
NR1102 NR1156 NR1156 NR1136 NR1136 NR1504 NR1521 NR1521 NR1523 NR1301
NET-DSP Module
NET-DSP Module
MON module
PWR module
DSP module
DSP Module
BO module
BO module
BO module
BI module
Slot No.
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 P1
The following typical wiring is given based on above hardware configuration

Date: 2016-06-22
MU
RX TX …… RX TX RX TX RX TX …… RX TX RX TX
Channel 8 Channel 2 Channel 1 Channel 8 Channel 2 Channel 1
RX
NET-DSP plug-in module (optional IRIG-B)
1201 Power supply supervision 1301

BO_01
1302
1202 + BI_01 1303

BO_02
1304
*BI plug-in module can be independent common terminal

1305
… BO_03
1306
1207 + BI_06 ……
1208 1317
Not used BO_09
1318
1209 + BI_07 1319
BO_10
BO plug-in module for trip

1320
…
1321
BO_11
1214 + BI_12 1322
1215 1401
Not used BO_01
1402
1216 + BI_13 1403
BO_02
1404
…
1405
BO_03
1221 + BI_18 1406
……
1222 - 1417
BO_09
1418
PWR+ P110 1419
External DC power Power BO_10
supply P111 Supply 1420
PWR-
P107 1421
OPTO+ BO_11
Power supply for 1422
opto-coupler (24V) P108
OPTO-
P102 BO_FAIL
P103 1501
BO_ALM BO_01
P101 1502
COM
P105 1503
BO_FAIL BO_02
BO plug-in module for signal
P106 1504
BO_ALM
P104 1505
COM BO_03
P112 1506
…… Transducer_24V_Return
To_Transducer_24V
Grounding Screw 1517
Grounding Bus BO_09
1518
1519
Optional optical or electrical Ethernet to SCADA
COM(optonal)
485-1A 0101 BO_10

1520
485-1B 0102
1521
SGND 0103 BO_11
1522
0104
SYN+ 0101 S3
Clock SYN
Input_-
Jumper
SYN- 0102 0-20mA

SGND 0103 Input_+ or 0-5V
S1
0104
Current input+
RTS 0105
PRINT
PT100
Current input-
TXD 0106
Measurement input+
SGND 0107 Multiplex RJ45 (Front) Measurement input-
Figure 6.2-2 Typical wiring of PCS-978 (ECT/EVT)

Date: 2016-06-22
PCS-978 ECT/EVT, GOSSE, with conventional BI and BO
Slot No. 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 P1
Module ID NR1102 NR1151 NR1151 NR1136 NR1136 NR1504 NR1521 NR1521 NR1523B NR1301
NET- NET-
MON DSP DSP BI BO BO BO PWR
DSP DSP
PCS-978 ECT/EVT, GOSSE, without conventional BI and BO
Slot No. 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 P1
Module ID NR1102 NR1151 NR1151 NR1136 NR1136 NR1504 NR1301

NET- NET-
MON DSP DSP BI PWR
DSP DSP
In the protection system adopting electronic current and voltage transformer (ECT/EVT), the
merging unit will merge the sample data from ECT/EVT, and then send it to the device through
multi-mode optical fibre. Two DSP modules respectively receive the data from merging unit
through the optical-fibre interface to complete the protection calculation and fault detector.
The difference between the hardware platform based on ECT/EVT and the hardware platform
based on conventional CT/VT lies in the receiving module of sampled values only, and the device
receives the sampled value from merging unit through multi-mode optical fibre.
6.2.3 CT Requirement
-Rated primary current Ipn:
According to the rated current or maximum load current of primary apparatus.
-Rated continuous thermal current Icth:
According to the maximum load current
-Rated short-time thermal current Ith and rated dynamic current Idyn:
According to the maximum fault current
-Rated secondary current Isn
-Accuracy limit factor Kalf:
Ipn Rated primary current (amps)

Icth Rated continuous thermal current (amps)
Ith Rated short-time thermal current (amps)
Idyn Rated dynamic current (amps)
Isn Rated secondary current (amps)
Kalf Accuracy limit factor Kalf=Ipal/Ipn
IPal Rated accuracy limit primary current (amps)
Performance verification
Esl > Esl′
Rated secondary limiting e.m.f (volts)

Esl
Esl = kalf×Isn×(Rct+Rbn)

Date: 2016-06-22
Kalf Accuracy limit factor (Kalf=Ipal/Ipn)

IPal Rated accuracy limit primary current (amps)
Rct Current transformer secondary winding resistance. (ohms)
Rated resistance burden (ohms)
Rbn
Rbn=Sbn/Isn2
Sbn Rated burden (VAs)
Required secondary limiting e.m.f (volts)

Esl′
Esl′ = k×Ipcf ×Isn×(Rct+Rb)/Ipn
k stability factor = 2
Protective checking factor current (amps)
Ipcf
Same as the maximum prospective fault current
Rct Current transformer secondary winding resistance. (ohms)
Real resistance burden (ohms)
Rb
Rb=Rr+2×RL+Rc
Rc Contact resistance, 0.05-0.1 ohm (ohms)
RL Resistance of a single lead from relay to current transformer (ohms)
Rr Impedance of relay phase current input (ohms)
For example:
1. Kalf=30, Isn=5A, Rct=1ohm, Sbn=60VA
Esl = kalf×Isn×(Rct+Rbn) = kalf×Isn×(Rct+ Sbn/ Isn2)
= 30×5×(1+60/25)=510V
2. Ipcf=40000A, RL=0.5ohm, Rr=0.1ohm, Rc=0.1ohm, Ipn=2000A
Esl′ = 2×Ipcf×Isn×(Rct+Rb)/Ipn
= 2×Ipcf ×Isn×(Rct+(Rr+2×RL+Rc))/Ipn
= 2×40000×5×(1+(0.1+2×0.5+0.1))/2000=440V
Thus, Esl > Esl′
6.3 Plug-in Module Description
The device consists of PWR plug-in module, MON plug-in module, DSP plug-in module, AI plug-in
module, BI plug-in module, BO plug-in module, MR plug-in module, DI plug-in module and
NET-DSP plug-in module. Terminal definitions and application of each plug-in module are
introduced as follows.

Date: 2016-06-22
6.3.1 PWR Plug-in Module (Power Supply)

PWR module is a DC/DC converter with electrical insulation between input and output. It has an
input voltage range as described in Chapter 2 “Technical Data”. The standardized output voltages
are +5V and +24V DC. The tolerances of the output voltages are continuously monitored.
The +5V DC output provides power supply for all the electrical elements that need +5V DC power
supply in this device.
The use of an external miniature circuit breaker is recommended. The miniature circuit breaker
must be in the on position when the device is in operation and in the off position when the device is
in cold reserve.
A 12-pin connector is fixed on PWR module. The terminal definition of the connector is described
as below.
NR1301
5V OK ALM
BO_ALM BO_FAIL
ON
OFF
1 BO_COM1
2 BO_FAIL
3 BO_ALM
4 BO_COM2
5 BO_FAIL
6 BO_ALM
7 OPTO+
8 OPTO-
9
10 PWR+
11 PWR-
12 GND
Figure 6.3-1 View of PWR plug-in module
The power switch in the dotted box of above figure maybe is not existed.

Date: 2016-06-22
01
BO_FAIL
02
BO_ALM
03
04
BO_FAIL
05
BO_ALM
06
Figure 6.3-2 Output contacts of PWR plug-in module
Terminal definition and description is shown as follows:
Table 6.3-1 Terminal definition and description of PWR plug-in module
Terminal No. Symbol Description
01 BO_COM1 Common terminal 1
02 BO_FAIL Device failure output 1 (01-02, NC)
03 BO_ALM Device abnormality alarm output 1 (01-03, NO)
04 BO_COM2 Common terminal 2
05 BO_FAIL Device failure output 2 (04-05, NC)
06 BO_ALM Device abnormality alarm output 2 (04-06, NO)
07 OPTO+ Positive power supply for BI module (24V)
08 OPTO- Negative power supply for BI module (24V)
09 Blank Not used
10 PWR+ Positive input of power supply for the device (250V/220V/125V/110V)
11 PWR- Negative input of power supply for the device (250V/220V/125V/110V)
12 GND Grounded connection of the power supply
NOTICE!
The standard rated voltage of PWR module is self-adaptive to 88~300 Vdc. If input
voltage is out of range, an alarm signal (Fail_Device) will be issued. For non-standard
rated voltage power supply module please specify when place order, and check if the
rated voltage of power supply module is the same as the voltage of power source
before the device being put into service.
PWR module provides terminal 12 and grounding screw for device grounding. Terminal
12 shall be connected to grounding screw and then connected to the earth copper bar
of panel via dedicated grounding wire.
Effective grounding is the most important measure for a device to prevent EMI, so
effective grounding must be ensured before the device is put into service.
PCS-978, like almost all electronic relays, contains electrolytic capacitors. These
capacitors are well known to be subject to deterioration over time if voltage is not

Date: 2016-06-22
applied periodically. Deterioration can be avoided by powering the relays up once a

year.
6.3.2 MON Plug-in Module (Monitor & Management)
MON module consists of high-performance built-in processor, FLASH, SRAM, SDRAM, Ethernet
controller and other peripherals. Its functions include management of the complete device, human
machine interface, communication and waveform recording etc.
MON module uses the internal bus to receive the data from other modules of the device. It
communicates with the LCD module by RS-485 bus. This module comprises 100BaseT Ethernet
interfaces, RS-485 communication interfaces that exchange information with above system by
using IEC 61850, PPS/IRIG-B differential time synchronization interface and RS-232 printing
interface.
Modules with various combinations of memory and interface are available as shown in the table
below.
CAUTION!
Do NOT look into the end of an optical fiber connected to an optical port.
Do NOT look into an optical port/connector.
A direct sight to laser light may cause temporary or permanent blindness.
NR1102M NR1102N NR1101D NR1101F
TX
ETHERNET
ETHERNET ETHERNET
RX
TX
RX
ETHERNET
Figure 6.3-3 View of MON plug-in module

Date: 2016-06-22
Module ID Memory Interface Terminal No. Usage Physical Layer

4 RJ45 Ethernet To SCADA
01 SYN+
02 SYN- To clock Twisted pair wire
RS-485/TTL
03 SGND synchronization
NR1102M 256M DDR
04
05 RTS
RS-232 06 TXD To printer Cable
07 SGND
2 RJ45 Ethernet To SCADA Twisted pair wire
2 FO Ethernet To SCADA Optical fiber ST
01 SYN+
02 SYN- To clock
RS-485/TTL Twisted pair wire
NR1102N 256M DDR 03 SGND synchronization
04
05 RTS
RS-232 06 TXD To printer Cable
07 SGND
01 A
02 B
RS-485 To SCADA
03 SGND
04
05 A
Twisted pair wire
06 B
RS-485 To SCADA Cable
07 SGND
NR1101D 256M DDR 08
09 SYN+
10 SYN- To clock
RS-485/TTL
12
13 RTS
14 TXD
RS-232 To printer Cable
15 SGND
16
01 A
NR1101F 02 B
RS-485 To SCADA
(Support 03 SGND Twisted pair wire
256M DDR
independent 04 Cable
MAC) 05 A
RS-485 06 B To SCADA
07 SGND

Date: 2016-06-22
08
09 SYN+
10 SYN- To clock
RS-485/TTL
12
13 RTS
14 TXD
RS-232 To printer Cable
15 SGND
16
The correct method of connection is shown in Figure 6.3-4. Generally, the shielded cables with two
pairs of twisted pairs inside shall be applied. One pair of the twisted pairs are respectively used to
connect the “+” and “–” terminals of differential signal; the other pair of twisted pairs are used to
connect the signal ground of the interface, i.e. connect the signal groundings of all the devices
connected with the bus to the twisted pair. The module reserves a free terminal for all the
communication ports; the blank terminal does not need to be connected.
Twisted pair wire

A 01
B 02
COM
SGND 03
04
Twisted pair wire

SYN+ 01 Clock SYN
SYN- 02
SGND 03
04
Cable
RTS 05
PRINT
TXD 06
SGND 07
Figure 6.3-4 Connection of communication terminal
Pin1
Pin2
Pin3
Figure 6.3-5 Jumpers of clock synchronization port

Date: 2016-06-22
NOTICE!
As shown in Figure 6.3-5, the external receiving mode of IRIG-B differential time
synchronization interface can be set by the jumper J8&J9.
Jumper RS-485 TTL

J8 Pin-1 and Pin-2 are connected. (RS-485+) Pin-2 and Pin-3 are connected. (TTL+)
J9 Pin-1 and Pin-2 are connected. (RS-485-) Pin-2 and Pin-3 are connected. (TTL-)
6.3.3 AI Plug-in Module (AC Analog Input)

AI module can transform these high AC input values to relevant low AC output value for the DSP
module. The transformers are used both to step-down the currents and voltages to levels
appropriate to the electronic circuitry of this device and to provide effective isolation between this
device and the power system. A low pass filter circuit is connected to each transformer (CT or VT)
secondary circuit for reducing the noise of each analog AC input signal. However, the module is
not required if the device is used with ECT/EVT.
For AI module, if the plug is not put in the socket, external CT circuit is closed itself. Just shown as
below:
Plug
Socket
In
Out
plug is not put in the socket
In
Out
Put the plug in the socket
Figure 6.3-6 Schematic diagram of CT circuit automatically closed
There are four types of AI module with rating 1A (NR1401), 5A (NR1401), 1A/5A (NR1408) or
1A/5A (NR1409). Please declare which kind of AI module is needed before ordering. Maximum

Date: 2016-06-22
linear range of the current converter is 40In.
NOTICE!
Because the rated value of the input current transformer is optional, it is necessary to
check whether the rated values of the current transformer inputs are accordant to the
demand of the engineering before putting the device into operation.
 NR1401
It has 12 input transformers, and each channel can be configured as a specified current or voltage
channel by PCS-Explorer software according to user requirements. There are four kinds of typical
application module as following shows.
1. Type A: 6I and 6U, 6 current channels and 6 voltage channels
2. Type B: 9I and 3U, 9 current channels and 3 voltage channels
3. Type C: 12I, 12 current channels
4. Type D: 12U, 12 voltage channels
A 24-pin connector is fixed on the front of this module, and its pin definition is described as below.
01 I1 02 I1n 01 I1 02 I1n 01 I1 02 I1n 01 U1 02 U1n

NR1401
03 I2 04 I2n 03 I2 04 I2n 03 I2 04 I2n 03 U2 04 U2n
05 I3 06 I3n 05 I3 06 I3n 05 I3 06 I3n 05 U3 06 U3n
07 I4 08 I4n 07 I4 08 I4n 07 I4 08 I4n 07 U4 08 U4n
09 I5 10 I5n 09 I5 10 I5n 09 I5 10 I5n 09 U5 10 U5n
11 I6 12 I6n 11 I6 12 I6n 11 I6 12 I6n 11 U6 12 U6n
13 U1 14 U1n 13 I7 14 I7n 13 I7 14 I7n 13 U7 14 U7n
15 U2 16 U2n 15 I8 16 I8n 15 I8 16 I8n 15 U8 16 U8n
17 U3 18 U3n 17 I9 18 I9n 17 I9 18 I9n 17 U9 18 U9n
19 U4 20 U4n 19 U1 20 U1n 19 I10 20 I10n 19 U10 20 U10n
21 U5 22 U5n 21 U2 22 U2n 21 I11 22 I11n 21 U11 22 U11n
23 U6 24 U6n 23 U3 24 U3n 23 I12 24 I12n 23 U12 24 U12n
Figure 6.3-7 View of AI plug-in module (NR1401)
NOTICE!
In above figure, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12 and U1, U2, U3, U4, U5, U6,
U7, U8, U9, U10, U11, U12 are polarity terminals of corresponding relevant voltage and
current inputs respectively.
1. Typical application 1 for two-windings transformer

Date: 2016-06-22
In this application, there are one branch at HV side and two branches at LV side without voltage
input.
AI Module configuration:
Slot No. Module ID Type

04 NR1401 12 current channels
The CT/VT wiring diagram for the application is shown below.
LV side 2
*
A
*
B
*
C
HV side LV side 1
*
*
A A
*
*
B B
*
*
C C
*
0420 0422
0419 0421
0401 0407
0402 0408
0403 0409
0404 0410
0405 0411
0406 0412
0413
0414
0415
0416
0417
PCS-978 0418
Figure 6.3-8 Typical CT/VT connection 1 for two-windings transformer
The following table lists the pin definition of AI module.
Pin No. Original definition New definition Description
0401 I1 Ia_H The phase A current input of HV side (polarity).
0402 I1n Ian_H The phase A current input of HV side.
0403 I2 Ib_H The phase B current input of HV side (polarity).
0404 I2n Ibn_H The phase B current input of HV side.
0405 I3 Ic_H The phase C current input of HV side (polarity).
0406 I3n Icn_H The phase C current input of HV side.

Date: 2016-06-22
0407 I4 Ia_L1 The phase A current input of LV side 1 (polarity).
0408 I4n Ian_L1 The phase A current input of LV side 1.
0409 I5 Ib_L1 The phase B current input of LV side 1 (polarity).
0410 I5n Ibn_L1 The phase B current input of LV side 1.
0411 I6 Ic_L1 The phase C current input of LV side 1 (polarity).
0412 I6n Icn_L1 The phase C current input of LV side 1.
0419 I10 3I0_H The neutral current input of HV side (polarity).
0420 I10n 3I0n_H The neutral current input of HV side.
0421 I11 3I0_L The neutral current input of LV side (polarity).
0422 I11n 3I0n_L The neutral current input of LV side.
0423 I12 Reserved
0424 I12n Reserved
In this application, there is one branch at HV side and LV side respectively with voltage input at HV
side.

04 NR1401 9 current channels and 3 voltage channels

Date: 2016-06-22
HV side LV side
*
A A
*
B B
*
C C
*
0414 0416
0413 0415
0401 0407
0402 0408
0403 0409
0404 0410
0405 0411
0406 0412
0419
0420
0421
0422
0423
0424 PCS-978
0407 I4 Ia_L The phase A current input of LV side (polarity).
0408 I4n Ian_L The phase A current input of LV side.
0409 I5 Ib_L The phase B current input of LV side (polarity).
0410 I5n Ibn_L The phase B current input of LV side.
0411 I6 Ic_L The phase C current input of LV side (polarity).
0412 I6n Icn_L The phase C current input of LV side.

Date: 2016-06-22
0417 I9 Reserved
0418 I9n Reserved
0419 U1 Ua_H The phase A voltage input of HV side (polarity).
0420 U1n Uan_H The phase A voltage input of HV side.
0421 U2 Ub_H The phase B voltage input of HV side (polarity).
0422 U2n Ubn_H The phase B voltage input of HV side.
0423 U3 Uc_H The phase C voltage input of HV side (polarity).
0424 U3n Ucn_H The phase C voltage input of HV side.
side.

04 NR1401 9 current inputs and 3 voltage inputs

Date: 2016-06-22
HV side LV side
*
A A
*
B B
*
C C
0416 0415
0401 0407
0402 0408
0403 0409
0404 0410
0405 0411
0406 0412
0419
0420
0421
0422
0423
0424 PCS-978

Date: 2016-06-22
0413 I7 Reserved
0414 I7n Reserved
0417 I9 Reserved
0418 I9n Reserved
and LV sides.


Date: 2016-06-22
HV side LV side
*
A A
*
B B
*
C C
*
0608 0612
0607 0611
0401 0601
0402 0602
0403 0603
0404 0604
0405 0605
0406 0606
0619 0623
0620 0624
0413 0613
0414 0614
0415 0615
0416 0616
0417 0617
0418 PCS-978 0618
Slot 04&05
0407 I4 Reserved
0408 I4n Reserved
0409 I5 Reserved
0410 I5n Reserved
0411 I6 Reserved
0412 I6n Reserved

Date: 2016-06-22
0419 U4 Reserved
0420 U4n Reserved
0421 U5 Reserved
0422 U5n Reserved
0423 U6 Reserved
0424 U6n Reserved
Slot 06&07
0609 I5 Reserved
0610 I5n Reserved
0613 U1 Ua_L The phase A voltage input of LV side (polarity).
0614 U1n Uan_L The phase A voltage input of LV side.
0615 U2 Ub_L The phase B voltage input of LV side (polarity).
0616 U2n Ubn_L The phase B voltage input of LV side.
0617 U3 Uc_L The phase C voltage input of LV side (polarity).
0618 U3n Ucn_L The phase C voltage input of LV side.
0619 U4 3U0_H The residual voltage input of HV side (polarity).
0620 U4n 3U0n_H The residual voltage input of HV side.
0621 U5 Reserved
0622 U5n Reserved

Date: 2016-06-22
0623 U6 3U0_L The residual voltage input of LV side (polarity).
0624 U6n 3U0n_L The residual voltage input of LV side.
and LV sides.

HV side LV side
*
*
A A
*
*
B B
*
*
C C
0612 0611
0401 0601
0402 0602
0403 0603
0404 0604
0405 0605
0406 0606
0619 0623
0620 0624
0413 0613
0414 0614
0415 0615
0416 0616
0417 0617
0418 PCS-978 0618
Slot 04&05

Date: 2016-06-22
0407 I4 Reserved
0408 I4n Reserved
0409 I5 Reserved
0410 I5n Reserved
0411 I6 Reserved
0412 I6n Reserved
0419 U4 Reserved
0420 U4n Reserved
0421 U5 Reserved
0422 U5n Reserved
0423 U6 Reserved
0424 U6n Reserved
Slot 06&07
0607 I4 Reserved
0608 I4n Reserved

Date: 2016-06-22
0609 I5 Reserved
0610 I5n Reserved
0619 U4 3U0_H The residual current input of HV side (polarity).
0620 U4n 3U0n_H The residual current input of HV side.
0621 U5 Reserved
0622 U5n Reserved
0623 U6 3U0_L The residual current input of LV side (polarity).
0624 U6n 3U0n_L The residual current input of LV side.
6. Typical application 1 for three-windings transformer
In this application, there is one branch at HV side, MV side and LV side respectively with voltage
input at HV side, MV side and LV side.


Date: 2016-06-22
C
A
B
LV side
* * *
HV side MV side
*
*
A A
*
*
B B
*
*
C C
*
0610
0608
0607 0609
0401 0407
0402 0408
0403 0409
0404 0410
0405 0411
0406 0412
0619 0621
0620 0622
0413 0419
0414 0420
0415 0421
0416 0422
0417 0423
0418 0424
0601
0602
0603
0604
0605
0606
0623
0624
0613
0614
0615
0616
0617
PCS-978 0618
Figure 6.3-13 Typical CT/VT connection 1 for three-windings transformer
The following tables list the pin definition of AI module.
Slot 04&05

Date: 2016-06-22
0407 I4 Ia_M The phase A current input of MV side (polarity).
0408 I4n Ian_M The phase A current input of MV side.
0409 I5 Ib_M The phase B current input of MV side (polarity).
0410 I5n Ibn_M The phase B current input of MV side.
0411 I6 Ic_M The phase C current input of MV side (polarity).
0412 I6n Icn_M The phase C current input of MV side.
0419 U4 Ua_M The phase A voltage input of MV side (polarity).
0420 U4n Uan_M The phase A voltage input of MV side.
0421 U5 Ub_M The phase B voltage input of MV side (polarity).
0422 U5n Ubn_M The phase B voltage input of MV side.
0423 U6 Uc_M The phase C voltage input of MV side (polarity).
0424 U6n Ucn_M The phase C voltage input of MV side.
Slot 06&07
0609 I5 3I0_M The neutral current input of MV side (polarity).

Date: 2016-06-22
0610 I5n 3I0n_M The neutral current input of MV side.
0611 I6 Reserved
0612 I6n Reserved
0621 U5 3U0_M The residual voltage input of MV side (polarity).
0622 U5n 3U0n_M The residual voltage input of MV side.

04 NR1401 12 current inputs
06 NR1401 12 voltage inputs

Date: 2016-06-22
C
A
B
LV side
* * *
HV side MV side
*
*
A A
*
*
B B
*
*
C C
*
0422
0419
0420 0421
0401 0413
0402 0414
0403 0415
0404 0416
0405 0417
0406 0418
0619 0621
0620 0622
0601 0613
0602 0614
0603 0615
0604 0616
0605 0617
0606 0618
0407
0408
0409
0410
0411
0412
0623
0624
0607
0608
0609
0610
0611
PCS-978 0612
Slot 04&05

Date: 2016-06-22
0423 I12 Reserved
0424 I12n Reserved
Slot 06&07

Date: 2016-06-22
In this application, there are two branches at HV side, and one branch at MV side and LV side with
voltage input at HV side, MV side and LV side.


Date: 2016-06-22
C
A
B
LV side
* * *
HV
side2
*
A
*
B
*
MV side
*
*
A A
*
*
B B
*
*
C C
HV
side1
*
0614 0616
0613 0615
0413 0601
0414 0602
0415 0603
0416 0604
0417 0605
0418 0606
0401 0419
0402 0420
0403 0421
0404 0422
0405 0423
0406 0424
0407 0607
0408 0608
0409 0609
0410 0610
0411 0611
0412 0612
0619
0620
0621
0622
0623
PCS-978 0624
Slot 04&05
0401 I1 Ia_H1 The phase A current input of HV side 1 (polarity).
0402 I1n Ian_H1 The phase A current input of HV side 1.
0403 I2 Ib_H1 The phase B current input of HV side 1 (polarity).
0404 I2n Ibn_H1 The phase B current input of HV side 1.
0405 I3 Ic_H1 The phase C current input of HV side 1 (polarity).

Date: 2016-06-22
0406 I3n Icn_H1 The phase C current input of HV side 1.
Slot 06&07

Date: 2016-06-22
0617 I9 Reserved
0618 I9n Reserved
9. Typical application 1 for auto-transformer
In this application, there are two branches at HV side, MV side and LV side with voltage input at
HV side, MV side and LV side.


Date: 2016-06-22
C
A
B
*
*
LV side 2
1
* LV side
C
A
B
*
*
0623
0624
0802
0801
0804
0803
0806
0805
0808
0807
0810
0809
0812
0811
0613
0614
PCS-978
0615
0616
0606
0605
0604
0603
0602
0601
0612
0611
0610
0609
0608
0607
0617
0618
HV side 2
A *
* A
B *
* B
C *
HV side 1
A * * * C
* A MV side 2
B * *
* B
C * *
* C
*
MV side 1
0418 0416 0414 0620
0417 0415 0413 0619

0401
0402
0403 0813
0404 0814
PCS-978
0405 0815
0406 0816
0407 0817
0408 0818
0409 0819
0410 0820
0411 0621
0412 0622
0419
0420
0421
0422
0423
0424
Figure 6.3-16 Typical CT/VT connection 1 for auto-transformer
Slot 04&05

Date: 2016-06-22
0406 I3n Icn_H1 The phase C current input of HV side1.
Slot 06&07
0601 I1 Ia_M1 The phase A current input of MV side 1 (polarity).
0602 I1n Ian_M1 The phase A current input of MV side 1.
0603 I2 Ib_M1 The phase B current input of MV side 1 (polarity).
0604 I2n Ibn_M1 The phase B current input of MV side 1.
0605 I3 Ic_M1 The phase C current input of MV side 1 (polarity).
0606 I3n Icn_M1 The phase C current input of MV side1.

Date: 2016-06-22
0612 I6n Icn_M2 The phase C current input of MV side 2.
Slot 08&09
0806 I3n Icn_L1 The phase C current input of LV side1.
0813 I7 Ia_CW The phase A current input of common winding (polarity).
0814 I7n Ian_CW The phase A current input of common winding.
0815 I8 Ib_CW The phase B current input of common winding (polarity).
0816 I8n Ibn_CW The phase B current input of common winding.

Date: 2016-06-22
0817 I9 Ic_CW The phase C current input of common winding (polarity).
0818 I9n Icn_CW The phase C current input of common winding.
0819 I10 3I0_CW Neutral current input of common winding (polarity).
0820 I10n 3I0n_CW Neutral current input of common winding.
0821 I11 Reserved
0822 I11n Reserved
0823 I12 Reserved
0824 I12n Reserved
10. Typical application 2 for auto-transformer
In this application, there are two branches at HV side, MV side and LV side with voltage input at
HV side, MV side and LV side.

04 NR1401 12 voltage inputs

Date: 2016-06-22
C
A
B
*
*
LV side 2
1
* LV side
C
A
B
*
*
0423
0424
0802
0801
0804
0803
0806
0805
0808
0807
0810
0809
0812
0811
0413
0414
PCS-978
0415
0416
0618
0617
0616
0615
0614
0613
0624
0623
0622
0621
0620
0619
0417
0418
HV side 2
A *
* A
B *
* B
C *
HV side 1
A * * * C
* A MV side 2
B * *
* B
C * *
* C
*
MV side 1
0406 0404 0402 0420
0405 0403 0401 0419

0601
0602
0603 0813
0604 0814
PCS-978
0605 0815
0606 0816
0607 0817
0608 0818
0609 0819
0610 0820
0611 0421
0612 0422
0407
0408
0409
0410
0411
0412
Figure 6.3-17 Typical CT/VT connection 2 for auto-transformer
Slot 04&05

Date: 2016-06-22
Slot 06&07
0606 I3n Icn_H1 The phase C current input of HV side1.

Date: 2016-06-22
0618 I9n Icn_M1 The phase C current input of MV side1.
0624 I12n Icn_M2 The phase C current input of MV side 2.
Slot 08&09
0806 I3n Icn_L1 The phase C current input of LV side1.
0813 I7 Ia_CW The phase A current input of common winding (polarity).
0814 I7n Ian_CW The phase A current input of common winding.
0815 I8 Ib_CW The phase B current input of common winding (polarity).
0816 I8n Ibn_CW The phase B current input of common winding.

Date: 2016-06-22
0817 I9 Ic_CW The phase C current input of common winding (polarity).
0818 I9n Icn_CW The phase C current input of common winding.
0819 I10 3I0_CW Neutral current input of common winding (polarity).
0820 I10n 3I0n_CW Neutral current input of common winding.
0821 I11 Reserved
0822 I11n Reserved
0823 I12 Reserved
0824 I12n Reserved
 NR1408
It has 4 groups of current input channels and 4 groups of voltage input channels, and terminal 01
(or 03), 05 (or 07), 09 (or 11), 13 (or 15), 17, 19, 21 and 23 are polarity marks. A 24-pin connector
is fixed on the front of this module, and its pin definition is described as below.
I1-1A 01 I1n-1A 02
NR1408
I1-5A 03 I1n-5A 04
I2-1A 05 I2n-1A 06
I2-5A 07 I2n-5A 08
I3-1A 09 I3n-1A 10
I3-5A 11 I3n-5A 12
I4-1A 13 I4n-1A 14
I4-5A 15 I4n-5A 16
U1 17 U1n 18
U2 19 U2n 20
U3 21 U3n 22
U4 23 U4n 24
side.


Date: 2016-06-22

HV side LV side
*
A A
*
B B
*
C C
*
(0416) 0414 0614 (0616)
(0415) 0413 0613 (0615)

0401 (0403) (0603) 0601
0402 (0404) (0604) 0602
0405 (0407) (0607) 0605
0406 (0408) (0608) 0606
0409 (0411) (0611) 0609
0410 (0412) (0612) 0610
0417
0418
0419
0420
0421
0422 PCS-978
Slot 04&05
0401 I1-1A
Ia_H The phase A current input of HV side (polarity).
0403 I1-5A
0402 I1n-1A
Ian_H The phase A current input of HV side.
0404 I1n-5A
0405 I2-1A
Ib_H The phase B current input of HV side (polarity).
0407 I2-5A
0406 I2n-1A
Ibn_H The phase B current input of HV side.
0408 I2n-5A
0409 I3-1A
Ic_H The phase C current input of HV side (polarity).
0411 I3-5A

Date: 2016-06-22
0410 I3n-1A
Icn_H The phase C current input of HV side.
0412 I3n-5A
0413 I4-1A
3I0_H The neutral current input of HV side (polarity).
0415 I4-5A
0414 I4n-1A
3I0n_H The neutral current input of HV side.
0416 I4n-5A
0423 U4 Reserved
0424 U4n Reserved
Slot 06&07
0601 I1-1A
Ia_L The phase A current input of LV side (polarity).
0603 I1-5A
0602 I1n-1A
Ian_L The phase A current input of LV side.
0604 I1n-5A
0605 I2-1A
Ib_L The phase B current input of LV side (polarity).
0607 I2-5A
0606 I2n-1A
Ibn_L The phase B current input of LV side.
0608 I2n-5A
0609 I3-1A
Ic_L The phase C current input of LV side (polarity).
0611 I3-5A
0610 I3n-1A
Icn_L The phase C current input of LV side.
0612 I3n-5A
0613 I4-1A
3I0_L The neutral current input of LV side (polarity).
0615 I4-5A
0614 I4n-1A
3I0n_L The neutral current input of LV side.
0616 I4n-5A

Date: 2016-06-22
0617 U1 Reserved
0618 U1n Reserved
0619 U2 Reserved
0620 U2n Reserved
0621 U3 Reserved
0622 U3n Reserved
0623 U4 Reserved
0624 U4n Reserved
and LV sides.

HV side LV side
*
A A
*
B B
*
C C
*
(0416) 0414 0614 (0616)
(0415) 0413 0613 (0615)

0401 (0403) (0603) 0601
0402 (0404) (0604) 0602
0405 (0407) (0607) 0605
0406 (0408) (0608) 0606
0409 (0411) (0611) 0609
0410 (0412) (0612) 0610
0423 0623
0424 0624
0417 0617
0418 0618
0419 0619
0420 0620
0421 0621
0422 0622
PCS-978

Date: 2016-06-22
Slot 04&05
0401 I1-1A
0403 I1-5A
0402 I1n-1A
0404 I1n-5A
0405 I2-1A
0407 I2-5A
0406 I2n-1A
0408 I2n-5A
0409 I3-1A
0411 I3-5A
0410 I3n-1A
0412 I3n-5A
0413 I4-1A
0415 I4-5A
0414 I4n-1A
0416 I4n-5A
Slot 06&07
0601 I1-1A
0602 I1-5A
0603 I1n-1A
0604 I1n-5A
0605 I2-1A Ib_L The phase B current input of LV side (polarity).

Date: 2016-06-22
0606 I2-5A
0607 I2n-1A
0608 I2n-5A
0609 I3-1A
0610 I3-5A
0611 I3n-1A
0612 I3n-5A
0613 I4-1A
0614 I4-5A
0615 I4n-1A
0616 I4n-5A
3. Typical application for three-windings transformer


Date: 2016-06-22
C
A
B
LV side
* * *
HV side MV side
*
*
A A
*
*
B B
*
*
C C
*
(0416) 0414 0614 (0616)
(0415) 0413 0613 (0615)

0401 (0403) (0803) 0801
0402 (0404) (0804) 0802
0405 (0407) (0807) 0805
0406 (0408) (0808) 0806
0409 (0411) (0811) 0809
0410 (0412) (0812) 0810
0423 0823
0424 0824
0417 0817
0418 0818
0419 0819
0420 0820
0421 0821
0422 0822
(0603) 0601
(0604) 0602
(0607) 0605
(0608) 0606
(0611) 0609
(0612) 0610
0623
0624
0617
0618
0619
0620
0621
PCS-978 0622
Figure 6.3-21 Typical CT/VT connection for three-windings transformer
Slot 04&05
0401 I1-1A
0403 I1-5A
0402 I1n-1A Ian_H The phase A current input of HV side.

Date: 2016-06-22
0404 I1n-5A
0405 I2-1A
0407 I2-5A
0406 I2n-1A
0408 I2n-5A
0409 I3-1A
0411 I3-5A
0410 I3n-1A
0412 I3n-5A
0413 I4-1A
0415 I4-5A
0414 I4n-1A
0416 I4n-5A
Slot 06&07
0601 I1-1A
Ia_M The phase A current input of MV side (polarity).
0602 I1-5A
0603 I1n-1A
Ian_M The phase A current input of MV side.
0604 I1n-5A
0605 I2-1A
Ib_M The phase B current input of MV side (polarity).
0606 I2-5A
0607 I2n-1A
Ibn_M The phase B current input of MV side.
0608 I2n-5A
0609 I3-1A Ic_M The phase C current input of MV side (polarity).

Date: 2016-06-22
0610 I3-5A
0611 I3n-1A
Icn_M The phase C current input of MV side.
0612 I3n-5A
0613 I4-1A
3I0_M The neutral current input of MV side (polarity).
0614 I4-5A
0615 I4n-1A
3I0n_M The neutral current input of MV side.
0616 I4n-5A
Slot 08&09
0801 I1-1A
0802 I1-5A
0803 I1n-1A
0804 I1n-5A
0805 I2-1A
0806 I2-5A
0807 I2n-1A
0808 I2n-5A
0809 I3-1A
0810 I3-5A
0811 I3n-1A
0812 I3n-5A
0813 I4-1A
Reserved
0814 I4-5A
0815 I4n-1A Reserved

Date: 2016-06-22
0816 I4n-5A
 NR1409
It has 6 groups of current input channels, and terminal 01 (or 03), 05 (or 07), 09 (or 11), 13 (or 15),
17 (or 19) and 21 (or 23) are polarity marks. A 24-pin connector is fixed on the front of this module,
and its pin definition is described as below.
I1-1A 01 I1n-1A 02
NR1409
I1-5A 03 I1n-5A 04
I2-1A 05 I2n-1A 06
I2-5A 07 I2n-5A 08
I3-1A 09 I3n-1A 10
I3-5A 11 I3n-5A 12
I4-1A 13 I4n-1A 14
I4-5A 15 I4n-5A 16
I5-1A 17 I5n-1A 18
I5-5A 19 I5n-5A 20
I6-1A 21 I6n-1A 22
I6-5A 23 I6n-5A 24
1. Typical application for two-windings transformer
In this application, there are one branch at HV side and two branches at LV side without voltage
input.

Date: 2016-06-22

LV side 2
*
A
*
B
*
C
HV side LV side 1
*
*
A A
*
*
B B
*
*
C C
*
(0416) 0414 0418 (0420)
(0415) 0413 0417 (0419)

0401 (0403) (0603) 0601
0402 (0404) (0604) 0602
0405 (0407) (0607) 0605
0406 (0408) (0608) 0606
0409 (0411) (0611) 0609
0410 (0412) (0612) 0610
(0615) 0613
(0616) 0614
(0619) 0617
(0620) 0618
(0623) 0621
PCS-978 (0624) 0622
Figure 6.3-23 Typical CT/VT connection for two-windings transformer
Slot 04&05
0401 I1-1A
0403 I1-5A
0402 I1n-1A
0404 I1n-5A
0405 I2-1A
0407 I2-5A
0406 I2n-1A Ibn_H The phase B current input of HV side.

Date: 2016-06-22
0408 I2n-5A
0409 I3-1A
0411 I3-5A
0410 I3n-1A
0412 I3n-5A
0413 I4-1A
0415 I4-5A
0414 I4n-1A
0416 I4n-5A
0417 I5-1A
0418 I5-5A
0419 I5n-1A
0420 I5n-5A
0421 I6-1A
Reserved
0422 I6-5A
0423 I6n-1A
Reserved
0424 I6n-5A
Slot 06&07
0601 I1-1A
Ia_L1 The phase A current input of LV side 1 (polarity).
0602 I1-5A
0603 I1n-1A
Ian_L1 The phase A current input of LV side 1.
0604 I1n-5A
0605 I2-1A
Ib_L1 The phase B current input of LV side 1 (polarity).
0606 I2-5A
0607 I2n-1A
Ibn_L1 The phase B current input of LV side 1.
0608 I2n-5A
0609 I3-1A
Ic_L1 The phase C current input of LV side 1 (polarity).
0610 I3-5A
0611 I3n-1A
Icn_L1 The phase C current input of LV side 1.
0612 I3n-5A
0613 I4-1A Ia_L2 The phase A current input of LV side 2 (polarity).

Date: 2016-06-22
0614 I4-5A
0615 I4n-1A
Ian_L2 The phase A current input of LV side 2.
0616 I4n-5A
0617 I5-1A
Ib_L2 The phase B current input of LV side 2 (polarity).
0618 I5-5A
0619 I5n-1A
Ibn_L2 The phase B current input of LV side 2.
0620 I5n-5A
0621 I6-1A
Ic_L2 The phase C current input of LV side 2 (polarity).
0622 I6-5A
0623 I6n-1A
Icn_L2 The phase C current input of LV side 2.
0624 I6n-5A
2. Typical application for three-windings transformer
In this application, there is one branch at HV side, MV side and LV side respectively without
voltage input.


Date: 2016-06-22
C
A
B
LV side
* * *
HV side MV side A
*
*
A
B
*
*
B
C
*
*
C
*
(0416) 0414 (0616) 0614
(0415) 0413 (0615) 0613

0401 (0403) (0803) 0801
0402 (0404) (0804) 0802
0405 (0407) (0807) 0805
0406 (0408) (0808) 0806
0409 (0411) (0811) 0809
0410 (0412) (0812) 0810
(0603) 0601
(0604) 0602
(0607) 0605
(0608) 0606
(0611) 0609
PCS-978 (0612) 0610
Figure 6.3-24 Typical CT/VT connection for three-windings transformer
Slot 04&05
0401 I1-1A
0403 I1-5A
0402 I1n-1A
0404 I1n-5A
0405 I2-1A
0407 I2-5A

Date: 2016-06-22
0406 I2n-1A
0408 I2n-5A
0409 I3-1A
0411 I3-5A
0410 I3n-1A
0412 I3n-5A
0413 I4-1A
0415 I4-5A
0414 I4n-1A
0416 I4n-5A
0417 I5-1A
Reserved
0418 I5-5A
0419 I5n-1A
Reserved
0420 I5n-5A
0421 I6-1A
Reserved
0422 I6-5A
0423 I6n-1A
Reserved
0424 I6n-5A
Slot 06&07
0601 I1-1A
Ia_M The phase A current input of MV side (polarity).
0602 I1-5A
0603 I1n-1A
Ian_M The phase A current input of MV side.
0604 I1n-5A
0605 I2-1A
Ib_M The phase B current input of MV side (polarity).
0606 I2-5A
0607 I2n-1A
Ibn_M The phase B current input of MV side.
0608 I2n-5A
0609 I3-1A
Ic_M The phase C current input of MV side (polarity).
0610 I3-5A
0611 I3n-1A
Icn_M The phase C current input of MV side.
0612 I3n-5A

Date: 2016-06-22
0613 I4-1A
3I0_M The neutral current input of MV side (polarity).
0614 I4-5A
0615 I4n-1A
3I0n_M The neutral current input of MV side.
0616 I4n-5A
0617 I5-1A
Reserved
0618 I5-5A
0619 I5n-1A
Reserved
0620 I5n-5A
0621 I6-1A
Reserved
0622 I6-5A
0623 I6n-1A
Reserved
0624 I6n-5A
Slot 08&09
0801 I1-1A
0802 I1-5A
0803 I1n-1A
0804 I1n-5A
0805 I2-1A
0806 I2-5A
0807 I2n-1A
0808 I2n-5A
0809 I3-1A
0810 I3-5A
0811 I3n-1A
0812 I3n-5A
0813 I4-1A
Reserved
0814 I4-5A
0815 I4n-1A
Reserved
0816 I4n-5A
0817 I5-1A
Reserved
0818 I5-5A

Date: 2016-06-22
0819 I5n-1A
Reserved
0820 I5n-5A
0821 I6-1A
Reserved
0822 I6-5A
0823 I6n-1A
Reserved
0824 I6n-5A
NOTICE!
All typical current circuit and voltage circuit connections mentioned above are only for
reference.
6.3.4 DSP Plug-in Module (Protection Calculation)

The module consists of high-performance digital signal processor, optical-fibre interface, 16-digit
high-accuracy ADC that can perform synchronous sampling and other peripherals. The functions
of this module include analog data acquisition, sample data exchanging with the opposite side,
calculation of protection logic and tripping output etc.
NR1156
1 2 3
4 5 6
Figure 6.3-25 View of DSP plug-in module
When the module is connected to conventional CT/VT, it can perform the synchronous data
acquisition through the AC input board; when the module is connected to ECVT, it can receive the
real-time synchronous sample data from merging unit through the multi-mode optical-fibre

Date: 2016-06-22
interface.
6.3.5 DSP Plug-in Module (Fault Detector)
The module consists of high-performance digital signal processor, optical-fibre interface, 16-digit
high-accuracy ADC that can perform synchronous sampling and other peripherals. The functions
of this module include analog data acquisition, calculation of fault detector elements and providing
positive power supply to output relay.
When the module is connected to conventional CT/VT, it can perform the synchronous data
acquisition through the AC input board; when the module is connected to ECVT, it can receive the
real-time synchronous sample data from merging unit through the multi-mode optical-fibre
interface.
NR1156
1 2 3
4 5 6
Figure 6.3-26 View of DSP plug-in module
6.3.6 BI Plug-in Module (Binary Input)
There are five kinds of BI modules available, NR1503A, NR1503AR, NR1504A, NR1504AR and
NR1508A. Up to 2 BI modules can be equipped with one device.

Date: 2016-06-22
Voltage
264
176
154
140
110
87.5
77
62.5 Operation
55
Operation uncertain
No operation
0 110V 125V 220V 220V
Figure 6.3-27 Voltage dependence for binary inputs
The well-designed debouncing technique is adopted in this device, and the state change of binary
input within “Debouncing time” will be ignored. As shown in Figure 6.3-28.
Binary input state
Validate binary input state

change & write it into SOE
record
1
Debouncing time
Time
T0 T1
Figure 6.3-28 Debouncing technique
1. NR1503
Each BI module is with a 22-pin connector for 11 binary inputs, and its rated voltage can be
selected to be 110Vdc, 125Vdc, 220Vdc. Each binary input of NR1503A and NR1503AR has
independent negative power input of opto-coupler and can be configurable. NR1503A′s pickup
voltage and dropoff voltage are fixed value, and the range is from 55%Un to 70%Un. NR1503AR′s

Date: 2016-06-22
pickup voltage and dropoff voltage are settable by the setting [xx.U_Pickup_BI] and
[xx.U_Dropoff_BI] from 55%Un to 80%Un.
BI_01 01
NR1503 Opto01- 02
BI_02 03
Opto02- 04
BI_03 05
Opto03- 06
BI_04 07
Opto04- 08
BI_05 09
Opto05- 10
BI_06 11
Opto06- 12
BI_07 13
Opto07- 14
BI_08 15
Opto08- 16
BI_09 17
Opto09- 18
BI_10 19
Opto10- 20
BI_11 21
Opto11- 22
Figure 6.3-29 View of BI plug-in module (NR1503)
[BI_n] can be configured as a specified binary input by PCS-Explorer software (n=01, 02, ……).
Terminal description for NR1503 is shown as follows.

01 BI_01 Configurable binary input 1
02 Opto01- Negative supply of configurable binary input 1

Date: 2016-06-22

2. NR1504
Each BI module is with a 22-pin connector for 18 binary inputs, and its rated voltage can be
selected to be 110Vdc, 125Vdc, 220Vdc. All binary inputs of NR1504A and NR1504AR share one
common negative power input and can be configurable. NR1504A′s pickup voltage and dropoff
voltage are fixed value, and the range is from 55%Un to 70%Un. NR1504AR′s pickup voltage and
dropoff voltage are settable by the setting [xx.U_Pickup_BI] and [xx.U_Dropoff_BI] from 55%Un to
80%Un.
Opto+ 01
NR1504 BI_01 02
BI_02 03
BI_03 04
BI_04 05
BI_05 06
BI_06 07
08
BI_07 09
BI_08 10
BI_09 11
BI_10 12
BI_11 13
BI_12 14
15
BI_13 16
BI_14 17
BI_15 18
BI_16 19
BI_17 20
BI_18 21
COM- 22
Figure 6.3-30 View of BI plug-in module (NR1504)
Terminal description for NR1504 is shown as follows.

01 Opto+ Positive supply of power supply of the module

Date: 2016-06-22

08 Blank Not used
15 Blank Not used
22 COM- Common terminal of negative supply of binary inputs
3. NR1508
NR1508A is with a 22-pin connector for 11 binary inputs, and its rated voltage is 220Vdc. Each
binary input of NR1508A has independent negative power input of opto-coupler and can be
configurable. NR1508A′s pickup voltage and dropoff voltage are fixed value, and the range is from
75%Un to 80%Un.

Date: 2016-06-22
BI_01 01
NR1508A Opto01- 02
BI_02 03
Opto02- 04
BI_03 05
Opto03- 06
BI_04 07
Opto04- 08
BI_05 09
Opto05- 10
BI_06 11
Opto06- 12
BI_07 13
Opto07- 14
BI_08 15
Opto08- 16
BI_09 17
Opto09- 18
BI_10 19
Opto10- 20
BI_11 21
Opto11- 22
Figure 6.3-31 View of BI plug-in module (NR1508A)
Terminal description for NR 1508A is shown as follows.


Date: 2016-06-22

NOTICE!
A default configuration is given for first four binary signals (BI_01, BI_02, BI_03, BI_04)
in first BI plug-in module, and they are [BI_TimeSyn], [BI_Print], [BI_Maintenance] and
[BI_RstTarg] respectively. They can alos be configured as other signals. Because the
first binary signal [BI_01] is set as [BI_TimeSyn] by default (the state change
information of binary signal [BI_TimeSyn] does not need be displayed), new binary
signal should be added to state change message if it is set as other signal.
1. Binary input: [BI_TimeSyn]
It is used to receive clock synchronization signal from clock synchronization device, the binary
input [BI_TimeSyn] will change from “0” to “1” once pulse signal is received. When the device
adopts “Conventional” mode as clock synchronization mode (refer to section “Communication
Settings”), the device can receives PPM (pulse per minute) and PPS (pulse per second). If the
setting [Opt_TimeSyn] is set as other values, this binary input is invalid.
2. Binary input: [BI_Print]
It is used to manually trigger printing latest report when the equipment is configured as manual
printing mode by logic setting [En_AutoPrint]=0. The printer button is located on the panel usually.
If the equipment is configured as automatic printing mode ([En_AutoPrint]=1), report will be printed
automatically as soon as it is formed.
3. Binary input: [BI_Maintenance]
It is used to block communication export when this binary input is energized. During device
maintenance or testing, this binary input is then energized not to send reports via communication
port, local display and printing still work as usual. This binary input should be de-energized when
the device is restored back to normal.
The application of the binary input [BI_Maintenance] for digital substation communication adopting
IEC61850 protocol is given as follows.
1) Processing mechanism for MMS (Manufacturing Message Specification) message
 The protection device should send the state of this binary input to client.
 When this binary input is energized, the bit “Test” of quality (Q) in the sent message
changes to “1”.
 When this binary input is energized, the client cannot control the isolator link and circuit
breaker, modify settings and switch setting group remotely.
 According to the value of the bit “Test” of quality (Q) in the message sent, the client
discriminate whether this message is maintenance message, and then deal with it

Date: 2016-06-22
correspondingly. If the message is the maintenance message, the content of the message
will not be displayed on real-time message window, audio alarm not issued, but the picture
is refreshed so as to ensure that the state of the picture is in step with the actual state. The
maintenance message will be stored, and can be inquired, in independent window.
2) Processing mechanism for GOOSE message
 When this binary input is energized, the bit “Test” in the GOOSE message sent by the
protection device changes to “1”.
 For the receiving end of GOOSE message, it will compare the value of the bit “Test” in the
GOOSE message received by it with the state of its own binary input (i..e
[BI_Maintenance]), the message will be thought as invalid unless they are conformable.
3) Processing mechanism for SV (Sampling Value) message
 When this binary input of merging unit is energized, the bit “Test” of quality (Q) of sampling
data in the SV message sent change “1”.
 For the receiving end of SV message, if the value of bit “Test” of quality (Q) of sampling
data in the SV message received is “1”, the relevant protection functions will be disabled,
but under maintenance state, the protection device should calculate and display the
magnitude of sampling data.
 For duplicated protection function configurations, all merging units of control module
configured to receive sampling should be also duplicated. Both dual protection devices
and dual merging units should be fully independent each other, and one of them is in
maintenance state will not affect the normal operation of the other.
4. Binary input: [BI_RstTarg]
It is used to reset latching signal relay and LCD displaying. The reset is done by pressing a button
on the panel.
6.3.7 BO Plug-in Module (Binary Output)

6.3.7.1 Trip Binary Output
There are three kinds of signal output module to select, NR1521A, NR1521H and NR1580A.
1. NR1521A
NR1521A is a standard binary output module, which can provide 11 tripping output contacts that
can be controlled separately by positive power supply of fault detector. The contacts provide by
NR1521A are all normally open (NO) contacts. [BO_n] (n=01, 02…11) can be configured as a
specified tripping output contact by PCS-Explorer according to project requirement.

Date: 2016-06-22
01
BO_01
NR1521A 02
03
BO_02
04
05
BO_03
06
07
BO_04
08
09
BO_05
10
11
BO_06
12
13
BO_07
14
15
BO_08
16
17
BO_09
18
19
BO_10
20
21
BO_11
22
Figure 6.3-32 View of BO plug-in module (NR1521A)
2. NR1521H
01
BO_01
NR1521H 02
03
BO_02
04
05
BO_03
06
07
BO_04
08
09
BO_05
10
11
BO_06
12
13
BO_07
14
15
BO_08
16
17
BO_09
18
19
BO_10
20
21
BO_11
22
3.
Figure 6.3-33 View of BO plug-in module (NR1521H)

Date: 2016-06-22
NR1521H is a standard binary output module, which can provide 11 tripping output contacts that
can be controlled separately by positive power supply of fault detector. The contacts provide by
NR1521H are all normally open (NO) contacts. [BO_n] (n=01, 02…11) can be configured as a
specified tripping output contact by PCS-Explorer according to project requirement. The first four
output contacts, BO_01, BO_02, BO_03 and BO_04, are in parallel with instantaneous operating
contacts which can improve operating speed of binary output contact.
4. NR1580A
NR1580A can provide 6 output contacts with controlled by fault detector. It is a heavy-capacity
binary output plug-in module, which can be used to control the circuit breaker directly.
+ 01
NR1580A BO_01 02
- 03
04
+ 05
BO_02 06
- 07
08
+ 09
BO_03 10
- 11
12
+ 13
BO_04 14
- 15
16
+ 17
BO_05 18
- 19
20
+ 21
BO_06
- 22
Figure 6.3-34 View of BO plug-in module (NR1580A)
6.3.7.2 Signal Binary Output
There are two kinds of signal output module to select, NR1523B and NR1521C
1. NR1523B
NR1523B is a standard binary output module, which can provide 11 signal output contacts without
controlled by fault detector. Among those contacts, [BO_n] (n=01, 02…07, 10) are normally open
(NO) contacts, [BO_08] and [BO_09] are normally closed (NC) contacts and [BO_11] is a magnetic
latched NO contact defined as protection tripping signal fixedly. All contacts in the module can be
configured as specified signal output contacts of some protection by PCS-Explorer according to
project requirement.

Date: 2016-06-22
01
BO_01
NR1523B 02
03
BO_02
04
05
BO_03
06
07
BO_04
08
09
BO_05
10
11
BO_06
12
13
BO_07
14
15
BO_08
16
17
BO_09
18
19
BO_10
20
21
BO_11
22
Figure 6.3-35 View of BO plug-in module (NR1523B)
NOTICE!
If more magnetic latched contacts or normally closed (NC) contacts are required,
please specific when placing order.
2. NR1521C
NR1521C is a standard binary output module, which can provide 11 NO signal output contacts
without controlled by fault detector. All contacts, [BO_n] (n=01, 02…07, 11), can be configured as
specified signal output contacts of some protection by PCS-Explorer according to project
requirement.

Date: 2016-06-22
01
BO_01
NR1521C 02
03
BO_02
04
05
BO_03
06
07
BO_04
08
09
BO_05
10
11
BO_06
12
13
BO_07
14
15
BO_08
16
17
BO_09
18
19
BO_10
20
21
BO_11
22
Figure 6.3-36 View of BO plug-in module (NR1521C)
6.3.8 DI Plug-in Module (DC Analog Input)
There are two kinds of signal output module to select, NR1410A and NR1410B
1. NR1410A
NR1410A is a standard transducer input module, which can receive three RTD input signals and
three DC input signals (0~20mA current or 0~5V voltage) from external transducer. The hardware
and software of the device are provided to receive these signals from the external transducers and
convert these signals into a digital format to be used as required.
Typical connection of the module with external transducers is shown in the figure below:
 RTD input signals
PT100
NR1410A
Current input+
Input_I1+ 01
Current input-
Input_I1- 02
Measurement input+
Input_M1+ 03
Measurement input-
Input_M1- 04

Date: 2016-06-22
 DC input signals
There is a jumper between pin S1 and pin S3 on NR1410A to control the input signal type
(0~20mA or 0~5V).
S1~S3 (OFF): 0~20mA shunt resistor disabled and 0~5V measure provided.
S1~S3 (ON): 0~20mA shunt resistor enabled and 0~20mA measure provided.
External Transducer
To_Transducer_24V
4-20mA Transducer_24V_Return
Input_+
S1
Jumper
S3
R
Input_- NR1410A
The pin definition of NR1410A is described as below.
Input_I1+ 01
NR1410A Input_I1- 02
Input_M1+ 03
Input_M1- 04
Input_I2+ 05
Input_I2- 06
Input_M2+ 07
Input_M2- 08
Input_I3+ 09
Input_I3- 10
Input_M3+ 11
Input_M3- 12
13
Input_1+ 14
Input_1- 15
16
Input_2+ 17
Input_2- 18
19
Input_3+ 20
Input_3- 21
22
Figure 6.3-37 View of DI plug-in module (NR1410A)
2. NR1410B

Date: 2016-06-22
NR1410B is a standard transducer input module, which can receive six 0~20mA current or 0~5V
voltage input signals from external transducer. The hardware and software of the device are
provided to receive these signals from the external transducers and convert these signals into a
digital format to be used as required.
There is a jumper between pin S1 and pin S6 on NR1410B to control the input signal type
(0~20mA or 0~5V).
S1~S6 (OFF): 0~20mA shunt resistor disabled and 0~5V measure provided.
S1~S6 (ON): 0~20mA shunt resistor enabled and 0~20mA measure provided.
External Transducer
To_Transducer_24V
4-20mA Transducer_24V_Return
Input_+
S1
Jumper
S6
R
Input_- NR1410B
The pin definition of NR1410B is described as below.
01
NR1410B 02
Input_1+ 03
Input_1- 04
05
06
Input_2+ 07
Input_2- 08
09
10
Input_3+ 11
Input_3- 12
13
Input_4+ 14
Input_4- 15
16
Input_5+ 17
Input_5- 18
19
Input_6+ 20
Input_7- 21
22
Figure 6.3-38 View of DI plug-in module (NR1410B)

Date: 2016-06-22
6.3.9 MR Plug-in Module (Mechanical Relay Input/Output)

There are two kinds of MR modules, NR1536A (220Vdc) and NR1536B (110Vdc/125Vdc), to be
selected, and they are input and output modules for mechanical protection. This module is used to
output various signals, issue trip commands and accept reset command.
01 Reset signal Reset input

NR1536A NR1536B 02 BI_MR1
Binary input
03 signals of BI_MR2
04 mechanical BI_MR3
protection
05 BI_MR4
06 BI_MR1_1
07 BI_MR2_1
08 BI_MR3_1
09 BI_MR4_1
10 Common 1
11 BI_MR1_2
12 BI_MR2_2
13 BI_MR3_2
14 BI_MR4_2
15 Common 2
16 BI_MR1_3
17 BI_MR2_3
18 BI_MR3_3
19 BI_MR4_3
20 Common 3
21 PWR+
Power supply
22 PWR-
Figure 6.3-39 View of MR plug-in module (NR1536A/NR1536B)
Pin No. Symbol Description

Reset input, when a reset signal arrives, the corresponding magnetic latched
01 Reset input
contacts of mechanical signals are reset.
Mechanical signal inputs
02 BI_MR1 Mechanical relay (MR) signal input 1
st
1 group output contacts (magnetic latched contact)
10,06 BO_MR1_1 NO contact, is closed when binary input [BI_MR1] is energized.
nd
2 group output contacts

Date: 2016-06-22
Pin No. Symbol Description

rd
3 group output contacts
Power supply input of module
20 PWR+ Positive pole of power supply for MR module connected to DC power supply
21 PWR- Negative pole of power supply for MR module connected to DC power supply
6.3.10 NET-DSP module (Optional)
This module consists of high-performance DSP (digital signal processor), two 100Mbit/s
optical-fibre interfaces and two 100Mbit/s RJ-45 ethernet and other peripherals. It supports
GOOSE and SV by IEC 61850-9-2 protocols. It can receive and send GOOSE command to
intelligent control device, and receive SV from MU (merging unit).
This module supports IEEE1588 network time protocol, E2E and P2P defined in IEEE1588
protocol can be selected. This module supports Ethernet IEEE802.3 time adjustment message
format, UDP time adjustment message format and GMRP.
NR1136A NR1136C
RX
Figure 6.3-40 View of the NET-DSP module

Date: 2016-06-22
CAUTION!
Do NOT look into the end of an optical fiber connected to an optical port.
Do NOT look into an optical port/connector.
A direct sight to laser light may cause temporary or permanent blindness.
The device can output q data by GOOSE, and an output signal is provided “Output_q”. This signal
is used to indicate the quality of all output signals. According to the standard definition about the
quality by IEC 61850, the value of this signal is “0” under normal conditions, and it will be “2048”
(Bit1 is “1”, and other bits is “0”) when the device is under maintenance condtion.
The definition of each bit about quality signal by IEC 61850 is as below.
Table 6.3-2 Encoding of IEC 61850-7-3 quality
Bit (s) IEC 61850-7-3 Bit-String

Bit Attribute name Attribute value Value Default
Good 00 00
Invalid 01
0-1 Validity
Reserved 10
Questionable 11
2 Overflow TRUE FALSE
3 OutofRange TRUE FALSE
4 BadReference TRUE FALSE
5 Oscillatory TRUE FALSE
6 Failure TRUE FALSE
7 OldData TRUE FALSE
8 Inconsistent TRUE FALSE
9 Inaccurate TRUE FALSE
Process 0 0
10 Source
Subsituted 1
11 Test TRUE FALSE
12 OperatorBlocked TRUE FALSE
The method of adding q data is as bellow steps.
1. Step1: Open the DEV file and find “MMS_GOOSE_Out” page.

Date: 2016-06-22
2. Step2: Taking “PTRC_out” module as an example, which can be found in “Symbol Library”
and instanced as bellow.
3. Step3: Double click the instanced module, the parameter list is displayed as bellow. Tr1~Tr8
are used for sending signals, q1~q8 are used for q data, the relationship between them is one
to one. Only one total q data can be added to all 8 sending signals by “batch_q”.

Date: 2016-06-22
4. Step4: The output q data, named “Output_q” in variable library, is used for all sending signals.
The path is shown as bellow which is marked in red color.
5. Step5: Put the mouse on the “Output_q” signal, hold the left button of the mouse and drag it to
the corresponding position, and then release. The detail is as bellow.

Date: 2016-06-22
After the above steps, save the modifications and compress driver file. Check the latest GOOSE
and CID file.
6.3.11 HMI Module
The display panel consists of liquid crystal display module, keyboard, LED and ARM processor.
The functions of ARM processor include display control of the liquid crystal display module,
keyboard processing, and exchanging data with the CPU through serial port etc. The liquid crystal
display module is a high-performance grand liquid crystal panel with soft back lighting, which has a
user-friendly interface and an extensive display range.
6.4 Tripping Output Group
The PCS-978 provides output contacts which are controlled by tripping logic settings. Tripping
logic settings of each protection element can be configured by users as per their requirements.
The tripping logic setting in form of [x.OutMap] is comprised of 16-bit binary number, but that
displayed on the LCD is 4-bit hexadecimal number. Each binary bit controls a set of tripping output
contacts. When the protection element operates, if the corresponding bit is set as “1”, the relevant
output contacts will pick up, conversely, if the bit is set as “0”, the relevant output contacts will not
pick up.
For typical configuration of PCS-978, two BO modules are equipped with being installed
adjacently in slot 13 and slot 14, and then tripping output contacts controlled by logic setting are
list in the following table.
Table 6.4-1 Output contact groups of typical configuration
Bit Tripping output group Contacts
0 TrpOutp1: the 1st group of tripping output contacts 1301-1302, 1303-1304, 1305-1306

Date: 2016-06-22
Bit Tripping output group Contacts
1 TrpOutp2: the 2nd group of tripping output contacts 1307-1308, 1309-1310
2 TrpOutp3: the 3rd group of tripping output contacts 1311-1312, 1313-1314
3 TrpOutp4: the 4th group of tripping output contacts 1315-1316, 1317-1318
5 TrpOutp6: the 6th group of tripping output contacts 1401-1402, 1403-1404, 1405-1406
6 TrpOutp7: the 7th group of tripping output contacts 1407-1408 1409-1410,
10 No definition
11 No definition
12 No definition
13 No definition
14 No definition
15 No definition
NOTICE!
The controlled contacts are represents with its slot position and pin number. For
example, contact 1301-1302 means terminal 01-02 of the module at the slot 13, i.e. 13
represents the slot position of module, 01(02) represents the pin number on the
module.

Date: 2016-06-22
7 Settings
7 Settings
Table of Contents
7 Settings .............................................................................................. 7-a
7.1 Overview .......................................................................................................... 7-1
7.2 System Settings .............................................................................................. 7-1
7.2.1 Setting Description............................................................................................................... 7-1
7.2.2 Access Path ......................................................................................................................... 7-6
7.3 Protection Settings ......................................................................................... 7-6

7.3.1 Setting Description............................................................................................................... 7-6
7.3.2 Access Path ....................................................................................................................... 7-31
7.4 Logic Link Settings ....................................................................................... 7-32

7.1.1 Setting Description............................................................................................................. 7-32
7.1.2 Access Path ....................................................................................................................... 7-32
7.5 Device Setup.................................................................................................. 7-32

7.5.1 Setting Description............................................................................................................. 7-32
7.1.3 Access Path ...................................................................................................................... 7-42
List of Tables
Table 7.2-1 System setting ................................................................................... 7-1
Table 7.2-2 Matrix of phase compensation .............................................................. 7-3
Table 7.5-1 Device settings ................................................................................. 7-32
Table 7.5-2 Communication settings ...................................................................... 7-34

Date: 2016-06-22
-09-07
7 Settings

Date: 2016-06-22
7 Settings
7.1 Overview
All settings are classified to two kinds, protection settings and common settings. Each protection
element has its independent setting menu to configure which are given detailed description in
Chapter “Operation Theory”. Common settings consist of device settings, communication settings
and system settings, and protection settings are also listed in the chapter.
The device has 10 setting groups for protection to coordinate with the mode of power system
operation, one of which is assigned to be active. However, common settings are shared by all
protection setting groups, and settings of protection element are set according to secondary
values.
NOTICE!
7.2 System Settings
7.2.1 Setting Description

Table 7.2-1 System setting
No. Item Range Step Unit

1 Active_Grp 1~10 1
2 Opt_SysFreq 50Hz or 60Hz
3 PrimaryEquip_Name Max 20 characters
4 Sn 0.1~5000 0.001 MVA
5 U1n_Plate 0.1~2000 0.001 kV
6 HVS.U1n_Plate 0~2000 0.001 kV
7 MVS.U1n_Plate 0~2000 0.001 kV
8 LVS.U1n_Plate 0~2000 0.001 kV
9 Clk_MVS_WRT_HVS 0~11 1 Clk
10 Clk_LVS_WRT_HVS 0~11 1 Clk
11 Clk_PhComp 0~11 1 Clk
12 HVS.En_I0Elim 0: disable or 1: enable
13 MVS.En_I0Elim 0: disable or 1: enable
14 LVS.En_I0Elim 0: disable or 1: enable
15 x.U1n 0~2000 0.001 kV
16 x.U2n 100~130 0.001 V
17 x.U1n_Delt 0~2000 0.001 kV
18 x.U2n_Delt 30~300 0.001 V

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-09-07
7 Settings
No. Item Range Step Unit

19 x.I1n 0~60000 1 A
20 x.I2n 1A or 5A A
21 x.I1n_NP 0~60000 1 A
22 x.I2n_NP 1A or 5A A
23 Zn_Reac_NP 0~10000 1 ohm
24 f_High_FreqAlm 50~65 1 Hz
25 f_Low_FreqAlm 40~60 1 Hz
26 x.En_RevCT 0 or 1
27 x.En_RevCT_NP 0 or 1
1. Active_Grp
The current protection setting group number, and total 10 group settings are provided. The device
settings, communication settings and system settings, are common for all protection groups.
2. Opt_SysFreq
It is option of system frequency, and can be set as 50Hz or 60Hz
3. PrimaryEquip_Name
It is recognized by the device automatically. Such setting is used for printing messages
4. Sn
Transformer or reactor capacity
5. x.U1n_Plate
They are primary rated voltage at x side of transformer or reactor stated on nameplate
The setting principle of rated phase-to-phase voltages of each side is to take the primary rated
voltage marked on the nameplate of transformer as the primary rated voltage of corresponding
side. For an on-load tap changing transformer, the voltage of transformer with tap in middle
position can be taken as the value of this setting. As to other kind of transformers, actual operation
voltage (i.e. phase-to-phase voltage) shall be taken as this setting value, otherwise the calculation
of correction coefficient may be wrong
For example, if the voltage at 220kV side is 230kV for an on-load tap changing transformer with
tap in its middle position, and then the setting is set as 230kV.
NOTICE!
For one side not used in the device, please set the primary rated voltage value of the
corresponding side as “0”.
6. Clk_MVS_WRT_HVS, Clk_LVS_WRT_HVS
They are the wiring o′clock of MV/LV side with respect to HV side, is the parameter shown on
transformer nameplate with the range of 0~11, and need not further calculation.

Date: 2016-06-22
7 Settings
7. Clk_PhComp
It is the target o′clock each side current will be shift to for phase compensation.
For examples:
The vector group of a transformer is Y0/Δ11 and the target o′clock ([Clk_PhComp]) is set to “11”.
Therefore, the setting [Clk_LVS_WRT_HVS] should be set to “11”.
1. For HV side, the clock of HV side with reference to target o′clock is 1 (i.e. wiring o′clock
12-target o′clock 11) clock, so the matrix of relative o′clock 1 is adopted to compensate HV
side current. Zero-sequence current elimination has no effect on phase compensation in the
condition.
2. For LV side, the clock of LV side with reference to target o′clock is 0 (i.e. wiring o′clock 11-
target o′clock 11), so the matrix of relative o′clock 0 is adopted to compensate LV side current.
Then it is needed to decide whether zero-sequence current is eliminated and select the
corresponding matrix.
If an earthing transformer is connected at LV side out the protection zone of differential protection,
then matrix of relative o′clock 0 without zero-sequence current elimination can be selected.
If an earthing transformer is connected at LV side in the protection zone of differential protection,

then zero-sequence current must be eliminated and otherwise differential protection may operate
unexpectedly during an external fault. Therefore the matrix of relative o′clock 0 with
zero-sequence current elimination should be selected.
Table 7.2-2 Matrix of phase compensation

Relative o'clock
 1 0 0  2  1  1
0
0 1 0  1 
  1 2  1
  3
0 0 1  1  1 2
 1  1 0
1 
1   0 1  1
3
 1 0 1
 0  1 0  1  2 1
2
 0 0 1  1 
 1 1  2
  3 
 1 0 0  2 1 1
 0  1 1
1 
3   1 0  1
3
 1 1 0

Date: 2016-06-22
-09-07
7 Settings

Relative o'clock
0 0 1   1  1 2
1 
4
 1 0 0  2  1  1
  3 
0 1 0  1 2  1
 1 0 1
1 
5   1  1 0
3
 0 1  1
 1 0 0  2 1 1
6
 0  1 0 1 
  1  2 1
  3
 0 0  1  1 1  2
  1 1 0
1 
7   0  1 1
3
 1 0  1
 0 1 0  1 2  1 
8
0 0 1
1 
 1  1 2 
 3 
 1 0 0  2  1  1
 0 1  1
1 
9   1 0 1
3
 1  1 0
 0 0  1  1 1  2
10
 1 0 0
1 
  2 1 1
 3
 0  1 0  1  2 1
 1 0  1
1 
11   1 1 0
3
 0  1 1
8. HVS.En_I0Elim, MVS.En_I0Elim, LVS.En_I0Elim
They are logic settings to enable or disable zero-sequence current elimination for phase
compensation of each side of transformer. The setting is recommended to be set to “1” in general,
and only if one side of transformer, without eathing transformer being connected, is no grounded,
the setting of corresponding side is recommended to be set to “0”.
9. x.U1n, x.U2n
They are primary voltage and secondary voltage values of the three-phase VT at each side of a
transformer respectively, which are phase-to-phase voltage values.

Date: 2016-06-22
7 Settings
They should be set according to the actual primary value and secondary value of the
corresponding side VT. For example, if the voltage ratio is 220kV/100V at HV side of a transformer,
[HVS.U1n] shall be set as “220kV” and [HVS.U2n] should be set as “100V”.
10. x.U1n_Delt, x.U2n_Delt
They are primary and secondary rated voltage of broken-delta VT at x side, which should be set
according to the actual primary value and secondary value of the corresponding side VT.
11. x.I1n, x.I2n
They are primary and secondary rated current of CT at x side, which should be set according to
the actual primary value and secondary value of the corresponding side CT.
12. x.I1n_NP, x.I2n_NP
They are primary and secondary rated current of neutral CT at x side, which should be set
according to the actual primary value and secondary value of the corresponding side CT.
13. Zn_Reac_NP
It is impedance of neutral earthing reactor
14. f_High_FreqAlm
It is frequency upper limit setting. The device will issue an alarm [Alm_Freq], when system
frequency is higher than the setting.
15. f_Low_FreqAlm
It is frequency lower limit setting. The device will issue an alarm [Alm_Freq], when system
frequency is lower than the setting.
16. x.En_RevCT
It is used to adjust the current polarity of CT at x side of transformer, and default value is 0.
0: keep connected current polarity unchanged
1: make connected current polarity reversed
When the current polarity of primary CT is different with defined forward direction by PCS-978, the
setting can be set as “1”. However, it is recommended to change external wiring of primary CT.
17. x.En_RevCT_NP
It is used to adjust the current polarity of zero-sequence CT at x side of transformer, and default
value is 0.
0: keep connected current polarity unchanged
1: make connected current polarity reversed
When the current polarity of primary CT is different with defined forward direction by PCS-978, the
setting can be set as “1”. However, it is recommended to change external wiring of primary CT.

Date: 2016-06-22
-09-07
7 Settings
7.2.2 Access Path

MainMenu→“Settings”→“System Settings”
7.3 Protection Settings
There are some symbols mentioned in the following sections and the meaning of them are given
here.
Un: rated secondary voltage of VT
In: rated secondary current of CT
p.u.: per unit value of setting and current for current differential protection

7.3.1.1 Three-phase Current Element Settings (Curr3P)

1 x.I1n 0~60000 1 A Primary current value at x side of transformer
2 x.I2n 1 or 5 A Secondary current value at x side of transformer
7.3.1.2 Three-phase Voltage Element Settings (Volt3P)

Rated value of primary voltage at x side of
1 x.U1n 1~2000 0.001 kV
transformer
Rated value of secondary voltage at x side of
2 x.U2n 100~130 0.001 V
transformer
7.3.1.3 Residual Current Element Settings (Curr1P)

Primary rated current of neutral CT at x side of
1 x.I1n_NP 0~60000 1 A
transformer
Secondary rated current of neutral CT at x side of
2 x.I2n_NP 1 or 5 A
transformer
7.3.1.4 Residual Voltage Element Settings (Volt1P)

Primary rated voltage of broken-delta VT at x side
1 x.U1n_Delt 1~2000 1000 kV
of transformer
Secondary rated voltage of broken-delta VT at x
2 x.U2n_Delt 10~200 100 V
side of transformer

Date: 2016-06-22
7 Settings
7.3.1.5 Transformer Current Differential Protection Settings (87T)

1 87T.I_Knee1 0.100~1.000 0.001 p.u.
2 87T.I_Knee2 4.000~8.000 0.001 p.u.
3 87T.I_Biased 0.050~5.000 0.001 p.u. Pickup setting of biased differential element
Current setting of instantaneous differential
4 87T.I_Inst 0.050~20.000 0.001 p.u.
element
8 87T.K_Hm2_Inrush 0.050~0.800 0.001
current detection
Coefficient of third harmonics for inrush
9 87T.K_Hm3_Inrush 0.050~0.800 0.001
current detection
Current setting of differential circuit
10 87T.I_Alm 0.050~1.500 0.001 p.u.
abnormality alarm
Coefficient of third or fifth harmonic for
11 87T.K_Hm3/Hm5_OvExc 0.050~0.800 0.001 overexcitation detection
The recommended value is 0.25.
instantaneous differential element
12 87T.En_Inst 0 or 1 1
0: disable
1: enable
conventional biased differential element
13 87T.En_Biased 0 or 1 1
0: disable
1: enable
Logic setting of enabling/disabling DPFC
14 87T.En_DPFC 0 or 1 1
0: disable
1: enable
Option of inrush current discrimination
principle:
15 87T.Opt_Inrush_Ident 0, 1 1
0: waveform symmetry
1: Harmonic principle
Option of inrush blocking mode
16 87T.Opt_BlkMode_Inrush 0, 1 1 0: self-adaptive blocking
1: phase-to-phase crossing
Logic setting of enabling/disabling third
17 87T.En_Hm3_Blk 0 or 1 1 harmonic blocking for inrush current
0: disable

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-09-07
7 Settings

1: enable
Logic setting of enabling/disabling block
biased differential element during CT circuit
18 87T.En_CTS_Blk 0 or 1 1 failure
0: disable
1: enable
Option of third or fifth harmonic for
overexcitation criterion
19 87T.Opt_Hm3/Hm5_OvExc 0, 1 1
0: third harmonic
1: fifth harmonic
Tripping logic setting of transformer
differential protection
20 87T.OutMap 0000~FFFF
Refer to section 7.3.1.26 for detailed
description
7.3.1.6 Reactor Current Differential Protection Settings (87R)
Transformer current differential protection and reactor current differential protection are alternative
for users, so setting lists of two protections must not appear on device LCD and the access path of
them is same.

1 87R.I_Biased 0.05~5 0.001 p.u. Pickup setting of biased differential element
2 87R.I_Inst 0.05~20 0.001 p.u. Current setting of instantaneous differential element
3 87R.Slope 0.1~0.9 0.001 Slope of biased differential element
4 87R.K_Hm2_Inrush 0.05~0.3 0.001
current detection
Coefficient of third harmonics for inrush current
5 87R.K_Hm3_Inrush 0.05~0.3 0.001
detection
Current setting of differential current abnormality
6 87R.I_Alm 0.1~1.5 0.001 p.u.
alarm
Logic setting of enabling/disabling instantaneous
7 87R.En_Inst 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling conventional
8 87R.En_Biased 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling DPFC biased
9 87R.En_DPFC 0 or 1
0: disable
1: enable
10 87R.En_REF 0 or 1 Logic setting of enabling/disabling zero-sequence

Date: 2016-06-22
7 Settings

0: disable
1: enable
Logic setting of enabling/disabling block biased
differential element during CT circuit failure
11 87R.En_CTS_Blk 0 or 1
0: disable
1: enable
Tripping logic setting of reactor current differential
protection.
12 87R.OutMap 0000~FFFF The logic setting is shared by the instantaneous
differential element, biased differential element
and DPFC biased differential element.
7.3.1.7 Restricted Earth Fault Protection Settings (64REF)

Knee point setting of REF
1 x.64REF.I_Knee 0.1~4 0.001 In
0.5In is recommended.
2 x.64REF.I_Biased 0.05~5 0.001 In Pickup setting of REF
Percentage restraint coefficient of REF
3 x.64REF.Slope 0.2~0.75 0.001
0.5 is recommended.
Time delay for REF
4 x.64REF.t_Op 0~20 0.001 s
Recommended value is zero.
Logic setting of enabling/disabling block REF
during CT circuit failure
5 x.64REF.En_CTS_Blk 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling neutral
current criterion
6 x.64REF.En_NPCurr 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling REF
7 x.64REF.En 0 or 1 0: disable
1: enable
8 x.64REF.OutMap 0000~FFFF Tripping logic setting of REF
7.3.1.8 Winding Differential Protection Settings (87W)

Knee point setting of biased winding differential
1 87W.I_Knee 0.1~4 0.001 In
protection.
Pickup setting of biased winding differential
2 87W.I_Biased 0.05~5 0.001 In
protection
Percentage restraint coefficient of biased
3 87W.Slope 0.1~0.9 0.001
winding differential protection

Date: 2016-06-22
-09-07
7 Settings

Logic setting of enabling/disabling blocking
winding differential protection during CT circuit
4 87W.En_CTS_Blk 0 or 1 failure
0: disable
1: enable
Logic setting of enabling/disabling phase winding
5 87W.En_PhSeg 0 or 1
0: disable
1: enable
Logic setting of enabling/disabling winding
6 87W.En_REF 0 or 1
0: disable
1: enable
Tripping logic setting of winding differential
7 87W.OutMap 0000~FFFF
protection
7.3.1.9 Inter-turn Fault Protection Settings (21IT)

inter-turn fault protection
1 21IT.En 0 or 1
0: disable
1: enable
Tripping logic setting of inter-turn
2 21IT.OutMap 0000~FFFF
fault protection
7.3.1.10 Overexcitation Protection Settings (24)

It is used to set reference voltage of
overexcitation calculation, and it is
1 24.Un 0~2000 0.001 kV
usually set as primary rated voltage
at calculated side of transformer
Voltage option between phase
voltage and phase-to-phase voltage
for calculation of overexcitation
2 24.Opt_Up/Upp 0, 1 1
protection
0: phase voltage

Date: 2016-06-22
7 Settings

overexcitation protection for trip
5 24DT1.En 0 or 1
purpose
0: disable
1: enable
Tripping logic settings of stage 1 of
6 24DT1.OutMap 0000~FFFF definite-time overexcitation
overexcitation protection for alarm
9 24DT2.En 0 or 1
purpose
0: disable
1: enable
Highest-limit multiple setting of
10 24IDMT.K0_Set 1.0~1.7 0.001 inverse-time overexcitation
protection: n0
11 24IDMT.t0_Op 0.1~9999 0.001 s
highest-limit setting: t0
12 24IDMT.K1_Set 1.0~1.7 0.001
13 24IDMT.t1_Op 0.1~9999 0.001 s
14 24IDMT.K2_Set 1.0~1.7 0.001
15 24IDMT.t2_Op 0.1-9999 0.001 s
16 24IDMT.K3_Set 1.0~1.7 0.001
17 24IDMT.t3_Op 0.1~9999 0.001 s
18 24IDMT.K4_Set 1.0~1.7 0.001
19 24IDMT.t4_Op 0.1~9999 0.001 s
20 24IDMT.K5_Set 1.0~1.7 0.001 Multiple setting 5 of inverse-time

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-09-07
7 Settings

21 24IDMT.t5_Op 0.1~9999 0.001 s
22 24IDMT.K6_Set 1.0~1.7 0.001
23 24IDMT.t6_Op 0.1~9999 0.001 s
24 24IDMT.K7_Set 1.0~1.7 0.001
25 24IDMT.t7_Op 0.1~9999 0.001 s
26 24IDMT.K8_Set 1.0~1.7 0.001
27 24IDMT.t8_Op 0.1~9999 0.001 s
Lowest-limit multiple setting of
28 24IDMT.K9_Set 1.0~1.7 0.001
inverse-time overexcitation: n9
29 24IDMT.t9_Op 0.1~9999 0.001 s
lowest-limit multiple setting: t9
Multiple setting of inverse-time
30 24IDMT.K_Alm 0.5~0.99 0.001 overexcitation protection for alarm
purpose
31 24IDMT.En_Alm 0 or 1 protection for alarm purpose
0: disable
1: enable
Cooling time of inverse-time
32 24IDMT.t_Cooling 0.1~9999 0.001 s
33 24IDMT.En_Trp 0 or 1 protection for trip purpose
0: disable
1: enable
Tripping logic setting of inverse-time
34 24IDMT.OutMap 0000~FFFF 1
7.3.1.11 Frequency Protection Settings (81)

Pickup setting of overfrequency
1 81O.f_Pkp 50~65 0.01 Hz
protection
2 81O.OFn.f_Set 50~65 0.01 Hz
overfrequency protection (n=1, 2, 3,

Date: 2016-06-22
7 Settings

4)
3 81O.OFn.t_Op 0~6000 0.001 s overfrequency protection (n=1, 2, 3,
4)
stage n of overfrequency protection
4 81O.OFn.En 0 or 1 (n=1, 2, 3, 4)
0:disable
1:enable
5 81O.OFn.OutMap. 0000~FFFF overfrequency protection (n=1, 2, 3,
4)
Pickup setting of underfrequency
6 81U.f_Pkp 45~60 0.01 Hz
protection
df/dt setting of blocking
7 81U.df/dt_Blk 0.05~20 0.01 Hz/s
underfrequency protection
8 81U.UFn.f_Set 45~60 0.01 Hz underfrequency protection (n=1, 2,
3, 4)
9 81U.UFn.t_Op 0~6000 0.001 s underfrequency protection (n=1, 2,
3, 4)
stage n of underfrequency
10 81U.UFn.En 0 or 1 protection (n=1, 2, 3, 4)
0:disable
1:enable
df/dt blocking function for stage n of
underfrequency protection (n=1, 2,
11 81U.UFn.En_df/dt_Blk 0 or 1
3, 4)
0:disable
1:enable
12 81U.UFn.OutMap 0000~FFFF underfrequency protection (n=1, 2,
3, 4)
7.3.1.12 Impedance Protection Settings (21)

Relay characteristic angle (also called
1 x.21.RCA 1~89 0.01 deg
reach angle)
Current setting of PSBR element
2 x.21.I_PSBR 0.04~150 0.001 A
It should be greater than maximum

Date: 2016-06-22
-09-07
7 Settings

load current.
power swing blocking releasing
function to control impedance
3 x.21.En_PSBR 0 or 1
protection
0: disable
1: enable
protection
protection
protection
0: disable
1: enable
protection
protection
protection
protection
0: disable
1: enable
protection
Zero-sequence compensation
14 x.21.K0 0~2 0.001
coefficient

Date: 2016-06-22
7 Settings

protection
protection
protection
0: disable
1: enable
protection
protection
protection
protection
0: disable
1: enable
protection
7.3.1.13 Phase Overcurrent Protection Settings (50/51P)

Phase-to-phase voltage setting of
1 x.50/51P.VCE.Upp_VCE 2~200 0.001 V
voltage control element
Negative-sequence voltage setting
2 x.50/51P.VCE.U2_VCE 2~200 0.001 V
of voltage control element
Relay characteristic angle of phase
3 x.50/51P.DIR.RCA 0~360 1 deg

Date: 2016-06-22
-09-07
7 Settings

4 x.50/51P.HMB.K_Hm2 0.05~1.0 0.001
blocking function of phase
5 x.50/51P.HMB.I_Rls_HmBlk 0.04~150 0.001 A
overcurrent protection.
It is recommended to set as 0.15.
Option of harmonic blocking mode
6 x.50/51P.HMB.Opt_HmBlk 0, 1 1 0: phase-segregated blocking mode
1: phase crossing blocking mode
block for phase overcurrent
protection during VT circuit abnormal
0: disable
1: enable
7 x.50/51P.En_VTS_Blk 0 or 1 service, phase overcurrent
protection will be blocked if the
setting is set as “1”, and phase
overcurrent protection is not
controlled by direction element and
voltage control element if the setting
is set as ”0”.
Current setting of stage n of phase
8 x.50/51Pn.I_Set 0.04~30In 0.001 A
Time delay of stage n of phase
9 x.50/51Pn.t_Op 0~3600 0.001 s
voltage control element for phase
10 x.50/51Pn.En_VCE 0 or 1 overcurrent protection (n=1, 2, 3)
0: disable
1: enable
Non_Directional
Direction option of stage n of phase
11 x.50/51Pn.Opt_Dir Forward
Reverse
phase overcurrent protection (n=1, 2,
12 x.50/51Pn.En_Hm2_Blk 0 or 1
3)
0: disable
1: enable
13 x.50/51Pn.En 0 or 1 stage n of phase overcurrent

Date: 2016-06-22
7 Settings

0: disable
1: enable
14 x.50/51Pn.OutMap 0000~FFFF phase overcurrent protection (n=1, 2,
3)
Pickup setting of stage 4 of phase
15 x.50/51P4.I_Set 0.04~30In 0.001 A
Multiple of the maximum operating
16 x.50/51P4.K_I_Max 10~40 0.001 current to the pickup setting of stage
4 of phase overcurrent protection
Time delay of stage 4 of phase
17 x.50/51P4.t_Op 0~3600 0.001 s
18 x.50/51P4.TMS 0.05~3.2 0.001
Minimum delay of stage 4 of phase
19 x.50/51P4.tmin 0~20 0.001 s
The constant K of stage 4 of phase
20 x.50/51P4.K 0~120 0.001
The constant C of stage 4 of phase
21 x.50/51P4.C 0~20 0.001
22 x.50/51P4.Alpha 0.02~5 0.001
DefTime
IECN
IECV
IECE
IECST
IECLT
Option of characteristic curve for
ANSIE
23 x.50/51P4.Opt_Curve stage 4 of phase overcurrent
ANSIV
protection
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
voltage control element for stage 4 of
24 x.50/51P4.En_VCE 0 or 1 phase overcurrent protection
0: disable
1: enable
Non_Directional Direction option of stage 4 of phase
25 x.50/51P4.Opt_Dir
Forward overcurrent protection

Date: 2016-06-22
-09-07
7 Settings

Reverse
26 x.50/51P4.En_Hm2_Blk 0 or 1 phase overcurrent protection
0: disable
1: enable
stage 4 of phase overcurrent
27 x.50/51P4.En 0 or 1 protection
0: disable
1: enable
7.3.1.14 Earth Fault Protection Settings (50/51G)

Relay characteristic angle of earth
1 x.50/51G.DIR.RCA 0~360 1 deg
fault protection
2 x.50/51G.HMB.K_Hm2 0.05~1.0 0.001
3 x.50/51G.HMB.3I0_Rls_HmBlk 0.04~150 0.001 A blocking function of earth fault
protection
earth fault protection be blocked
during VT circuit abnormality
0: disable
1: enable
4 x.50/51G.DIR.En_VTS_Blk 0 or 1
service, directional earth fault is
blocked if the setting is set as “1”.
Directional earth fault protection
switches to non-directional earth
fault protection if the setting is set as
“0”.
Current setting of stage n of earth
5 x.50/51Gn.3I0_Set 0.04~30In 0.001 A
Time delay of stage n of earth fault
6 x.50/51Gn.t_Op 0~3600 0.001 s
Non_Directional
Direction option of stage n of earth
7 x.50/51Gn.Opt_Dir Forward
Reverse
8 x.50/51Gn.Opt_3I0 0, 1 1 Option of residual current for the

Date: 2016-06-22
7 Settings

calculation of stage n of earth fault
9 x.50/51Gn.En_Hm2_Blk 0 or 1 earth fault protection (n=1, 2, 3)
0: disable
1: enable
stage n of earth fault protection (n=1,
10 x.50/51Gn.En 0 or 1 2, 3)
0: disable
1: enable
11 x.50/51Gn.OutMap 0000~FFFF
earth fault protection (n=1, 2, 3)
Pickup setting of stage 4 of earth
12 x.50/51G4.3I0_Set 0.04~30In 0.001 A
fault protection
13 x.50/51G4.K_3I0_Max 10~40 0.001 residual current to the pickup setting
of stage 4 of earth fault protection
Time delay of stage 4 of earth fault
14 x.50/51G4.t_Op 0~3600 0.001 s
protection
15 x.50/51G4.TMS 0.05~3.2 0.001
Minimum delay of stage 4 of earth
16 x.50/51G4.tmin 0~20 0.001 s
fault protection
The constant K of stage 4 of earth
17 x.50/51G4.K 0~120 0.001
fault protection
The constant C of stage 4 of earth
18 x.50/51G4.C 0~20 0.001
fault protection
19 x.50/51G4.Alpha 0.02~5 0.001
DefTime
IECN
IECV
IECE
IECST Option of characteristic curve for
20 x.50/51G4.Opt_Curve
IECLT stage 4 of earth fault protection
ANSIE
ANSIV
ANSI
ANSIM

Date: 2016-06-22
-09-07
7 Settings

ANSILTE
ANSILTV
ANSILT
UserDefine
Non_Directional
Direction option of stage 4 of earth
21 x.50/51G4.Opt_Dir Forward
fault protection
Reverse
calculation of stage 4 of earth fault
22 x.50/51G4.Opt_3I0 0, 1 1 protection
23 x.50/51G4.En_Hm2_Blk 0 or 1 earth fault protection
0: disable
1: enable
stage 4 of earth fault protection
24 x.50/51G4.En 0 or 1
0: disable
1: enable
25 x.50/51G4.OutMap 0000~FFFF
7.3.1.15 Negative-Sequence Overcurrent Protection Settings (50/51Q)

Current setting of stage 1 of negative-sequence
1 x.50/51Q1.I2_Set 0.04~30In 0.001 A
2 x.50/51Q1.t_Op 0~3600 0.001 s
3 x.50/51Q1.En 0 or 1
0: disable
1: enable
Pickup setting of stage 2 of negative-sequence
5 x.50/51Q2.I2_Set 0.04~30In 0.001 A
negative-sequence current to the pickup setting
6 x.50/51Q2.K_I2_Max 10~40 0.001
of stage 2 of negative-sequence overcurrent
protection
7 x.50/51Q2.t_Op 0~3600 0.001 s Time delay of stage 2 of negative-sequence

Date: 2016-06-22
7 Settings

Time multiplier setting of stage 2 of ground
8 x.50/51Q2.TMS 0.05~3.2 0.001
Minimum delay of stage 2 of negative-sequence
9 x.50/51Q2.tmin 0~20 0.001 s
The constant K of stage 2 of negative-sequence
10 x.50/51Q2.K 0~120 0.001
-sequence overcurrent protection
The constant C of stage 2 of negative-sequence
11 x.50/51Q2.C 0~20 0.001
12 x.50/51Q2.Alpha 0.02~5 0.001
DefTime
IECN
IECV
IECE
IECST
IECLT
13 x.50/51Q2.Opt_Curve
ANSIV negative-sequence overcurrent protection
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
14 x.50/51Q2.En 0 or 1
0: disable
1: enable
7.3.1.16 Phase Overvoltage Protection Settings (59P)

Voltage setting of stage 1 of phase overvoltage
1 x.59P1.U_Set 2~200 0.001 V
protection
2 x.59P1.t_Op 0~3600 0.001 s
protection
3 x.59P1.Opt_Up/Upp 0, 1 1 of phase overvoltage protection
0: phase voltage

Date: 2016-06-22
-09-07
7 Settings

4 x.59P1.Opt_1P/3P 0, 1 1 overvoltage protection
0: 1-out-of-3
1: 3-out-of-3
5 x.59P1.En 0 or 1 1
0: disable
1: enable
Pickup setting of stage 2 of phase overvoltage
7 x.59P2.U_Set 2~200 0.001 V
protection
Multiplier of the maximum operating voltage to
8 x.59P2.K_U_Max 1~10 0.001 the pickup setting of stage 2 of phase
9 x.59P2.t_Op 0~3600 0.001 s
protection
10 x.59P2.Opt_Up/Upp 0~1 1 of phase overvoltage protection
0: phase voltage
11 x.59P2.Opt_1P/3P 0~1 1 overvoltage protection
0: 1-out-of-3
1: 3-out-of-3
Time multiplier setting of stage 2 of phase
12 x.59P2.TMS 0.05~3.2 0.001
Minimum delay of stage 2 of phase overvoltage
13 x.59P2.tmin 0~20s 0.001 s
protection
The constant K of stage 2 of phase overvoltage
14 x.59P2.K 0~120 0.001
protection
The constant C stage 2 of phase overvoltage
15 x.59P2.C 0~20 0.001
protection
The exponent alpha stage 2 of phase
16 x.59P2.Alpha 0.02~5 0.001
DefTime
IECN
Option of characteristic curve for stage 2 of
17 x.59P2.Opt_Curve IECV
IECE
IECST

Date: 2016-06-22
7 Settings

IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
18 x.59P2.En 0 or 1
0: disable
1: enable
7.3.1.17 Residual Overvoltage Protection Settings (59G)

Voltage setting of stage 1 of residual overvoltage
1 x.59G1.3U0_Set 2~200 0.001 V
protection
2 x.59G1.t_Op 0~3600 0.001 s
protection
3 x.59G1.En 0 or 1
0: disable
1: enable
4 x.59G1.Opt_3U0 0, 1 1
Voltage setting of stage 2 of residual overvoltage
6 x.59G2.3U0_Set 2~200 0.001 V
protection
7 x.59G2.K_3U0_Max 1~2 0.001 voltage to the pickup setting of stage 2 of
8 x.59G2.t_Op 0~3600 0.001 s
protection
Minimum delay of stage 2 of residual
9 x.59G2.tmin 0~20s 0.001 s
Time multiplier setting of stage 2 of residual
10 x.59G2.TMS 0.05~3.2 0.001

Date: 2016-06-22
-09-07
7 Settings

The constant K of stage 2 of residual
11 x.59G2.K 0.0~120 0.001
The constant C stage 2 of residual overvoltage
12 x.59G2.C 0.0~20 0.001
protection
The exponent alpha stage 2 of residual
13 x.59G2.Alpha 0.02~5 0.001
DefTime
IECN
IECV
IECE
IECST
IECLT
14 x.59G2.Opt_Curve
ANSIV residual overvoltage protection
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
15 x.59G2.En 0 or 1
0: disable
1: enable
16 x.59G2.Opt_3U0 0, 1 1
7.3.1.18 Undervoltage Protection Settings (27P)

du/dt blocking setting of undervoltage
1 x.27P.du/dt_Blk 0~100 0.001 V/s
protection
2 x.27P.U_Recov 10~100 0.001 V Lowest voltage threshold of fault recovery
Time setting of fault recovery
It should be greater than the operating time of
3 x.27P.t_Recov 0~20 0.001 s backup protection generally. For example, if the
longest operating time of backup protection is 4s,
the setting [x.27.t_Recov] can be set to “4.5s~5s”.
4 x.27P.UV1.U_Set 10~100 0.001 V
protection

Date: 2016-06-22
7 Settings

5 x.27P.UV1.t_Op 0.05~100 0.001 s
protection
6 x.27P.UV1.En_du/dt_Blk 0 or 1 protection
0: disable
1: enable
7 x.27P.UV1.En 0 or 1
0: disable
1: enable
protection
9 x.27P.UV2.U_Set 0~100 0.001 V
protection
10 x.27P.UV2.t_Op 0.05~100 0.001 s
protection
11 x.27P.UV2.En_du/dt_Blk 0 or 1 protection.
0: disable
1: enable
undervoltage protection.
12 x.27P.UV2.En 0 or 1
0: disable
1: enable
protection
14 x.27P.UV3.U_Set 0~100 0.001 V
protection
15 x.27P.UV3.t_Op 0.05~100 0.001 s
protection
0: disable
1: enable
Logic setting of enabling stage 3 of
17 x.27P.UV3.En 0 or 1 1
0: disable
1: enable
protection

Date: 2016-06-22
-09-07
7 Settings

19 x.27P.UV4.U_Set 0~100 0.001 V
protection
20 x.27P.UV4.t_Op 0.05~100 0.001 s
protection
21 x.27P.UV4.En 0 or 1 1
0: disable
1: enable
0: disable
1: enable
protection
7.3.1.19 Thermal Overload Protection Settings (49)

Tripping setting of thermal capacity for thermal
1 x.49.K_Trp 1~3 0.001
overload protection
Alarm setting of thermal capacity for thermal
2 x.49.K_Alm 1~3 0.001
overload protection
Base current setting of thermal overload
3 x.49.Ib_Set 0.04~30In 0.001 A
protection
4 x.49.Tau 0.1~100 0.001 min Thermal time constant
The convertor coefficient from the current to the
5 x.49.K_T_Diff 0~200 0.001
temperature
The cooling mode of transformer, usually,
6 x.49.Alpha_Cold 1~2 0.001 natural cooling: 1.6
forced cooling: 2
overload protection operate to trip
7 x.49.En_Trp 0 or 1
0: disable
1: enable
overload protection operate to alarm
8 x.49.En_Alm 0 or 1
0: disable
1: enable
Tripping logic setting of thermal overload
9 x.49.OutMap 0000~FFFF
protection

Date: 2016-06-22
7 Settings
7.3.1.20 Breaker Failure Protection Settings (50BF)

1 x.50BF.Ip_Set 0.04~30In 0.001 A Current setting of phase current criterion.
2 x.50BF.3I0_Set 0.04~30In 0.001 A Current setting of residual current criterion.
Current setting of negative-sequence current
3 x.50BF.I2_Set 0.04~30In 0.001 A
criterion.
Logic setting of enabling/disabling phase current
criterion to control breaker failure protection
4 x.50BF.En_Ip 0 or 1
0: disable
1: enable
5 x.50BF.En_I2 0 or 1 breaker failure protection.
0: disable
1: enable
Logic setting of enabling/disabling DPFC current
criterion to control breaker failure protection.
6 x.50BF.En_DPFC 0 or 1
0: disable
1: enable
residual-sequence current criterion to control
7 x.50BF.En_3I0 0 or 1 breaker failure protection.
0: disable
1: enable
To enable the criterion of CB position for breaker
failure protection.
9 x. 50BF.En_CB_Ctrl 0 or 1
0: disable
1: enable
10 x.50BF.En_t1 0 or 1
0: disable
1: enable
failure protection.
13 x.50BF.En_t2 0 or 1
0: disable
1: enable
failure protection

Date: 2016-06-22
-09-07
7 Settings
7.3.1.21 Pole Disagreement Protection Settings (62PD)

Residual current setting of pole disagreement
1 x.62PD.3I0_Set 0.04~30In 0.001 A
protection
Negative-sequence current setting of pole
2 x.62PD.I2_Set 0.04~30In 0.001 A
3 x.62PD.t_Op 0~20 0.001 s
trip purpose
4 x.62PD.t_Alm 0~20 0.001 s
alarm purpose
current criterion to control pole disagreement
5 x.62PD.En_3I0 0 or 1 1 protection
0: disable
1: enable
6 x.62PD.En_I2 0 or 1 1 breaker failure protection
0: disable
1: enable
Logic setting of enabling/disabling pole
7 x.62PD.En_PD 0 or 1 1
0: disable
1: enable
Tripping logic setting of pole disagreement
8 x.62PD.OutMap 0000~FFFF
protection
7.3.1.22 Phase Overcurrent Alarm Settings (51PAlm)

Current setting of stage n of phase overcurrent
1 x.51PAlmn.I_Set 0.04A~30In 0.001 A
alarm (n=1, 2)
Time delay of stage n of phase overcurrent
2 x.51PAlmn.t_Op 0~3600 0.001 s
alarm (n=1, 2)
Drop off ratio of stage n of phase overcurrent
3 x.51PAlmn.K_DropOut 0.7~1.0 0.001
alarm (n=1, 2)
Logic setting of enabling/disabling stage n of
phase overcurrent alarm (n=1, 2)
4 x.51PAlmn.En 0 or 1
0: disable
1: enable
7.3.1.23 Residual Overvoltage Alarm Settings (59GAlm)

1 x.59GAlm.3U0_Set 2~200 0.001 V Voltage setting of residual overvoltage alarm

Date: 2016-06-22
7 Settings

2 x.59GAlm.t_Alm 0~3600 0.001 s Time delay of residual overvoltage alarm
3 x.59GAlm.K_3U0_Max 1~2 0.001 voltage to the pickup setting of residual
overvoltage alarm
4 x. 59GAlm.tmin 0~20 0.001 s Minimum delay of residual overvoltage alarm
Time multiplier setting of residual overvoltage
5 x. 59GAlm.TMS 0.05~3.2 0.001
alarm
6 x. 59GAlm.K 0.0~120 0.001 The constant K of residual overvoltage alarm
7 x. 59GAlm.C 0.0~20 0.001 s The constant C of residual overvoltage alarm
The exponent alpha of residual overvoltage
8 x. 59GAlm.Alpha 0.02~5 0.001
alarm
DefTime
IECN
IECV
IECE
IECST
IECLT
ANSIE Option of characteristic curve for residual
9 x. 59GAlm.Opt_Curve
ANSIV overvoltage alarm
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
overvoltage alarm
10 x.59GAlm.En 0 or 1
0: disable
1: enable
Option of residual voltage for residual
overvoltage alarm
11 x.59GAlm.Opt_3U0 0, 1 1
7.3.1.24 Mechanical Protection Settings (MR)

1 MR.t_DPU_1 0~3600 0.001 s
mechanical relay 1
2 MR.t_PW_1 0~10 0.001 s
relay 1
3 MR.En_1 0 or 1 relay 1
0: disable

Date: 2016-06-22
-09-07
7 Settings

1: enable
5 MR.t_DPU_2 0~3600 0.001 s
mechanical relay 2
6 MR.t_PW_2 0~10 0.001 s
relay 2
relay 2
7 MR.En_2 0 or 1
0: disable
1: enable
9 MR.t_DPU_3 0~3600 0.001 s
mechanical relay 3
10 MR.t_PW_3 0~10 0.001 s
relay 3
relay 3
11 MR.En_3 0 or 1
0: disable
1: enable
13 MR.t_DPU_4 0~3600 0.001 s
mechanical relay 4
14 MR.t_PW_4 0~10 0.001 s
relay 4
relay 4
15 MR.En_4 0 or 1
0: disable
1: enable
7.3.1.25 Temperature Protection Settings (26)

1 26.Tmax 0~200 0.01 °C
maximum input
2 26.Tmin 0~200 0.01 °C
minimum input
Temperature setting for trip purpose of
3 26.T_Trp 0~200 0.01 °C
temperature protection
Temperature setting for alarm purpose of
4 26.T_Alm 0~200 0.01 °C
temperature alarm element
Time delay for trip purpose of temperature
5 26.t_Trp 0.01~4800 0.001 s
protection

Date: 2016-06-22
7 Settings

Time delay for alarm purpose of temperature
6 26.t_Alm 0.01~4800 0.001 s
protection
7 26.En_Trp 0 or 1
0: disable
1: enable
8 26.En_Alm 0 or 1
0: disable
1: enable
9 26.OutMap 0000~FFFF Tripping logic setting of temperature protection
Input option of temperature transducer
0~5V Input signal from Pt100 sensors, i.e., the nominal
10 26.Opt_Input_T 0~20mA 1 resistance of 100 ohms at 0 °C (Pt is the symbol
Pt100 for platinum, 100 for the resistance in ohm at
0 °C).
7.3.1.26 Output Map Settings (OutMap)

01
02
03
04
05
06
07
08
09
10
7.3.2 Access Path

MainMenu→“Settings”→“Prot Settings”

Date: 2016-06-22
-09-07
7 Settings
7.4 Logic Link Settings
The logic link settings are used to determine whether the relevant function of this device is
enabled or disabled. If this device supports the logic link function, it will have a corresponding
submenu in the submenu “Logic Links” for the logic link settings.
Each logic link settings is an “AND” condition of enabling the relevant function with the
corresponding binary input and logic setting. Through SAS or RTU, logic link settings can be set
as “1” or “0”; and it means that the relevant function can be in service or out of service through
remote command. It provides convenience for operation management.

7.1.1.1 Function Link Settings
The function link settings can be defined according to project specification through the
configuration tool, PCS-Explorer.
No. Item Remark Range

1 Link_01 Function link setting 01 0 or 1
7.1.2 Access Path

MainMenu→“Settings”→“Logic Links”
7.5 Device Setup

7.5.1.1 Device Settings
Table 7.5-1 Device settings
No. Item Range

1 HDR_EncodeMode GB18030, UTF-8
2 Opt_Caption_103 Current_language, Fixed_Chinese, Fixed_English
3 Bxx.Un_BinaryInput 24V, 30V, 48V, 110V, 125V, 220V
4 Bxx.U_Pickup_BI 55%Un~80%Un
5 Bxx.U_Dropoff_BI 55%Un~80%Un

Date: 2016-06-22
7 Settings
No. Item Range

6 En_MDisk 0 or 1
7 Bxx.Opt_Type_Chn 0~5V, 0~20mA, PT100 (n=01, 02, 03, 04, 05, 06)
1. HDR_EncodeMode
Select encoding format of header (HDR) file COMTRADE recording file
Default value is “UTF-8”.
2. Opt_Caption_103
Select the caption language sent to SAS via IEC103 protocol
Default value of [Opt_Caption_103] is “Current_language”, and please set it to “Fixed_Chinese” if

the SAS is supplied by China Manufacturer.
3. Bxx.Un_BinaryInput
This setting is used to set voltage level of binary input module. If low-voltage BI module is
equipped, 24V, 30V or 48V can be set according to the actual requirement, and if high-voltage BI
module is equipped, 110V, 125V or 220V can be set according to the actual requirement.
Bxx: this plug-in module is inserted in slot xx.
4. Bxx.U_Pickup_BI
This setting is used to set pickup voltage of binary input module. Bxx: this plug-in module is
inserted in slot xx.
5. Bxx.U_Dropoff_BI
This setting is used to set dropoff voltage of binary input module. Bxx: this plug-in module is
inserted in slot xx.
6. En_MDisk
1: Use moveable disk to realize the backup and recovery function.
0: Moveable disk will be disabled.
A moveable mdisk is implemented on the MON plug-in module to backup and restore programs,
settings and configurations.
If MON plug-in module is broken, remove the mdisk and put it into a new MON plug-in module, use
the menu on HMI to restore the backup programs and configurations. If DSP plug-in module is
broken, after a new DSP plug-in module is installed, use the menu on HMI to restore the backup
programs and configurations. If the moveable mdisk is broken, after a new mdisk is installed on
the MON plug-in module, use the menu on HMI to back up the current programs and
configurations into the new mdisk.
The default setting is 0

Date: 2016-06-22
-09-07
7 Settings
7. Bxx. Opt_Type_Chn
n=01, 02, 03, 04, 05, 06
This setting is used to select the channel n type of the module at slot xx (Bxx represents the slot
number. For example, B08 represents the module at slot 08).
0~5V: supporting 0-5V DC signal
0~20mA: supporting 0~20mA DC signal
PT100: supporting AC voltage signal from PT100 voltage transformer
7.1.2.1 Communication Settings
Table 7.5-2 Communication settings
No. Item Range

1 IP_LAN1 000.000.000.000~255.255.255.255
2 Mask_LAN1 000.000.000.000~255.255.255.255
3 IP_LAN2 000.000.000.000~255.255.255.255
4 Mask_LAN2 000.000.000.000~255.255.255.255
5 En_LAN2 Disable or enable
6 IP_LAN3 000.000.000.000~255.255.255.255
7 Mask_LAN3 000.000.000.000~255.255.255.255
9 IP_LAN4 000.000.000.000~255.255.255.255
10 Mask_LAN4 000.000.000.000~255.255.255.255
12 Gateway 000.000.000.000~255.255.255.255
13 En_Broadcast Disable or enable
14 Addr_RS485A 0~255
15 Baud_RS485A 4800,9600,19200,38400,57600,115200 (bps)

16 Protocol_RS485A IEC103, Modbus, Resv1
17 Addr_RS485B 0~255
18 Baud_RS485B 4800,9600,19200,38400,57600,115200 (bps)
19 Protocol_RS485B IEC103, Modbus, Resv1

20 Threshold_Measmt_Net 0~100%
21 Period_Measmt_Net 0~65535s
22 Format_Measmt 0, 1
23 Baud_Printer 4800,9600,19200,38400,57600,115200 (bps)
24 En_AutoPrint Disable or enable
25 Opt_TimeSyn Conventional, SAS, Advanced or NoTImeSyn
26 IP_Server_SNTP 000.000.000.000~255.255.255.255
27 IP_StandbyServer_SNTP 000.000.000.000~255.255.255.255

Date: 2016-06-22
7 Settings
No. Item Range

28 OffsetHour_UTC -12~+12 (hrs)
29 OffsetMinute_UTC 0~60 (min)
30 Opt_Display_Status PriValue, SecValue
31 Num_Cyc_PreTrigDFR 0~50 (cycles)
32 Cfg_NetPorts_Bond 0x00~0xC0
33 En_TCPx_DNP 0 or 1
34 Addr_Slave_TCPx_DNP 0~65519
35 Addr_Master_TCPx_DNP 0~65519
36 IP_Master_TCPx_DNP 000.000.000.000~255.255.255.255
37 Opt_Map_TCPx_DNP 0~4
BISingleBit
38 Obj01DefltVar_TCPx_DNP
BIWithStatus
BIChWoutT
39 Obj02DefltVar_TCPx_DNP BIChWithAbsTime
BIChWithRelTime
AI32Int
AI16Int
40 Obj30DefltVar_TCPx_DNP AI32IntWoutF
AI16IntWoutF
AI32Flt
AI32IntEvWoutT
41 Obj32DefltVar_TCPx_DNP AI16IntEvWoutT
AI32FltEvWoutT
AO32Int
42 Obj40DefltVar_TCPx_DNP AO16Int
AO32Flt
43 t_AppLayer_TCPx_DNP 0~5 (s)
44 t_KeepAlive_TCPx_DNP 0~7200 (s)
45 En_UR_TCPx_DNP 0 or 1
46 Num_URRetry_TCPx_DNP 2~10
47 t_UROfflRetry_TCPx_DNP 1~5000 (s)
48 Class_BI_TCPx_DNP 0~3
49 Class_AI_TCPx_DNP 0~3
50 t_Select_TCPx_DNP 0~240 (s)
51 t_TimeSynIntvl_TCPx_DNP 0~3600 (s)
1. IP_LAN1, IP_LAN2, IP_LAN3, IP_LAN4
IP address of Ethernet port 1, Ethernet port 2, Ethernet port 3 and Ethernet port 4
2. Mask_LAN1, Mask_LAN2, Mask_LAN3, Mask_LAN4
Subnet mask of Ethernet port 1, Ethernet port 2, Ethernet port 3 and Ethernet port 4

Date: 2016-06-22
-09-07
7 Settings
3. En_LAN2, En_LAN3, En_LAN4
Put Ethernet port 2, Ethernet port 3 and Ethernet port 4 in service
They are used for Ethernet communication based on the IEC 60870-5-103 protocol. When the IEC
61850 protocol is applied, the IP address of Ethernet A will be GOOSE source MAC address.
Ethernet port 1 is always in service by default.
4. Gateway
IP address of Gateway (router)
5. En_Broadcast
This setting is only used only for IEC 60870-5-103 protocol. If NR network IEC 60870-5-103
protocol is used, the setting must be set as “1”.
0: the device does not send UDP messages through network
1: the device sends UDP messages through network
6. Addr_RS485A, Addr_RS485B
They are the device′s communication address used to communicate with the SCADA or RTU via
serial ports (port A and port B).
7. Baud_RS485A, Baud_RS485B
Baud rate of rear RS-485 serial port A or B
8. Protocol_RS485A, Protocol_RS485B
Communication protocol of rear RS-485 serial port A or B
IEC103: IEC 60870-5-103 protocol
Modbus: Modbus Protocol
Resv1: Reserved 1
NOTICE!
Above table listed all the communication settings, the device delivered to the user
maybe only show some settings of them according to the communication interface
configuration. If only the Ethernet ports are applied, the settings about the serial ports
(port A and port B) are not listed in this submenu. And the settings about the Ethernet
ports only listed in this submenu according to the actual number of Ethernet ports.
The standard arrangement of the Ethernet port is two, at most four (predetermined
when ordering). Set the IP address according to actual arrangement of Ethernet
numbers and the un-useful port/ports need not be configured. If PCS-Explorer
configuration tool auxiliary software is connected with this device through the Ethernet,
the IP address of PCS-Explorer must be set as one of the available IP address of this
device.

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7 Settings
9. Threshold_Measmt_Net
Threshold value of sending measurement values to SCADA through IEC 60870-5-103 or

IEC61850 protocol via Ethernet port.
Default value: “1%”
10. Period_Measmt_Net
The time period for equipment sends measurement data to SCADA through IEC 60870-5-103
protocol via Ethernet port.
Default value: “60”
11. Format_Measmt
The setting is used to select the format of measurement data sent to SCADA through IEC
60870-5-103 protocol.
0: GDD data type through IEC103 protocol is 12
1: GDD data type through IEC103 protocol is 7, i.e. 754 short real number of IEEE standard
12. Baud_Printer
Baud rate of printer port
13. En_AutoPrint
If automatic print is required for fault report after protection operating, it is set as “1”. Otherwise, it
should be set to “0”.
14. Opt_TimeSyn
There are four selections for clock synchronization of device shown as follow.
 Conventional
PPS (RS-485): Pulse per second (PPS) via RS-485 differential level
IRIG-B (RS-485): IRIG-B via RS-485 differential level
PPM (DIN): Pulse per minute (PPM) via the binary input [BI_TimeSyn]
PPS (DIN): Pulse per second (PPS) via the binary input [BI_TimeSyn]
 SAS
SNTP (PTP): Unicast (point-to-point) SNTP mode via Ethernet network
SNTP (BC): Broadcast SNTP mode via Ethernet network
Message (IEC103): Clock messages through IEC103 protocol
 Advanced
IEEE1588: Clock message via IEEE1588

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-09-07
7 Settings
IRIG-B (Fiber): IRIG-B via optical-fibre interface
PPS (Fiber) PPS: Pulse per second (PPS) via optical-fibre interface
 NoTimeSync
When no time synchronization signal is connected to the device, please select this option and the
alarm message [Alm_TimeSyn] will not be issued anymore.
“Conventional” mode and “SAS” mode are always be supported by the device, but “Advanced”
mode is only supported when NET-DSP module is equipped. The alarm signal [Alm_TimeSyn]
may be issued to remind user loss of time synchronization signals.
1) When “SAS” is selected, if there is no conventional clock synchronization signal, the device
will not send the alarm signal [Alm_TimeSyn]. When “Conventional” mode is selected, if there
is no conventional clock synchronization signal, “SAS” mode will be enabled automatically
with the alarm signal [Alm_TimeSyn] issued simultaneously.
2) When “Advanced” mode is selected, if there is no conventional clock synchronization signal

connected to NET-DSP module, “SAS” mode is enabled automatically with the alarm signal
[Alm_TimeSyn] issued simultaneously.
3) When “NoTimeSyn” mode is selected, the device will not send alarm signals without time
synchronization signal. But the device can be still synchronized if receiving time
synchronization signal.
NOTICE!
The clock message via IEC 60870-5-103 protocol is invalid when the device receives
the IRIG-B signal through RCS-485 port.
15. IP_Server_SNTP
It is the address of the SNTP time synchronization server which sends SNTP timing messages to
the relay or BCU.
16. IP_StandbyServer_SNTP
Both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are ineffective unless SNTP clock

synchronization is valid.
When both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are set as "000.000.000.000", the

device receives broadcast SNTP synchronization message.
When either [IP_Server_SNTP] or [IP_StandbyServer_SNTP] is set as "000.000.000.000", the

device adopts the setting whose value is not equal to "000.000.000.000" as SNTP server address
and receives unicast SNTP synchronization message.
If neither [IP_Server_SNTP] nor [IP_StandbyServer_SNTP] is set as "000.000.000.000", the

device adopts the setting [IP_Server_SNTP] as SNTP server address to receive unicast SNTP
synchronization message. If the device does not receive any server response after 30s, it adopts
the setting [IP_StandbyServer_SNTP] as SNTP server address to receive unicast SNTP

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7 Settings
synchronization message.
The device will switch between [IP_Server_SNTP] and [IP_StandbyServer_SNTP] repeatedly if it

does not receive any server response in 30s.
17. OffsetHour_UTC, OffsetMinute_UTC
If the IEC61850 protocol is adopted in substations, the time tags of communication messages are
required according to UTC (Universal Time Coordinated) time.
The setting [OffsetHour_UTC] is used to set the hour offset of the current time zone to the GMT
(Greenwich Mean Time) zone; for example, if a relay is applied in China, the time zone of China is
east 8th time zone, so this setting is set as “8”. The setting [OffsetMinute_UTC] is used to set the
minute offset of the current time zone to the GMT zone.
st nd rd th th
Time zone GMT zone East 1 East 2 East 3 East 4 East 5
Setting 0 1 2 3 4 5
th th th th th
Time zone East 6 East 7 East 8 East 9 East 10 East 11th
Setting 6 7 8 9 10 11
th st nd rd th
Time zone East/West 12 West 1 West 2 West 3 West 4 West 5th
Setting 12/-12 -1 -2 -3 -4 -5
th th th th th
Time zone West 6 West 7 West 8 West 9 West 10 West 11th
Setting -6 -7 -8 -9 -10 -11
18. Opt_Display_Status
This setting is used to set display mode of current and voltage in fault records, primary value or
secondary value. The sampled values of current and voltage are displayed as secondary value by
default. When it is set as primary value, both secondary voltage and secondary current are
converted into primary voltage and primary current according to rated secondary and primary
value of VT and CT respectively.
19. Num_Cyc_PreTrigDFR
The setting is used to set the cycle number recorded by the device before the trigger element
operating.
20. Cfg_NetPorts_Bond
This setting consists of 8 bits, two bits of them must set as “1”, and the rest bits must be set as “0”.
The two bits is corresponding with two communication ports which is used by master and salve
backup.
21. En_TCPx_DNP
The logic setting is used to enable or disable network No.x DNP client. (x=1, 2, 3, 4)
1: enable
0: disable
When network No.x DNP client is not configured to be in service by PCS-Explorer, DNP client

Date: 2016-06-22
-09-07
7 Settings
settings corresponding to network No.x will be hidden.
22. Addr_Slave_TCPx_DNP
It is the slave address of network No.x DNP client. (x=1, 2, 3, 4)
23. Addr_Master_TCPx_DNP
It is the master address of network No.x DNP client. (x=1, 2, 3, 4)
24. IP_Master_TCPx_DNP
It is the IP address of network No.x DNP client. (x=1, 2, 3, 4)
25. Opt_Map_TCPx_DNP
It is the communication map number of network No.x DNP client. (x=1, 2, 3, 4)
26. Obj01DefltVar_TCPx_DNP
It is the “OBJ1” default variation of network No.x DNP client. (x=1, 2, 3, 4)
BISingleBit: Binary Input format is packed with single bit
BIWithStatus: Binary Input with status flag
BIChWoutT: Binary Input Event without time-of-occurrence
BIChWithAbsTime: Binary Input Event with absolute time-of-occurrence
BIChWithRelTime: Binary Input Event with relative time-of-occurrence
AI32Int: Analog Input with a flag octet and a 32-bit, signed integer value
AI16Int: Analog Input with a flag octet and a 16-bit, signed integer value
AI32IntWoutF: Analog Input with a 32-bit (but without flags)
AI16IntWoutF: Analog Input with a 16-bit (but without flags)
AI32Flt: Analog Input with a flag octet and a single-precision, floating-point value
AI32IntEvWoutT: Analog Input Event with a flag octet and a 32-bit, signed integer value (but
without time-of-occurence)
AI16IntEvWoutT: Analog Input Event with a flag octet and a 16-bit, signed integer value (but

Date: 2016-06-22
7 Settings
without time-of-occurence)
AI32FltEvWoutT: Analog Input Event with single-precision, floating-point value (but without
time-of-occurence)
AO32Int: Analog Output with a flag octet and a 32-bit, signed integer value
AO16Int: Analog Output with a flag octet and a 16-bit, signed integer value
AO32Flt: Analog Output with a flag octet and a single-precision, floating-point value
31. t_AppLayer_TCPx_DNP
It is the timeout of application layer of network No.x DNP client. (x=1, 2, 3, 4)
32. t_KeepAlive_TCPx_DNP
It is the heartbeat time interval of network No.x DNP client. (x=1, 2, 3, 4)
33. En_UR_TCPx_DNP
The logic setting is used to enable or disable the unsolicited message function of network No.x
DNP client. (x=1, 2, 3, 4)
1: enable
0: disable
34. Num_URRetry_TCPx_DNP
It is the online retransmission number of the unsolicited message of network No.x DNP client. (x=1,
2, 3, 4)
35. t_UROfflRetry_TCPx_DNP
It is the offline timeout of the unsolicited message of network No.x DNP client. (x=1, 2, 3, 4)
36. Class_BI_TCPx_DNP
It is the class level of the “Binary Input” of network No.x DNP client. (x=1, 2, 3, 4)
37. Class_AI_TCPx_DNP
It is the class level of the “Analog Input” of network No.x DNP client. (x=1, 2, 3, 4)
38. t_Select_TCPx_DNP
It is the selection timeout of network No.x DNP client. (x=1, 2, 3, 4)
39. t_TimeSynIntvl_TCPx_DNP
It is the time interval of the time synchronization function of network No.x DNP client. (x=1, 2, 3, 4)

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-09-07
7 Settings
7.1.3 Access Path

MainMenu→“Settings”→“Device Setup”

Date: 2016-06-22
Table of Contents
8.1 Overview ........................................................................................................... 8-1
8.1.1 Keypad Operation................................................................................................................. 8-2
8.1.2 LED Indications .................................................................................................................... 8-3
8.1.3 Front Communication Port ................................................................................................... 8-4
8.1.4 Ethernet Pot Setup ............................................................................................................... 8-4
8.2 Menu Tree ......................................................................................................... 8-5

8.2.1 Overview ............................................................................................................................... 8-5
8.2.2 Main Menus .......................................................................................................................... 8-6
8.2.3 Sub Menus ........................................................................................................................... 8-7
8.3 Access Authority Management ..................................................................... 8-25

8.3.1 Authority Classification ....................................................................................................... 8-25
8.3.2 Authority Identification ........................................................................................................ 8-26
8.4 LCD Display ................................................................................................... 8-27

8.4.1 Overview ............................................................................................................................. 8-27
8.4.2 Function Shortcuts Key ...................................................................................................... 8-28
8.4.3 Normal Display ................................................................................................................... 8-31
8.4.4 Display Disturbance Records ............................................................................................. 8-32
8.4.5 Display Supervision Event ................................................................................................. 8-34
8.4.6 Display IO Events ............................................................................................................... 8-35
8.4.7 Display Device Logs ........................................................................................................... 8-36
8.5 Keypad Operation .......................................................................................... 8-37

8.5.1 View Device Measurements ............................................................................................... 8-37
8.5.2 View Device Status ............................................................................................................. 8-37
8.5.3 View Device Records ......................................................................................................... 8-37
8.5.4 Print Device Records.......................................................................................................... 8-38

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8.5.5 View Device Setting ........................................................................................................... 8-39
8.5.6 Modify Device Setting......................................................................................................... 8-39
8.5.7 Copy Device Setting ........................................................................................................... 8-42
8.5.8 Switch Setting Group.......................................................................................................... 8-42
8.5.9 Delete Device Records....................................................................................................... 8-43
8.5.10 Remote Control via SLD................................................................................................... 8-44
8.5.11 Modify Device Clock ......................................................................................................... 8-46
8.5.12 View Module Information .................................................................................................. 8-47
8.5.13 Check Software Version ................................................................................................... 8-47
8.5.14 Communication Test ......................................................................................................... 8-47
8.5.15 Select Language .............................................................................................................. 8-48
List of Figures
Figure 8.1-1 Front panel of PCS-978 ......................................................................................... 8-1
Figure 8.1-2 Keypad mounted on the front panel .................................................................... 8-2
Figure 8.1-3 Default configuration of LED indications ............................................................ 8-3
Figure 8.1-4 Corresponding cable of the RJ45 port in the front panel .................................. 8-4
Figure 8.1-5 Rear view and terminal definition of NR1102M .................................................. 8-5
Figure 8.2-1 Menu tree ................................................................................................................ 8-7
List of Tables
Table 8.1-1 Definition of the 8-core cable ................................................................................. 8-4
Table 8.4-1 Tripping report messages .................................................................................... 8-34
Table 8.4-2 User operating event list....................................................................................... 8-36
Table 8.4-1 Primary equipment symbols in SLD .................................................................... 8-44

Date: 2016-06-22
The operator can access the protective device from the front panel. Local communication with the
protective device is possible using a computer via a multiplex RJ45 port on the front panel.
Furthermore, remote communication is also possible using a PC with the substation automation
system via rear RS485 port or rear Ethernet port. The operator is able to check the protective
device status at any time.
This chapter describes human machine interface (HMI), and give operator an instruction about
how to display or print event report, setting and so on through HMI menu tree and display metering
value, including RMS current, voltage and frequency etc. through LCD. Procedures to change
active setting group or a settable parameter value through keypad are also described in details.
NOTICE!
About three measurements in menu “Measurements”, please refer to the following

description:
“Measurements1” is use to display measured values from protection calculation DSP

(displayed in secondary value)
“Measurements2” is used to display measured values from fault detector DSP

(displayed in secondary value)
“Measurements3” is used to display measured primary values and other calculated

quantities.
8.1 Overview
The human-machine interface consists of a human-machine interface (HMI) module which allows
a communication to be as simple as possible for the user. The HMI module helps to draw your
attention to something that has occurred which may activate a LED or a report displayed on the
LCD. Operator can locate the data of interest by navigating the keypad.
1
HEALTHY
11
PCS-978
2 12
5
ALARM TRANSFORMER RELAY
3 13
TRIP
4 14
GRP
5 15
6 16 ENT
ESC
7 17
4
8 18
1
9 19
3
10 20
Figure 8.1-1 Front panel of PCS-978
The function of HMI module:

Date: 2016-06-22

A 320×240 dot matrix backlight LCD display is visible in dim lighting
1 LCD conditions. The corresponding messages are displayed when there is
operation implemented.
20 status indication LEDs, first three LEDs are fixed as the signals of
2 LED “HEALTHY” , “ALARM” and “TRIP”, others are configurable with
selectable color among green, yellow and red.
3 Keypad Navigation keypad and command keys for full access to device
4 Communication port a multiplex RJ45 port for local communication with a PC
5 Logo Type and designation and manufacturer of device
8.1.1 Keypad Operation GR

P
ENT
ESC
Figure 8.1-2 Keypad mounted on the front panel
1. “ESC”:
 Cancel the operation
 Quit the current menu
2. “ENT”:
 Execute the operation
 Confirm the interface
3. “GRP”
 Activate the switching interface of setting group
4. leftward and rightward direction keys (“◄” and “►”):
 Move the cursor horizontally
 Enter the next menu or return to the previous menu
5. upward and downward direction keys (“▲” and “▼”)
 Move the cursor vertically
 Select command menu within the same level of menu
6. plus and minus sign keys (“＋” and “－”)
 Modify the value

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 Modify and display the message number
 Page up/down
8.1.2 LED Indications
HEALTHY
ALARM
TRIP
Figure 8.1-3 Default configuration of LED indications
A brief explanation has been made as bellow.
LED Display Description

When the equipment is out of service or any hardware error is detected
Off
HEALTHY during self-check.
Green Lit when the equipment is in service and ready for operation.
Off When equipment in normal operating condition.

ALARM
Yellow Lit when VT circuit failure, CT circuit failure or other abnormal alarm is issued.
TRIP Off When the equipment is in normal operating condition.
(Default) Red Lit when any protection element trips.
NOTICE!
“HEALTHY” LED can only be turned on by energizing the device and no abnormality
detected.
“ALARM” LED is lit when abnormalities of equipment occurs like above mentioned and
can be turned off after abnormalities are removed except alarm report [Alm_CTS] which
can only be reset only when the failure is removed and the equipment is rebooted or
re-energized.
The third LED is set to be “TRIP” by default, but user can modify the configuration of
this LED. If it is set as “TRIP”, it lit and latched once any protection element operates.
The “TRIP” LED can be turned off by pressing the signal RESET button on the front
panel.
Other LED indicators with no labels are configurable and user can configure them to be
lit by signals of operation element, alarm element and binary output contact according

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to requirement through PCS-Explorer software, and there are three colors (green,
yellow and red) for user selection.
8.1.3 Front Communication Port
There is a multiplex RJ45 port on the front panel. This port can be used as an RS-232 serial port
as well as a twisted-pair Ethernet port. As shown in the following figure, a customized cable is
applied for debugging via this multiplex RJ45 port.
P2
P1
P3
Figure 8.1-4 Corresponding cable of the RJ45 port in the front panel
In the above figure and the following table:
P1: To connect the multiplex RJ45 port. An 8-core cable is applied here.
P2: To connect the twisted-pair Ethernet port of the computer.
P3: To connect the RS-232 serial port of the computer.
The definition of the 8-core cable in the above figure is introduced in the following table.
Table 8.1-1 Definition of the 8-core cable
Device side Computer side

Terminal No. Core color Function
(Left) (Right)
1 Orange & white TX+ of the ethernet port P1-1 P2-1
2 Orange TX- of the ethernet port P1-2 P2-2
3 Green & white RX+ of the ethernet port P1-3 P2-3
4 Blue TXD of the RS-232 serial port P1-4 P3-2
5 Brown & white RXD of the RS-232 serial port P1-5 P3-3
6 Green RX- for the ethernet port P1-6 P2-6
7 Blue & white The ground connection of the P1-7
P3-5
8 Brown RS-232 port. P1-8
8.1.4 Ethernet Pot Setup
MON plug-in module is equipped with two or four 100Base-TX Ethernet interface, take NR1102M
as an example, as shown in Figure 8.1-5.
The Ethernet port can be used to communication with PC via auxiliary software (PCS-Explorer)

Date: 2016-06-22
after connecting the protection device with PC, so as to fulfill on-line function (please refer to the
instruction manual of PCS-Explorer). At first, the connection between the protection device and PC
must be established. Through setting the IP address and subnet mask of corresponding Ethernet
interface in the menu “Settings→Device Setup→Comm Settings”, it should be ensured that the
protection device and PC are in the same network segment. For example, setting the IP address
and subnet mask of network A. (using network A to connect with PC).
PC: IP address is set as “198.87.96.102”, subnet mask is set as “255.255.255.0”
The IP address and subnet mask of protection device should be [IP_LAN2]=198.87.96.XXX,

[Mask_LAN2]=255.255.255.0, [En_LAN2]=1. (XXX can be any value from 0 to 255 except 102)
If the logic setting [En_LAN2] is non-available, it means that network A is always enabled.
NR1102M
ETHERNET
Network A
Network B
Network C
Network D
Figure 8.1-5 Rear view and terminal definition of NR1102M
NOTICE!
If using other Ethernet port, for example, Ethernet B, the logic setting [En_LAN2] must
be set as “1”.
8.2 Menu Tree
8.2.1 Overview
Press “▲” of any running interface and enter the main menu. Select different submenu by “▲” and
“▼”. Enter the selected submenu by pressing “ENT” or “►”. Press “◄” and return to the previous
menu. Press “ESC” back to main menu directly. For sake of entering the command menu again, a
command menu will be recorded in the quick menu after its execution. Five latest command

Date: 2016-06-22
menus can be recorded in the quick menu. When five command menus are recorded, the latest
command menu will cover the earliest one, adopting the “first in first out” principle. It is arranged
from top to bottom and in accordance with the execution order of command menus.
Press “▲” to enter the main menu with the interface as shown in the following diagram:
MainMenu
Language
Clock
Quick Menu
For the first powered device, there is no record in quick menu. Press “▲” to enter the main menu
with the interface as shown in the following diagram:
Measurements
Status
Records
Settings
Print
Local Cmd
Information
Test
Clock
Language
The descriptions about menu are based on the maximized configuration, for a specific project, if
some function is not available, the corresponding submenu will hidden.
8.2.2 Main Menus

The menu of PCS-978 is organized into main menu and submenus, much like a PC directory
structure. The menu of PCS-978 is divided into 10 sections:

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Main Menu
Measurements
Status
Records
Settings
Print
Local Cmd
Information
Test
Clock
Language
Figure 8.2-1 Menu tree
Under main interface, press “▲” to enter main menu, and select submenu by pressing “▲”, “▼”
and “ENT”. The command menu adopts a tree shaped content structure. The above diagram
provides the integral structure and all main menus (first-level menus) under menu tree of the
device.
8.2.3 Sub Menus

8.2.3.1 Measurements
Main Menu
Measurements
Measurements1
Measurements2
Measurements3
This menu is used to display real-time measured values, including AC voltage, AC current, phase
angle and calculated quantities. These data can help users to acquaint the device′s status. This
menu comprises following submenus. Please refer to section “Measurement” about the detailed
measured values.

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No. Item Function description
1 Measurements1 Display sampled and calculated values on protection DSP module.
2 Measurements2 Display sampled and calculated values on fault detector DSP module.
3 Measurements3 Display measured values and other calculated quantities.
The submenu “Measurements1” comprises the following command menus.
Main Menu
Measurements
Measurements1
HVS Measurements
MVS Measurements
LVS Measurements
CWS Measurements
OvExc Measurements
Diff Measurements
REF Measurements
WDIF Measurements
Display measured values and corresponding phase angles of HV side on

1 HVS Measurements
protection calculation DSP.
Display measured values and corresponding phase angles of MV side

2 MVS Measurements
on protection calculation DSP.
Display measured values and corresponding phase angles of LV side on

3 LVS Measurements
protection calculation DSP.
Display measured values of common winding side on protection

4 CWS Measurements
calculation DSP.
Display measured values of overexcitation protection on protection

5 OvExc Measurements
calculation DSP.
Display currents for current differential protection and corresponding

6 Diff Measurements
phase angles on protection calculation DSP.
Display corrected currents for REF protection and corresponding phase

7 REF Measurements
angles on protection calculation DSP.
Display measured values and corresponding phase angles of winding

8 WDIF Measurements
differential protection on protection calculation DSP.

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Main Menu
Measurements
Measurements2
HVS Measurements
MVS Measurements
LVS Measurements
CWS Measurements
OvExc Measurements
Diff Measurements
REF Measurements
WDIF Measurements
Display measured values and corresponding phase angles of HV side on

1 HVS Measurements
fault detector DSP.
Display measured values and corresponding phase angles of MV side

2 MVS Measurements
on fault detector DSP.
Display measured values and corresponding phase angles of LV side on

3 LVS Measurements
fault detector DSP
4 CWS Measurements Display measured values of common winding side on fault detector DSP.
Display measured values of overexcitation protection on fault detector

5 OvExc Measurements
DSP.
Display currents for current differential protection and corresponding

6 Diff Measurements
phase angles on fault detector DSP.
Display corrected currents for REF protection and corresponding phase

7 REF Measurements
angles on fault detector DSP.
Display measured values and corresponding phase angles of winding

8 WDIF Measurements
differential protection on fault detector DSP.

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Main Menu
Measurements
Measurements3
Power Measurements
Temp Measurements
Display measured values, such as active power, reactive power,

1 Power Measurements
apparent power and power factor.
2 Temp Measurements Display measured temperature for temperature protection.
8.2.3.2 Status
Main Menu
Status
Inputs
Outputs
Superv State
This menu is used to display real time input signals, output signals and alarm signals of the device.
These data can help users to acquaint the device′s status. This menu comprises following
submenus. Please respectively refer to section “Signal List” about the detailed introduction of input
signals and output signals, and section “Supervision Alarms” about the detailed introduction of
alarm signals.
1 Inputs Display all input signal states
2 Outputs Display all output signal states
3 Superv State Display supervision alarm states
The submenu “Inputs” comprises the following command menus.

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Main Menu
Status
Inputs
Contact Inputs
GOOSE Inputs
1 Contact Inputs Display states of binary inputs derived from opto-isolated channels
2 GOOSE Inputs Display states of GOOSE binary inputs.
The submenu “Outputs” comprises the following command menus.
Main Menu
Status
Outputs
Contact Outputs
GOOSE Outputs
1 Contact Outputs Display states of contact binary outputs
2 GOOSE Outputs Display states of GOOSE binary outputs
The submenu “Superv State” comprises the following command menus.
Main Menu
Status
Superv State
Prot Superv
FD Superv
GOOSE Superv
SV Superv

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1 Prot Superv Display states of self-supervision signals from protection calculation DSP
2 FD Superv Display states of self-supervision signals from fault detector DSP
3 GOOSE Superv Display states of GOOSE self-supervision signals
4 SV Superv Display states of SV self-supervision signals
8.2.3.3 Records
Main Menu
Records
Disturb Records
Superv Events
IO Events
Device Logs
Control Logs
Clear Records
This menu is used to display all kinds of records, including the disturbance records, supervision
events, binary events and device logs, so that the operator can load to view and use as the
reference of analyzing accidents and repairing the device. All records are stored in non-volatile
memory, it can still record them even if it loses its power.
This menu comprises the following submenus.
1 Disturb Records Display disturbance records of the device
2 Superv Events Display supervision events of the device
3 IO Events Display binary events of the device
4 Device Logs Display device logs of the device
5 Control Logs Display control logs of the device
6 Clear Records Clear all records.

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8.2.3.4 Settings
Main Menu
Settings
System Settings
Prot Settings
Logic Links
Device Setup
Confirm Settings
This menu is used to check the device setup, system parameters, protection settings and logic
links settings, as well as modifying any of the above setting items. Moreover, it can also execute
the setting copy between different setting groups.
1 System Settings Check or modify the system parameters
2 Prot Settings Check or modify the protection settings
Check or modify the logic links settings, including function links, SV links,
3 Logic Links
GOOSE links and spare links
4 Device Setup Check or modify the device setup
The menu is hidden by default, and when it is visible, it can be used to

5 Confirm Settings
confirm all settings of this device.
The submenu “Prot Settings” includes the following command menus.

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Main Menu
Settings
Prot Settings
Diff Prot Settings
HVS REF Prot Settings
MVS REF Prot Settings
LVS REF Prot Settings
WdgDiff Prot Settings
Overexcitation Prot Settings
Frequency Prot Settings
Mechanical Prot Settings
OverTemp Prot Settings
HVS Backup Prot Settings
MVS Backup Prot Settings
LVS Backup Prot Settings
CWS Backup Prot Settings
Prog Logic Settings
Copy Settings
1 Diff Prot Settings Display and modify the settings of current differential protection.
2 HVS REF Prot Settings Display and modify the settings of REF protection of HV side.
3 MVS REF Prot Settings Display and modify the settings of REF protection of MV side.
4 LVS REF Prot Settings Display and modify the settings of REF protection of LV side.
5 WdgDiff_Prot_Settings Display and modify the settings of winding differential protection.
6 Overexcitation Prot Settings Display and modify the settings of overexcitation protection.
7 Frequency Prot Settings Display and modify the settings of frequency protection.
8 Mechanical Prot Settings Display and modify the settings of mechanical protection.
9 OverTemp Prot Setting Display and modify the settings of temperature protection.
10 HVS Backup Prot Settings Display and modify the settings of backup protection of HV side.
11 MVS Backup Prot Settings Display and modify the settings of backup protection of MV side.
12 LVS Backup Prot Settings Display and modify the settings of backup protection of LV side.
13 CWS Backup Prot Settings Display and modify the settings of backup protection of common winding

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side.
14 Prog Logic Settings Display and modify the programmable tripping logic settings.
15 Copy Settings Copy setting between different setting groups
The submenu “Logic Links” comprises the following command menus.
Main Menu
Settings
Logic Links
Function Links
GOOSE Send Links
GOOSE Recv Links
SV Links
1 Function Links Check or modify function links settings
2 GOOSE Send Links Check or modify GOOSE sending links settings
3 GOOSE Recv Links Check or modify GOOSE receiving links settings
4 SV Links Check or modify SV links settings
The submenu “Device Setup” comprises the following command menus.
Main Menu
Settings
Device Setup
Device Settings
Comm Settings
Label Settings
1 Device Settings Check or modify the device settings.
2 Comm Settings Check or modify the communication settings.
3 Label Settings Check or modify the label settings of each protection element.

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8.2.3.5 Print
Main Menu
Print
Device Info
Settings
Disturb Records
Superv Events
IO Events
Device Logs
Device Status
Waveforms
IEC103 Info
Cancel Print
This menu is used to print device description, settings, all kinds of records, waveforms, information
related with IEC60870-5-103 protocol, channel state and channel statistic.
Print the description information of the device, including software

1 Device Info
version.
Print device setup, system parameters, protection settings and logic

links settings. It can print by different classifications as well as printing all
2 Settings
settings of the device. Besides, it can also print the latest modified
settings.
3 Disturb Records Print the disturbance records
4 Superv Events Print the supervision events
5 IO Events Print the binary events
6 Device Logs Print running and operation reports of the device.
Print the current state of the device, including the sampled value of
7 Device Status
voltage and current, the state of binary inputs, setting and so on
8 Waveforms Print the recorded waveforms
Print 103 Protocol information, including function type (FUN),

9 IEC103 Info information serial number (INF), general classification service group
number, and channel number (ACC)
10 Cancel Print Cancel the print command

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The submenu “Settings” comprises the following submenus.
Main Menu
Print
Settings
System Settings
Prot Settings
Logic Links
Device Setup
All Settings
Latest Chgd Settings
1 System Settings Print the system parameters
2 Prot Settings Print the protection settings
3 Logic Links Print the logic links settings
4 Device Setup Print the settings related to device setup
Print all settings including device setup, system parameters, protection

5 All Settings
settings and logic links settings
6 Latest Chgd Settings Print the setting latest modified
The submenu “Prot Settings” comprises the following command menus.

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Main Menu
Print
Settings
Prot Settings
Diff Prot Settings
HVS REF Prot Settings
MVS REF Prot Settings
LVS REF Prot Settings
WdgDiff Prot Settings
Overexcitation Prot Settings
Frequency Prot Settings
Mechanical Prot Settings
OverTemp Prot Settings
HVS Backup Prot Settings
MVS Backup Prot Settings
LVS Backup Prot Settings
CWS Backup Prot Settings
Prog Logic Settings
All Settings
1 Diff Prot Settings Print the settings of current differential protection.
2 HVS REF Prot Settings Print the settings of REF protection of HV side.
3 MVS REF Prot Settings Print the settings of REF protection of MV side.
4 LVS REF Prot Settings Print the settings of REF protection of LV side.
5 WdgDiff_Prot_Settings Print the settings of winding differential protection.
6 Overexcitation Prot Settings Print the settings of overexcitation protection.
7 Frequency Prot Settings Print the settings of frequency protection.
8 Mechanical Prot Settings Print the settings of mechanical protection.
9 OverTemp Prot Settings Print the settings of temperature protection.
10 HVS Backup Prot Settings Print the settings of backup protection of HV side.
11 MVS Backup Prot Settings Print the settings of backup protection of MV side.

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12 LVS Backup Prot Settings Pint the settings of backup protection of LV side.
13 CWS Backup Prot Settings Pint the settings of backup protection of common winding side.
14 Prog Logic Settings Print the programmable tripping logic settings.
15 All Settings Print all settings included in “Prot Settings” submenu
The submenu “Logic Links” comprises the following command menus.
Main Menu
Print
Settings
Logic Links
Function Links
GOOSE Send Links
GOOSE Recv Links
SV Links
All Settings
1 Function Links Print function links settings
2 GOOSE Send Links Print GOOSE sending links settings
3 GOOSE Recv Links Print GOOSE receiving links settings
4 SV Links Print SV links settings
5 All Settings Print all settings included in “Logic Links” submenu
The submenu “Device Setup” comprises the following command menus.

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Main Menu
Print
Settings
Device Setup
Device Settings
Comm Settings
Label Settings
All Settings
1 Device Settings Print the device settings.
2 Comm Settings Print the communication settings.
3 Label Settings Print the label settings of each protection element.
4 All Settings Print all settings included in “Device Setup” submenu
The submenu “Waveforms” includes the following command menus.
Main Menu
Print
Waveforms
Diff Wave
HVS Wave
MVS Wave
LVS Wave
CWS Wave
1 Diff Wave Print differential current waveforms.
2 HVS Wave Print voltage and current waveforms of HV side.
3 MVS Wave Print voltage and current waveforms of MV side.
4 LVS Wave Print voltage and current waveforms of LV side.
5 CWS Wave Print voltage and current waveforms of common winding side.

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8.2.3.6 Local Cmd
Main Menu
Local Cmd
Reset Target
Trig Oscillograph
Control
Download
Clear Counter
Clear Energy Counter
This menu is used to reset the tripping relay with latch, indicator LED, LCD display, and as same
as the reset function of binary inputs. This menu provides a method of manually recording the
current waveform data of the device under normal condition for printing and uploading SAS.
Besides, it can send out the request of program download, clear statistic information about
GOOSE, SV and energy.
1 Reset Target Reset the local signal, indicator LED, LCD display and so on
2 Trig Oscillograph Trigger waveform recording
3 Control Manually operating to trip, close output or for signaling purpose
4 Download Send out the request of downloading program
5 Clear Counter Clear GOOSE and SV statistic data
Clear all energy metering values (i.e., PHr+_Pri, PHr-_Pri, Qr+_Pri,

6 Clear Energy Counter
QHr-_Pri)
8.2.3.7 Information
Main Menu
Information
Version Info
Board Info
In this menu, LCD can display software information of all kinds of intelligent plug-in modules,
which consists of version, creating time of software, CRC codes and management sequence
number. Besides, plug-in module information can also be viewed.

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This menu comprises the following command menus.
Display software information of DSP module, MON module and HMI module,
1 Version Info which consists of version, creating time of software, CRC codes and
management sequence number.
2 Board Info Monitor the current working state of each intelligent module.
8.2.3.8 Test
Main Menu
Test
GOOSE Comm Counter
SV Comm Counter
Device Test
Internal Signal
HMI Setup
NetPortBond Info
This menu is mainly used for developers to debug the program and for engineers to maintain the
device. It can be used to fulfill the communication test function. It is also used to generate all kinds
of reports or events to transmit to the SAS without any external input, so as to debug the
communication on site. Besides, it can also display statistic information about GOOSE, SV, AR
and FO channel.
1 GOOSE Comm Counter Check communication statistics data of GOOSE
2 SV Comm Counter Check communication statistics data of SV (Sampled Values)
Automatically generate all kinds of reports or events to transmit to SCADA,

including disturbance records, self-supervision events and binary events. It
3 Device Test
can realize the report uploading by different classification, as well as the
uploading of all kinds of reports
4 Internal Signal This submenu is only reserved for the manufacturer
5 HMI Setup Configure LCD display and check LCD display and LED indicators
6 NetPortBond Info Check information about bond port
The submenu “Device Test” comprises the following submenus.

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Main Menu
Test
Device Test
Disturb Events
Superv Events
IO Events
View the relevant information about disturbance records (only used for
1 Disturb Events
debugging persons)
View the relevant information about supervision events (only used for
2 Superv Events
debugging persons)
View the relevant information about binary events (only used for debugging
3 IO Events
persons)
Users can respectively execute the test automatically or manually by selecting commands “All
Test” or “Select Test”.
The submenu “Disturb Events” comprises the following command menus.
Main Menu
Test
Device Test
Disturb Events
All Test
Select Test
1 All Test Ordinal test of all protection elements
2 Select Test Selective test of corresponding classification
The submenu “Superv Events” comprises the following command menus.

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Main Menu
Test
Device Test
Superv Events
All Test
Select Test
1 All Test Ordinal test of all self-supervisions
The submenu “IO Events” comprises the following command menus.
Main Menu
Test
Device Test
IO Events
All Test
Select Test
1 All Test Ordinal test of change of all binary inputs
The submenu “HMI Setup” comprises the following command menus.

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Main Menu
Test
HMI Setup
Contrast
BacklitDur
LgtIntnsty
SupervLCD
SupervLED
1 Contrast To adjust the contrast of LCD display
2 BacklitDur To adjust the duration of LCD backlight
3 Lgtlntnsty To adjust the brightness of LCD display
4 SupervLCD To find out dead pixel of LCD display
5 SupervLED To find out broken LED indicator 03~20
8.2.3.9 Clock
The current time of internal clock can be viewed here. The time is displayed in the form
YY-MM-DD and hh:mm:ss. All values are presented with digits and can be modified.
8.2.3.10 Language
This menu is mainly used to set LCD display language.
8.3 Access Authority Management

In order to conveniently manage access authority, the device support setup up to 40 users and
allow each user to own different password (user password can support 8 characters at most and
must include one lowercase letter, one capital letter and one number at least) and access authority
(such as modify settings, view records, remote control)
According to different access authority, the corresponding operations to the device by LCD panel
can be allowed to perform. For the operation that requires authorization, the corresponding user
logs in and the correct password must be input after the operation can be performed.
8.3.1 Authority Classification

The devie provide five kinds of authorities: View, Control, Setting, Test, Design. The default
configuration of the device is no multi-users. Each item of different authority class can be enabled
or disabled independently, and the operation without access authority can be performed directly
no password provided. The valid time of the password can be set, and the password need not be

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input again within the valid time ,which ensure both security and convenience.
8.3.2 Authority Identification

The operation is as follows:
1. Press the “▲” to enter the main menu, the following interface will be shown when performing
an operation. (Multi-users have been configured in advance)
2. Press the “◄” or “►” to select username, and press the “ESC” to exit this menu
Username Setting
Password
3. Press the “ENT” or “▼” to move, and the following interface will be shown after the username
is confirmed.
Username Setting
Password ******
0 1 2 3 4 5 6 7 8 9 [OK]
4. Press the “◄” or “►” to select number or letter, and press “ENT” to ensure selected character.
5. Press the “▲” or “▼” to page up/down to select previous group or next group characters.
6. Press the “GRP” to switch uppercase or lowercase to be choosen characters.

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7. When the password reaches to 8 bits, the device will verify whether the username and
password are correctly. If the password is shorter than 8 bits, select and press “OK” to begin
to verify whether the username and password are correctly.
8. Press the “ESC” to cancel entered character during entering password, and the password will
be cleared if the password check fails. When the password is cleared, press the “ESC” to
select the username again.
9. The device provides the function of password memory, the following interface will be shown if
the valid time of the password is set and last entered password is no timeout.
Username Setting
Password *******
10. Press the “ENT” to verify the password, press the “◄” or “►” to switch the username and the
password will be cleared, and press the “ESC” to exit the interface.
11. If the password is correct and the user owns the authority of the operation performed, the
operation will be performed.
If the password is incorrect, the device will issue an alarm signal “Password Error”. If the password
is correct but the user has no the authority of the operation performed, the device will issue an
alarm signal “Unauthorized”. If the password is incorrect or the user has no the authority of the
operation performed more than three times, the device will issue an alarm signal “PWD Error or
Unauthorized, Screen Locked” and the device will return to main interface after the screen is
locked for 1 minutes, which will be recorded in device log.
8.4 LCD Display
8.4.1 Overview
There are some kinds of LCD display, SLD (single line diagram) display, disturbance records,
supervison events, IO events, control logs and device logs. Disturbance records and supervison
events will not disappear until them are acknowledged by pressing the “RESET” button in the
protection panel (i.e. energizing the binary input [BI_RstTarg]). If any event is detected, the

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corresponding event display will pop up automatically, and user can keep pressing “ENT” and then
press “ESC” to switch between normal display and event display. IO events will be displayed for 5s
and then it will return to the previous display interface automatically. Device logs will not pop up
and can only be viewed by navigating the corresponding menu.
8.4.2 Function Shortcuts Key

The device provide some function shortcuts key, which can be configured by PCS-Explorer and be
fulfilled by combination key of devices' keypad, to excute some operation quickly.
8.4.2.1 Shortcuts Key Configuration
1. Right-click the menu “LCD Graph”, and select the menu item “Edit Shortcut Key” to display
the configuration interface of function key shortcuts as shown below.
2. In configuration interface, double-click the table item in the list of “Extend Command” to select
LCD extend command of dropdown list corresponding with keypads in front panel as shown
below. Select the first blank item in dropdown list to cancel the setup.
3. Double-click the table item in the list of “Attribute” to edit the attribute of keypad in front panel
as shown below. When the attribute is set as “1”, the corresponding operation can not excute

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unless input correct password. When the attribute is set as “0” or blank, password is not
required. After finishing configuration, click the button “OK”.
4. The name description of extend command can be modified in signal setup interface, the
operation “Refresh” in the interface of “Source” must be excute at first before configuring
function shortcuts key or generating drive file package.
5. Right-click device node and excute the menu “Compress Driver File” to generate drive file
package of the device. The file “LCDConfig.txt” in drive file package of the device records
related contents about shortcuts key. If shortcuts keys are not required, set “Extend
Command” corresponding with function shortcuts key as blank, and generate drive file
package of the device again.

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8.4.2.2 Function Description
In general, the function of “GRP” is switch setting group, however, the original function of “GRP” is
blocked when configuring function shortcuts key. (the setting group can be switched by shortcuts
key, binary input or modifying the setting) Under main interface, press “GRP” to display the
interface of function shortcuts key and press “ESC” to return to main interface.
Shortcut keys
[ ] Extended_Command04
[ + ] Extended_Command08
[ - ] Extended_Command09
[ ENT ] Extended_Command10
The device support 10 extended command, Extended_Command01~Extended_Command10, and

the name can be modified by PCS-Explorer. The first three extend command is fixed in program,
so only Extended_Command04~Extended_Command10 are configurable, and configured as any
of seven function shortcuts key (“▲”, “▼”, “◄”, “►”, “＋”, “－” and “ENT”).

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Password:
000
Under the interface of function shortcuts key, press a shortcuts key to excute corresponding
operation. If the attribute of the extend command is set as “1”, the corresponding operation can not
excute unless input correct password. The extend command excuted by shortcuts key outputs a
pulse signal with 500ms, and for the operation requiring latching signal, the device provides
“T_FF” and “RS_FF” to fulfill the application, which can be configured by PCS-Explorer.
8.4.3 Normal Display

After the device is powered and entered into the initiating interface, it takes tens of seconds to
complete the initialization of the device. During the initialization of the device, the “HEALTHY”
indicator lamp of the device goes out.
The device can display single line diagram (SLD) and primary operation information, it can support
wiring configuration function. LCD configuration file can be downloaded via the network. Remote
control operation through single line diagram is also supported.
Under normal condition, LCD will display the following interface. LCD adopts white color as its
backlight that is activated if once there is any keyboard operation, moreover, the backlight will be
extinguished automatically if no keyboard operation is detected for a duration.

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S Addr:150 2008-11-28 10:10:00 Group 01
001.52A
Ida: 0.001Ie
5001 Three-phase
Idb: 0.001Ie differential current
Direction of power Idc: 0.001Ie
flow 3I0dH: 0.01In
3I0dM: 0.01In
Residual
differential current
3I0dL: 0.01In
Single line diagram 2001
of transformer 001.02A f: 50.00Hz system frequency
U/f: 1.000 overexcitation multiple
UH: 057.70V
000.22A mean voltage values
UM: 057.70V of each side
mean current values 3502
of each side 000.21A UL: 057.70V
3501
Circuit breaker
names of each side
The content displayed on the screen contains: the current date and time of the device (with a
format of yyyy-mm-dd hh:mm:ss:), the active setting group number, three-phase current sampling
value, residual current sampling value, three-phase voltage sampling value, residual voltage
sampling value, the synchronism voltage sampling value, line frequency and the address relevant
to IP address of Ethernet A. If all the sampling values of the voltage and the current can’t be fully
displayed within one screen, they will be scrolling-displayed automatically from the top to the
bottom.
If IP address of Ethernet A is “xxx.xxx.a.b”, the displayed address equals to (a×256+b). For

example, If IP address of Ethernet A is “198.087.000.150”, the displayed address will be “0×
256+150=150”.
If the device has detected any abnormal state, it′ll display the self-check alarm information.
“S” indicates that device clock is synchronized. If “S” disappears, it means that device clock is not
synchronized.
breaker open
breaker closed
8.4.4 Display Disturbance Records

This device can store up to 32 groups of disturbance records with fault waveform. Each group
consists of disturbance records of operation elements and corresponding fault detector elements.
Up to 1024 disturbance records can be stored in this device. If there is protection element
operation, LCD will automatically display the latest group of disturbance records, and two kinds of
LCD display interfaces will be available depending on whether there are supervision events or not.
For the situation that the disturbance records and the supervision events coexist, the upper half
part is the disturbance record, and the lower half part is the supervision event. The following items
are listed in the upper half part: record No., record name, generation time of the disturbance

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record. If there is protection element operation, faulty phase and relative operation time (with
reference to the corresponding fault detector element) will be displayed. If the disturbance records
can not be displayed in one page, they will be displayed in several pages alternately.
If there is no supervision event, disturbance records will be displayed as shown in the following
figure.
NO.001 2013-01-15 13:22:23:669 Disturb
0000ms TrigDFR_Man
0024ms A 87T.Op_Biased
If the device has the supervision event, the display interface will show the disturbance record and
the supervision event at the same time.
NO.001 2013-01-15 13:22:23:669 Disturb
0000ms TrigDFR_Man
0024ms A 87T.Op_Biased
Superv Events
Alm_Device
NO.001 shows the SOE No. of the disturbance record.
2013-01-15 13:22:23:669 shows the time of the disturbance record, the format is

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“yyyy-mm-dd hh:mm:ss:fff”.
Disturb shows the title of the disturbance record.
0000ms TrigDFR.Man shows fault detector element and its operation time (set as
“0000ms” fixedly).
0024ms A 87T.Op_Biased shows operation element and its relative operation time (with
reference to the corresponding fault detector element).
All the protection elements have been listed in chapter “Operation Theory”, and please refer to
each protection element for details. The reports related to oscillography function are showed in the
following table.
Table 8.4-1 Tripping report messages
No. Message Description

1 TrigDFR Fault detector operates to trigger oscillography function.
2 TrigDFR_Man Oscillography function is triggered manually.
3 TrigDFR_Rmt Oscillography function is triggered remotely.
Oscillography function is triggered by binary input [BI_TrigDFR]. The
4 TrigDFR_BI binary input [BI_TrigDFR] is configurable, and it can be designated to
internal signal or external input.
Oscillography function is triggered by alarm signals of protection DSP
5 ProtBrd.TrigDFR_Alm
module.
Oscillography function is triggered by failure signals of protection DSP
6 ProtBrd.TrigDFR_Fail
module.
Oscillography function is triggered by alarm signals of fault detector
7 FDBrd.TrigDFR_Alm
DSP module.
Oscillography function is triggered by failure signals of fault detector
8 FDBrd.TrigDFR_Fail
DSP module.
8.4.5 Display Supervision Event

This device can store 1024 pieces of supervision events. During the running of the device, the
supervision event of hardware self-check errors or system running abnormity will be displayed
immediately.

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S Superv Events
Alm_Device
Alm_Version
S indicates that device clock is synchronized. If “S” disappears, it

means that device clock is not synchronized.
Superv Events shows the title of the supervision events.
Alm_Device shows the contents of supervision events.
Alm_Version
8.4.6 Display IO Events

This device can store 1024 pieces of binary events. During the running of the device, the binary
input will be displayed once its state has changed, i.e. from “0” to “1” or from “1” to “0”.
NO.001 2013-01-15 13:31:23:669 IO Chg
BI_Maintenance 0 1

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NO.001 shows the No. of the binary event.
2013-01-15 13:31:23:669 shows date and time when the report occurred, the format is
“yyyy-mm-dd hh:mm:ss:fff”.
IO Chg shows the title of the binary event.
BI_Maintenance 0→1 shows the state change of binary input, including binary input
name, original state and final state.
8.4.7 Display Device Logs

This device can store 1024 pieces of device logs. Please refer to section “8.5.3” for LCD operation
4. Device Logs NO.4

2008-11-28 10:18:47:569ms
Reboot
Device Logs NO. 4 shows the title and the number of the device log
2008-11-28 10:18:47:569 shows date and time when the report occurred, the format is
year–month-date and hour:minute:second:millisecond
Reboot shows the manipulation content of the device log
User operating information listed below may be displayed.
Table 8.4-2 User operating event list
No. Message Description

1 Reboot The device has been reboot.
2 Settings_Chgd The device′s settings have been changed.
3 ActiveGrp_Chgd Active setting group has been changed.
4 Report_Cleared All reports have been deleted. (Device logs can not be deleted)
5 Waveform_Cleared All waveforms have been deleted.
6 Process_Exit A process has exited.
7 Counter_Cleared Clear counter
It will be displayed on LCD before disturbance records and supervision events are confirmed. Only

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pressing both “ENT” and “ESC” at the same time can switch among disturbance records,
supervision events and the normal running state of the device to display it. IO events will be
displayed for 5s and then it will return to the previous display interface automatically.
8.5 Keypad Operation

8.5.1 View Device Measurements
1. Press the “▲” to enter the main menu;
2. Press the “▲” or “▼” to move the cursor to the “Measurements” menu, and then press
the “ENT” or “►” to enter the menu;
3. Press the “▲” or “▼” to move the cursor to any command menu, and then press the
“ENT” to enter the menu;
4. Press the “▲” or “▼” to page up/down (if all information cannot be displayed in one
display screen, one screen can display 14 lines of information at most);
5. Press the “◄” or “►” to select pervious or next command menu;
6. Press the “ENT” or “ESC” to exit this menu (returning to the “Measurements” menu);
8.5.2 View Device Status

1. Press the key “▲” to enter the main menu.
2. Press the key “▲” or “▼” to move the cursor to the “Status” menu, and then press the
“ENT” or “►” to enter the menu.
3. Press the key “▲” or “▼” to move the cursor to any command menu item, and then press
the key “ENT” to enter the submenu.
4. Press the “▲” or “▼” to page up/down (if all information cannot be displayed in one
display screen, one screen can display 14 lines of information at most).
5. Press the key “◄” or “►” to select pervious or next command menu.
6. Press the key “ENT” or “ESC” to exit this menu (returning to the “Status” menu).
8.5.3 View Device Records

2. Press the “▲” or “▼” to move the cursor to the “Records” menu, and then press the
“ENT” or “►” to enter the menu;

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4. Press the “▲” or “▼” to page up/down;
5. Press the “＋” or “－” to select pervious or next record;
7. Press the “ENT” or “ESC” to exit this menu (returning to the “Records” menu);
8.5.4 Print Device Records

2. Press the “▲” or “▼” to move the cursor to the “Print” menu, and then press the “ENT” or
“►” to enter the menu;
 Selecting the “Disturb Records”, and then press the “＋” or “－” to select pervious
or next record. After pressing the key “ENT”, the LCD will display “Start Printing... ”,
and then automatically exit this menu (returning to the menu “Print”). If the printer
doesn’t complete its current print task and re-start it for printing, and the LCD will
display “Printer Busy…”. Press the key “ESC” to exit this menu (returning to the
menu “Print”).
 Selecting the command menu “Superv Events” or “IO Events”, and then press the
key “▲” or “▼” to move the cursor. Press the “＋” or “－” to select the starting and
ending numbers of printing message. After pressing the key “ENT”, the LCD will
display “Start Printing…”, and then automatically exit this menu (returning to the
menu “Print”). Press the key “ESC” to exit this menu (returning to the menu “Print”).
4. If selecting the command menu “Device Info”, “Device Status“ or “IEC103 Info”, press
the key “ENT”, the LCD will display “Start printing..”, and then automatically exit this menu
(returning to the menu “Print”).
5. If selecting the “Settings”, press the key “ENT” or “►” to enter the next level of menu.
6. After entering the submenu “Settings”, press the key “▲” or “▼” to move the cursor, and
then press the key “ENT” to print the corresponding default value. If selecting any item to
printing:
Press the key “＋” or “－” to select the setting group to be printed. After pressing the key
“ENT”, the LCD will display “Start Printing…”, and then automatically exit this menu
(returning to the menu “Settings”). Press the key “ESC” to exit this menu (returning to the
menu “Settings”).
7. After entering the submenu “Waveforms”, press the “＋” or “－” to select the waveform
item to be printed and press ”ENT” to enter. If there is no any waveform data, the LCD will
display “No Waveform Data!” (Before executing the command menu “Waveforms”, it is
necessary to execute the command menu “Trig Oscillograph” in the menu “Local Cmd”,

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otherwise the LCD will display “No Waveform Data!”). With waveform data existing:
Press the key “＋” or “－” to select pervious or next record. After pressing the key “ENT”, the LCD
will display “Start Printing…”, and then automatically exit this menu (returning to the menu
“Waveforms”). If the printer does not complete its current print task and re-start it for printing, and
the LCD will display “Printer Busy…”. Press the key “ESC” to exit this menu (returning to the menu
“Waveforms”).
8.5.5 View Device Setting

2. Press the “▲” or “▼” to move the cursor to the “Settings” menu, and then press the
4. Press the “▲” or “▼” to move the cursor;
5. Press the “+” or “-” to page up/down;
7. Press the “ESC” to exit this menu (returning to the menu “Settings”).
NOTICE!
If the displayed information exceeds 14 lines, the scroll bar will appear on the right side
of the LCD to indicate the quantity of all displayed information of the command menu
and the relative location of information where the current cursor points at.
8.5.6 Modify Device Setting

4. Press the “▲” or “▼” to move the cursor;
5. Press the “+” or “-” to page up/down;
7. Press the “ESC” to exit this menu (returning to the menu “Settings” );
8. If selecting the command menu “System Settings”, move the cursor to the setting item

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to be modified, and then press the “ENT”;
Press the “＋” or “－” to modify the value (if the modified value is of multi-bit, press the “◄” or “►”
to move the cursor to the digit bit, and then press the “＋” or “－” to modify the value), press the
“ESC” to cancel the modification and return to the displayed interface of the command menu
“System Settings”. Press the “ENT” to automatically exit this menu (returning to the displayed
interface of the command menu “System Settings”).
Move the cursor to continue modifying other setting items. After all setting values are modified,
press the “◄”, “►” or “ESC”, and the LCD will display “Save or Not?”. Directly press the “ESC” or
press the “◄” or “►” to move the cursor. Select the “Cancel”, and then press the “ENT” to
automatically exit this menu (returning to the displayed interface of the command menu “System
Settings”).
Press the “◄” or “►” to move the cursor. Select “No” and press the “ENT”, all modified setting item
will restore to its original value, exit this menu (returning to the menu “Settings”).
Press the “◄” or “►” to move the cursor to select “Yes”, and then press the “ENT”, the LCD will
display password input interface.
Password:
____
Input a 4-bit password (“＋”, “◄”, “▲” and “－”). If the password is incorrect, continue inputting it,
and then press the “ESC” to exit the password input interface and return to the displayed interface
of the command menu “System Settings”. If the password is correct, LCD will display “Save
Setting Now…”, and then exit this menu (returning to the displayed interface of the command
menu “System Settings”), with all modified setting items as modified values.
NOTICE!
For different setting items, their displayed interfaces are different but their modification
methods are the same. The following is ditto.
9. If selecting the submenu “Prot Settings”, and press “ENT” to enter. After selecting
different command menu, the LCD will display the following interface: (take “Diff Prot
Settings” as an example)

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Diff Prot Settings
Please Select Group for Config
Active Group: 01
Selected Group: 02
Press the “＋” or “－” to modify the value, and then press the “ENT” to enter it. Move the cursor to
the setting item to be modified, press the “ENT” to enter.
Take the setting [87.I_Biased] as an example is selected to modify, then press the “ENT” to enter
and the LCD will display the following interface. Press “＋” or “－” to modify the value and then
press the “ENT” to confirm.
87.I_Biased
Current Value 0.22
Modified Value 0.22
Min Value 0.05
Max Value 5.00
NOTICE!
After modifying protection settings in current active setting group or system parameters
of the device, the “HEALTHY” LED indicator the device will be lit off, and the MON
module will check the new settings. If the abnormality is detected during the setting
check, corresponding alarm signals will be issued. Moreover, if the critical error is
detected, the device will be blocked.

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8.5.7 Copy Device Setting

3. Press the “▲” or “▼” to move the cursor to the command menu “Copy Settings”, and
then press the “ENT” to enter the menu.
Copy Settings
Active Group: 01
Copy To Group: 02
Press the “＋” or “－” to modify the value. Press the “ESC”, and return to the menu “Settings”.
Press the “ENT”, the LCD will display the interface for password input, if the password is incorrect,
continue inputting it, press the “ESC” to exit the password input interface and return to the menu
“Settings”. If the password is correct, the LCD will display “Setting Copied!”, and exit this menu
(returning to the menu “Settings”).
8.5.8 Switch Setting Group

1. Exit the main menu;
2. Press the “GRP”

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Change Active Group
Active Group: 01
Change To Group: 02
Press the “＋” or “－” to modify the value, and then press the “ESC” to exit this menu (returning to
the main menu). After pressing the “ENT”, the LCD will display the password input interface. If the
password is incorrect, continue inputting it, and then press the “ESC” to exit the password input
interface and return to its original state. If the password is correct, the “HEALTHY” indicator lamp
of the protection device will go out, and the protection device will re-check the protection setting. If
the check doesn’t pass, the protection device will be blocked. If the check is successful, the LCD
will return to its original state.
NOTICE!
Users can switch the active setting group by binary input on BI plug-in module.
8.5.9 Delete Device Records

1. Exit the main menu;
2. Press the “＋”, “－”, “＋”, “－” and “ENT”; Press the “ESC” to exit this menu (returning to
the original state). Press the “ENT” to carry out the deletion.

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Press <ENT> To Clear

Press <ESC> To Exit
NOTICE!
The operation of deleting device message will delete all messages saved by the
protection device, including disturbance records, supervision events, binary events, but
not including device logs. Furthermore, the message is irrecoverable after deletion, so
the application of the function shall be cautious.
8.5.10 Remote Control via SLD

The control operation (close or open) also can be executed on the single line diagram (SLD) of the
default display under normal operation condition. The signs of the circuit breaker (abbreviated as
CB) and switch (DS or ES) are listed in the following table.
Table 8.5-1 Primary equipment symbols in SLD
Sign Explanation Sign Explanation
Position of CB: Open Position of switch: Open
Position of CB: Closed Position of switch: Closed
? Position of CB: Intermediate state ? Position of switch: Intermediate state
× Position of CB: Bad state × Position of switch: Bad state
An example of normal display with SLD is shown in the following figure. The single line diagram of
the default display on the LCD is shown as below when the device is in normal situation, if this
device adopts the single line diagram as default display.

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S Addr:150 2008-11-28 10:10:00 Group 01
Bus1
Bus2
M011 M0112
M0131
M01
M0151
M0171
Press key “▼” continuously to select a circuit breaker or a switch which will be opened or closed.
Then press key “ENT” to start to control the selected circuit breaker or switch. If it is the first time to
do control operation after a long time, it needs to input a correct password. The control operation
window will be valid for 150s after inputting correct password. The password for control operation
is fixed, and it is “111”.
S Addr:150 2008-11-28 10:10:00 Group 01
Bus1
Bus2
M011 M0112
M0131
M01
M0151
M0171 Password：
000
After inputting correct password, press key “ENT” to control the selected circuit breaker or switch.
Press key “▼” continuously to select the expected circuit breaker or switch with closed position,
and then press key “ENT” to start to open the selected circuit breaker or switch.

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S Addr:150 2008-11-28 10:10:00 Group 01
Bus1
Bus2
M011 M0112
M0131
M01
M0151
M0171
Open Close?
If control operation is succeed, the following figure will be shown.
S Addr:150 2008-11-28 10:10:00 Group 01
Bus1
Bus2
M011 M0112
M0131
M01
M0151
M0171
Op Success
8.5.11 Modify Device Clock

2. Press the “▲” or “▼” to move the cursor to the “Clock” menu, and then press the “ENT”
to enter clock display
3. Press the “▲” or “▼” to move the cursor to the date or time to be modified;
4. Press the “+” or “-” to modify value, and then press the “ENT” to save the modification
and return to the main menu;
5. Press the “ESC” to cancel the modification and return to the main menu.

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Clock
Year: 2008
Month: 11
Day: 28
Hour: 20
Minute: 59
Second: 14
8.5.12 View Module Information

2. Press the “▲” or “▼” to move the cursor to the “Information” menu, and then press the
3. Press the “▲” or “▼” to move the cursor to the command menu “Board Info”, and then
press the “ENT” to enter the menu;
4. Press the “▲” or “▼” to move the scroll bar;
5. Press the “ENT” or “ESC” to exit this menu (returning to the “Information” menu).
8.5.13 Check Software Version

1. Press the “▲” to enter the main menu.
2. Press the “▲” or “▼” to move the cursor to the “Information” menu, and then press the
“ENT” to enter the submenu.
3. Press the key “▲” or “▼” to move the cursor to the command menu “Version Info”, and
then press the key “ENT” to display the software version.
4. Press the “ESC” to return to the main menu.
8.5.14 Communication Test

2. Press the key “▲” or “▼” to move the cursor to the “Test” menu, and then press the key
“ENT” or “►” to enter the menu.

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3. Press the key “▲” or “▼” to move the cursor to the submenu “Device Test”, and then
press the key “ENT” to enter the submenu,to select test item. If “Disturb Events”
“Superv Events” or “IO Events” is selected, two options “All Test” and “Select Test” are
provided.
4. Press the key “▲” or “▼” to move the cursor to select the corresponding command menu
“All Test” or “Select Test”. If selecting the “All Test”, press the “ENT”, and the device will
successively carry out all operation element message test one by one.
5. If “Select Test” is selected, press the key “ENT”. Press the “＋” or “－” to page up/down,
and then press the key “▲” or “▼” to move the scroll bar. Move the cursor to select the
corresponding protection element. Press the key “ENT” to execute the communication
test of this protection element, the substation automatic system (SAS) will receive the
corresponding message.
NOTICE!
If no input operation is carried out within 60s, exit the communication transmission and
return to the “Test” menu, at this moment, the LCD will display “Communication Test
Timeout and Exiting...”.
Press the key “ESC” to exit this menu (returning to the menu “Test”, at this moment, the LCD will
display “Communication Test Exiting…”.
8.5.15 Select Language

2. Press the key “▲” or “▼” to move the cursor to the command menu “Language”, and
then press the key “ENT” to enter the menu and the following display will be shown on
LCD.
Please Select Language:
1 中文
2 English
3. Press the key “▲” or “▼” to move the cursor to the language user preferred and press

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the key “ENT” to execute language switching. After language switching is finished, LCD
will return to the menu “Language”, and the display language is changed. Otherwise,
press the key “ESC” to cancel language switching and return to the menu “Language”.
NOTICE!
LCD interface provided in this chapter is only a reference and available for explaining
specific definition of LCD. The displayed interface of the actual device may be some
different from it, so you shall be subject to the actual protection device.

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Table of Contents
9 Configurable Function ...................................................................... 9-a
9.1 Overview .......................................................................................................... 9-1
9.2 Introduction on PCS-Explorer Software ........................................................ 9-1
9.3 Signal List ........................................................................................................ 9-2
9.3.1 Input Signals ......................................................................................................................... 9-2
9.3.2 Output Signals .................................................................................................................... 9-10
9.3.3 Intermediate Signals .......................................................................................................... 9-17
9.4 Configurable LED Indicators ........................................................................ 9-18

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9.1 Overview
By adoption of PCS-Explorer software, it is able to make device configuration, function

configuration, LCD configuration, binary input and binary output configuration, LED indicator
configuration and programming logic for PCS-978.
9.2 Introduction on PCS-Explorer Software
PCS-Explorer software is developed in order to meet customer’s demand on functions of UAPC

platform device such as device configuration and programmable design. It selects substation as
the core of data management and the device as fundamental unit, supporting one substation to
govern many devices. The software provides on-line and off-line functions: on-line mode: Ethernet
connected with the device supporting IEC60870-5-103 and capable of uploading and downloading
configuration files through Ethernet net; off-line mode: off-line setting configuration. In addition, it
also supports programmable logic to meet customer’s demand.
After function configuration is finished, disabled protection function will be hidden in the device and
in setting configuration list of PCS-Explorer Software. The user can select to show or hide some
setting by this way, and modify the setting value.
Please refer to the instruction manual “PCS-Explorer Auxiliary Software” for details.
Overall functions:
 Programmable logic
 Device configuration
 Function configuration
 LCD configuration
 LED indicators configuration
 Binary signals configuration
 Setting configuration
 Real-time display of analogue and digital quantity of device
 Display of sequence of report (SOE)
 Analysis of waveform
 File downloading/uploading
 LCD function shortcut keys configuration
 DNP communication information map configuration
 Multi-user access authority management

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9.3 Signal List
If an input signal or output signal is gray in PCS-Explorer, it means that the input signal or output
signal is not configurable. Otherwise, it is configurable signal.
NOTICE!
9.3.1 Input Signals

All input signals of this device are listed in the following table.
9.3.1.1 Three-phase Current ELement

1 x.ia Sampled value of phase-A current at x side of transformer
2 x.ib Sampled value of phase-B current at x side of transformer
3 x.ic Sampled value of phase-C current at x side of transformer
The enabling input of CT circuit abnormality alarm, it is triggered from binary
4 x.CTS.En_Alm
9.3.1.2 Three-phase Voltage ELement

1 x.ua Sampled value of phase-A voltage at x side of transformer
2 x.ub Sampled value of phase-B voltage at x side of transformer
3 x.uc Sampled value of phase-C voltage at x side of transformer
Binary input of normally closed auxiliary contact of a circuit breaker at x side of
4 x.52b
transformer
5 x.In_VT Input signal of indicating VT in service at x side of transformer
9.3.1.3 Residual Current Element

1 x.3i0 Measured residual current at x side of transformer
9.3.1.4 Residual Voltage Element

1 x.3u0 Measured residual voltage at x side of transformer
9.3.1.5 Transformer Current Differential Protection


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Input signal 1 of enabling transformer current differential protection. It is
7 87T.En1
Input signal 2 of enabling transformer current differential protection. It is
8 87T.En2
Input signal of blocking transformer current differential protection. It is triggered
9 87T.Blk
9.3.1.6 Reactor Current Differential Protection

Input signal 1 of enabling reactor differential protection. It is triggered from
3 87R.En1
Input signal 2 of enabling reactor differential protection. It is triggered from
4 87R.En2
Input signal of blocking reactor differential protection. It is triggered from binary
5 87R.Blk
9.3.1.7 Restricted Earth Fault Protection

Three-phase current data input 1 for restricted earth fault protection at side x of
1 x.64REF.I3P1
of transformer.
2 x.64REF.I3P2
of transformer.
3 x.64REF.I3P3
of transformer.
4 x.64REF.I3P4
of transformer.
Residual current data input for restricted earth fault protection at side x of of
5 x.64REF.I1P
transformer.
Input signal 1 of enabling restricted earth fault protection at side x of of
6 x.64REF.En1
transformer. It is triggered from binary input or programmable logic etc.
Input signal 2 of enabling restricted earth fault protection at side x of of
7 x.64REF.En2
Input signal of blocking restricted earth fault protection at side x of of
8 x.64REF.Blk

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9.3.1.8 Winding Differential Protection

Input signal 1 of enabling winding differential protection. It is triggered from
6 87W.En1
Input signal 2 of enabling winding differential protection. It is triggered from
7 87W.En2
Input signal of blocking winding differential protection. It is triggered from binary
8 87W.Blk
9.3.1.9 Inter-turn Fault Protection

1 21IT.I3P Three-phase current data input for inter-turn fault protection.
2 21IT.U3P Three-phase voltage data input for inter-turn fault protection.
Input signal 1 of enabling inter-turn fault protection. It is triggered from binary
3 21IT.En1
Input signal 2 of enabling inter-turn fault protection. It is triggered from binary
4 21IT.En2
Input signal of blocking inter-turn fault protection. It is triggered from binary
5 21IT.Blk
9.3.1.10 Overexcitation Protection

Measurement data (including frequency and voltage) required by stage n of
1 24DTn.OvExc
definite-time overexcitation protection. (n=1, 2)
2 24DTn.En1
3 24DTn.En2
Input signal of blocking stage n of definite-time overexcitation protection. It is
4 24DTn.Blk
Measurement data (including frequency and voltage) required by inverse-time
5 24IDMT.OvExc
overexcitation protection.
Input signal 1 of enabling inverse-time overexcitation protection. It is triggered
6 24IDMT.En1
Input signal 2 of enabling inverse-time overexcitation protection. It is triggered
7 24IDMT.En2
Input signal of blocking inverse-time overexcitation protection. It is triggered
8 24IDMT.Blk

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9.3.1.11 Frequency Protection

1 81O.U3P Three-phase voltage data input for overfrequency protection.
2 81O.Freq Measured frequency data input for overfrequency protection.
Input signal 1 of enabling overfrequency protection. It is triggered from binary
3 81O.En1
Input signal 2 of enabling overfrequency protection. It is triggered from binary
4 81O.En2
Input signal of blocking overfrequency protection. It is triggered from binary
5 81O.Blk
6 81U.U3P Three-phase voltage data input for underfrequency protection.
7 81U.Freq Measured frequency data input for underfrequency protection.
8 81U.En1
9 81U.En2
Input signal of blocking underfrequency protection. It is triggered from binary
10 81U.Blk
9.3.1.12 Impedance Protection

Three-phase current data input for impedance protection at side x of
1 x.21.I3P
transformer.
Three-phase voltage data input for impedance protection at side x of
2 x.21.U3P
transformer.
3 x.21.En1
4 x.21.En2
Input signal of blocking impedance protection at side x of transformer. It is
5 x.21.Blk
9.3.1.13 Phase Overcurrent Protection

Three-phase current data input for stage n of phase overcurrent protection at
1 x.50/51Pn.I3P
side x of transformer or reactor. (n=1, 2, 3, 4)
Three-phase voltage data input for stage n of phase overcurrent protection at
2 x.50/51Pn.U3P
side x of transformer or reactor. (n=1, 2, 3, 4)
3 x.50/51Pn.En1 transformer or reactor. It is triggered from binary input or programmable logic
etc. (n=1, 2, 3, 4)
4 x.50/51Pn.En2
transformer or reactor. It is triggered from binary input or programmable logic

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etc. (n=1, 2, 3, 4)
Input signal of blocking stage n of phase overcurrent protection at side x of
5 x.50/51Pn.Blk transformer or reactor. It is triggered from binary input or programmable logic
etc. (n=1, 2, 3, 4)
9.3.1.14 Earth Fault Protection

Three-phase voltage data input for stage n of earth fault protection at side x of
1 x.50/51Gn.U3P
Three-phase current data input for stage n of earth fault protection at side x of
2 x.50/51Gn.I3P
Measured neutral current data input for stage n of earth fault protection at side x
3 x.50/51Gn.I1P
of transformer or reactor. (n=1, 2, 3, 4)
Input signal 1 of enabling stage n of earth fault protection at side x of
4 x.50/51Gn.En1 transformer or reactor. It is triggered from binary input or programmable logic
etc. (n=1, 2, 3, 4)
Input signal 2 of enabling stage n of earth fault protection at side x of
5 x.50/51Gn.En2 transformer or reactor. It is triggered from binary input or programmable logic
etc. (n=1, 2, 3, 4)
Input signal of blocking stage n of earth fault protection at side x of transformer
6 x.50/51Gn.Blk or reactor. It is triggered from binary input or programmable logic etc. (n=1, 2, 3,
4)
9.3.1.15 Negative-Sequence Overcurrent Protection

Three-phase current data input for stage n of negative-sequence overcurrent
1 x.50/51Qn.I3P
Input signal 1 of enabling stage n of negative-sequence overcurrent protection
2 x.50/51Qn.En1 at side x of transformer. It is triggered from binary input or programmable logic
etc. (n=1, 2)
Input signal 2 of enabling stage n of negative-sequence overcurrent protection
3 x.50/51Qn.En2 at side x of transformer. It is triggered from binary input or programmable logic
etc. (n=1, 2)
Input signal of blocking stage n of negative-sequence overcurrent protection at
4 x.50/51Qn.Blk side x of transformer. It is triggered from binary input or programmable logic etc.
(n=1, 2)
9.3.1.16 Phase Overvoltage Protection

Three-phase voltage data input for stage n of phase overvoltage protection at
1 x.59Pn.U3P
2 x.59Pn.En1

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3 x.59Pn.En2
Input signal of blocking stage n of phase overvoltage protection at side x of
4 x.59Pn.Blk
9.3.1.17 Residual Overvoltage Protection

Three-phase voltage data input for stage n of residual overvoltage protection at
1 x.59Gn.U3P
Measured residual voltage data input for stage n of residual overvoltage
2 x.59Gn.U1P
3 x.59Gn.En1
4 x.59Gn.En2
Input signal of blocking stage n of residual overvoltage protection at side x of
5 x.59Gn.Blk
9.3.1.18 Undervoltage Protection

Three-phase voltage data input for undervoltage protection at side x of
1 x.27P.U3P
transformer.
2 x.27P.En1
3 x.27P.En2
Input signal of blocking undervoltage protection at side x of transformer. It is
4 x.27P.Blk
9.3.1.19 Thermal Overload Protection

Three-phase current data input for thermal overload protection at side x of
1 x.49.I3P
transformer or reactor.
Clear command of thermal accumulation value for thermal overload protection
2 x.49.Clr
at side x of transformer or reactor.
3 x.49.En1
4 x.49.En2
Input signal of blocking thermal overload protection at side x of transformer or
5 x.49.Blk

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9.3.1.20 Breaker Failure Protection

Three-phase current data input for breaker failure protection at side x of
1 x.50BF.I3P
transformer.
2 x.50BF.Init Input signal of initiating breaker failure protection at side x of transformer.
Input signal of normally open auxiliary contact of circuit breaker at side x of
3 x.52b
transformer.
4 x.50BF.En1
5 x.50BF.En2
Input signal of blocking breaker failure protection at side x of transformer. It is
6 x.50BF.Blk
9.3.1.21 Pole Disagreement Protection

Three-phase current data input for pole disagreement protection at side x of
1 x.62PD.I3P
transformer.
2 x.62PD.In_PD_CB Input signal of indicating pole disagreement state at side x of transformer..
Input signal 1 of enabling pole disagreement protection at side x of transformer.
3 x.62PD.En1
Input signal 2 of enabling pole disagreement protection at side x of transformer.
4 x.62PD.En2
Input signal of blocking pole disagreement protection at side x of transformer. It
5 x.62PD.Blk
9.3.1.22 Phase Overcurrent Alarm

Three-phase current data input for stage n of phase overcurrent alarm at side x
1 x.51PAlmn.I3P
of transformer. (n=1, 2)
2 x.51PAlmn.En1
3 x.51PAlmn.En2
Input signal of blocking stage n of phase overcurrent alarm at side x of
4 x.51PAlmn.Blk
9.3.1.23 Residual Overvoltage Alarm

Three-phase voltage data input for residual overvoltage alarm at side x of
1 x.59GAlm.U3P
transformer.
Measured residual voltage data input for residual overvoltage alarm at side x of
2 x.59GAlm.U1P
transformer.

Date: 2016-06-22

Input signal 1 of enabling residual overvoltage alarm at side x of transformer. It
3 x.59GAlm.En1
Input signal 2 of enabling residual overvoltage alarm at side x of transformer. It
4 x.59GAlm.En2
Input signal of blocking residual overvoltage alarm at side x of transformer. It is
5 x.59GAlm.Blk
9.3.1.24 Mechanical Protection

Input signal 1 of enabling mechanical protection. It is triggered from binary input
5 MR.En1
Input signal 2 of enabling mechanical protection. It is triggered from binary input
6 MR.En2
Input signal of blocking mechanical protection. It is triggered from binary input
7 MR.Blk
9.3.1.25 Temperature Protection

1 26.Input_PhA DC input signal of phase A from external transducer.
2 26.Input_PhB DC input signal of phase B from external transducer.
3 26.Input_PhC DC input signal of phase C from external transducer.
Input signal 1 of enabling temperature protection. It is triggered from binary
4 26.En1
Input signal 2 of enabling temperature protection. It is triggered from binary
5 26.En2
Input signal of blocking temperature protection. It is triggered from binary input
6 26.Blk
9.3.1.26 Output Map


Date: 2016-06-22

9.3.2 Output Signals
All output signals of this device are listed in the following table.
9.3.2.1 Three-phase Current ELement

1 x.I3P Three-phase currents at x side of transformer
2 x.Ang(Ia) Phase angle of phase-A current at x side of transformer
3 x.Ang(Ib) Phase angle of phase-B current at x side of transformer
4 x.Ang(Ic) Phase angle of phase-C current at x side of transformer
5 x.Ang(3I0_Cal) Phase angle of calculated residual current at x side of transformer
6 x.AlmL_CTS CT secondary circuit abnormality at x side of transformer
7 x.AlmH_CTS CT secondary circuit failure at x side of transformer
9.3.2.2 Three-phase Voltage ELement

2 x.Ang(Ua) Phase angle of phase-A voltage at x side of transformer
3 x.Ang(Ub) Phase angle of phase-B voltage at x side of transformer
4 x.Ang(Uc) Phase angle of phase-C voltage at x side of transformer
5 x.Ang(3U0_Cal) Phase angle of calculated residual voltage at x side of transformer
6 x.Alm_VTS VT secondary circuit abnormality at x side of transformer
9.3.2.3 Residual Current Element

1 x.I1P A current data set at x side of transformer
2 x.Ang(3I0_Ext) Phase angle of measured residual current at x side of transformer
9.3.2.4 Residual Voltage Element

2 x.Ang(3U0_Ext) Phase angle of measured residual voltage at x side of transformer
9.3.2.5 Transformer Current Differential Protection

1 87T.St Transformer differential protection starts.
Instantaneous differential element of transformer differential protection is
2 87T.On_Inst
enabled.
3 87T.On_Biased Biased differential element of transformer differential protection is enabled.

Date: 2016-06-22

4 87T.On_DPFC DPFC differential element of transformer differential protection is enabled.
Instantaneous differential element of transformer differential protection
5 87T.Op_Inst
operates.
6 87T.Op_Biased Biased differential element of transformer differential protection operates.
7 87T.Op_DPFC DPFC differential element of transformer differential protection operates.
8 87T.Op Transformer differential protection operates.
10 87T.Alm_CTS CT secondary circuit of transformer differential protection is abnormal.
Instantaneous differential element of transformer differential protection picks up
11 87T.TrigDFR_Inst
to trigger DFR function.
Biased differential element of transformer differential protection picks up to
12 87T.TrigDFR_Biased
DPFC differential element of transformer differential protection picks up to
13 87T.TrigDFR_DPFC
9.3.2.6 Reactor Current Differential Protection

1 87R.St Reactor differential protection starts.
2 87R Op_Inst Instantaneous differential element of reactor differential protection operates.
3 87R Op_InstREF
4 87R Op_Biased Biased differential element of reactor differential protection operates.
5 87R Op_DPFC DPFC differential element of reactor differential protection operates.
6 87R Op_REF Zero-sequence differential element of reactor differential protection operates.
7 87R.Op Reactor differential protection operates.
8 87R On_Inst Instantaneous differential element of reactor differential protection is enabled.
9 87R On_InstREF
protection is enabled.
10 87R On_Biased Biased differential element of reactor differential protection is enabled.
11 87R On_DPFC DPFC differential element of reactor differential protection is enabled.
12 87R On_REF Zero-sequence differential element of reactor differential protection is enabled.
Instantaneous differential element reactor differential protection picks up to
15 87R.TrigDFR_Inst
Biased differential element of reactor differential protection picks up to trigger
16 87R.TrigDFR_Biased
DFR function.
DPFC differential element of reactor differential protection picks up to trigger
17 87R.TrigDFR_DPFC
DFR function.

Date: 2016-06-22
9.3.2.7 Restricted Earth Fault Protection

1 x.64REF.St Restricted earth-fault protection at side x of transformer starts.
2 x.64REF.On Restricted earth-fault protection at side x of transformer is enabled.
3 x.64REF.Op Restricted earth-fault protection at side x of transformer operates.
Differential current of restricted earth-fault protection at side x of transformer is
4 x.64REF.Alm_Diff
abnormal.
CT secondary circuit of restricted earth-fault protection at side x of transformer
5 x.64REF.Alm_CTS
is abnormal.
Restricted earth-fault protection at side x of transformer picks up to trigger DFR
6 x.64REF.TrigDFR
function.
9.3.2.8 Winding Differential Protection

1 87W.St Winding differential protection starts.
2 87W.On_PhSeg Phase-segregated winding differential protection is enabled.
3 87W.On_REF Restricted earth-fault element of winding differential protection is enabled.
4 87W.Op_PhSeg Phase-segregated winding differential protection operates.
5 87W.Op_REF Restricted earth-fault element of winding differential protection operates.
8 87W.TrigDFR Winding differential protection picks up to trigger DFR function.
9.3.2.9 Inter-turn Fault Protection

1 21IT.St Inter-turn fault protection starts.
2 21IT.On Inter-turn fault protection is enabled.
3 21IT.Op Inter-turn fault protection operates.
4 21IT.TrigDFR Inter-turn fault protection picks up to trigger DFR function.
9.3.2.10 Overexcitation Protection

3 24DT1.Op Stage 1 of definite-time overexcitation protection operates to trip.
6 24DT2.Alm Stage 2 of definite-time overexcitation protection operates to alarm.
7 24IDMT.St Inverse-time overexcitation protection starts
8 24IDMT.On Inverse-time overexcitation protection is enabled.
9 24IDMT.Op Inverse-time overexcitation protection operates to trip.
10 24IDMT.Alm Inverse-time overexcitation protection operates to alarm.
11 24DT1.TrigDFR Stage 1 of definite-time overexcitation protection picks up to trigger DFR

Date: 2016-06-22

function.
Stage 2 of definite-time overexcitation protection picks up to trigger DFR
12 24DT2.TrigDFR
function.
13 24DTIDMT.TrigDFR Inverse-time overexcitation protection picks up to trigger DFR function.
9.3.2.11 Frequency Protection

1 81O.St Overfrequency protection starts.
10 81O.TrigDFR Overfrequency protection picks up to trigger DFR function.
11 81U.St Underfrequency protection starts.
20 81U.TrigDFR Underfrequency protection picks up to trigger DFR function.
9.3.2.12 Impedance Protection

1 x.21.St Impedance protection at side x of transformer starts.
Stage n of phase-to-phase impedance protection at side x of transformer is
2 x.21.ZPn.On
enabled. (n=1, 2)
Stage n of phase-to-ground impedance protection at side x of transformer is
3 x.21.ZGn.On
enabled. (n=1, 2)
Stage n of phase-to-phase impedance protection at side x of transformer
4 x.21.ZPn.Op
operates. (n=1, 2)
Stage n of phase-to-ground impedance protection at side x of transformer
5 x.21.ZGn.Op
operates. (n=1, 2)
Stage n of phase-to-phase impedance protection at side x of transformer picks
6 x.21.ZPn.TrigDFR
7 x.21.ZGn.TrigDFR Stage n of phase-to-ground impedance protection at side x of transformer picks

Date: 2016-06-22

9.3.2.13 Phase Overcurrent Protection

1 x.50/51Pn.St
starts. (n=1, 2, 3, 4)
Stage n of phase overcurrent protection at side x of transformer or reactor is
2 x.50/51Pn.On
enabled. (n=1, 2, 3, 4)
3 x.50/51Pn.Op
operates. (n=1, 2, 3, 4)
Stage n of phase overcurrent protection at side x of transformer or reactor picks
4 x.50/51Pn.TrigDFR
up to trigger DFR function. (n=1, 2, 3, 4)
9.3.2.14 Earth Fault Protection

Stage n of earth fault protection at side x of transformer or reactor starts. (n=1,
1 x.50/51Gn.St
2, 3, 4)
Stage n of earth fault protection at side x of transformer or reactor is enabled.
2 x.50/51Gn.On
(n=1, 2, 3, 4)
Stage n of earth fault protection at side x of transformer or reactor operates.
3 x.50/51Gn.Op
(n=1, 2, 3, 4)
Stage n of earth fault protection at side x of transformer or reactor picks up to
4 x.50/51Gn.TrigDFR
trigger DFR function. (n=1, 2, 3, 4)
9.3.2.15 Negative-Sequence Overcurrent Protection

1 x.50/51Qn.St
starts. (n=1, 2)
Stage n of negative-sequence overcurrent protection at side x of transformer is
2 x.50/51Qn.On
enabled. (n=1, 2)
3 x.50/51Qn.Op
operates. (n=1, 2)
4 x.50/51Qn.TrigDFR
picks up to trigger DFR function. (n=1, 2)
9.3.2.16 Phase Overvoltage Protection

1 x.59Pn.St Stage n of phase overvoltage protection at side x of transformer starts. (n=1, 2)
Stage n of phase overvoltage protection at side x of transformer is enabled.
2 x.59Pn.On
(n=1, 2)
Stage n of phase overvoltage protection at side x of transformer operates. (n=1,
3 x.59Pn.Op
2)

Date: 2016-06-22

Stage n of phase overvoltage protection at side x of transformer picks up to
4 x.59Pn.TrigDFR
9.3.2.17 Residual Overvoltage Protection

Stage 1 of residual overvoltage protection at side x of transformer starts. (n=1,
1 x.59Gn.St
2)
Stage 1 of residual overvoltage protection at side x of transformer is enabled.
2 x.59Gn.On
(n=1, 2)
Stage 1 of residual overvoltage protection at side x of transformer operates.
3 x.59Gn.Op
(n=1, 2)
Stage 1 of residual overvoltage protection at side x of transformer picks up to
4 x.59Gn.TrigDFR
9.3.2.18 Undervoltage Protection

1 x.27P.UVn.St Stage n of undervoltage protection at side x of transformer starts. (n=1, 2, 3, 4)
Stage n of undervoltage protection at side x of transformer is enabled. (n=1, 2,
2 x.27P.UVn.On
3, 4)
Stage n of undervoltage protection at side x of transformer operates. (n=1, 2, 3,
3 x.27P.UVn.Op
4)
4 x.27P.Alm_Unrecov The voltage at side x of transformer does not recover to normal level.
Stage n of undervoltage protection at side x of transformer picks up to trigger
5 x.27P.UVn.TrigDFR
DFR function. (n=1, 2, 3, 4)
9.3.2.19 Thermal Overload Protection

1 x.49.St Thermal overload protection at side x of transformer or reactor starts.
2 x.49.On Thermal overload protection at side x of transformer or reactor is enabled.
3 x.49.Op Thermal overload protection at side x of transformer or reactor operates to trip.
Thermal overload protection at side x of transformer or reactor operates to
4 x.49.Alm
alarm.
Thermal overload protection at side x of transformer or reactor picks up to
5 x.49.TrigDFR
The calculated temperature difference of phase-A between winding
6 x.49.T_Diff_A
temperature and oil temperature.
The calculated temperature difference of phase-B between winding
7 x.49.T_Diff_B
The calculated temperature difference of phase-C between winding
8 x.49.T_Diff_C

Date: 2016-06-22
9.3.2.20 Breaker Failure Protection

1 x.50BF.St Breaker failure protection at side x of transformer starts.
Breaker failure protection with the time delay 1 at side x of transformer is
2 x.50BF.On_t1
enabled.
Breaker failure protection with the time delay 2 at side x of transformer is
3 x.50BF.On_t2
enabled.
Breaker failure protection at side x of transformer operates with the time delay
4 x.50BF.Op_t1
1.
Breaker failure protection at side x of transformer operates with the time delay
5 x.50BF.Op_t2
2.
The duration of input signal of initiating breaker failure protection at side x of
6 x.50BF.Alm_Init
transformer is over 3s.
The current criterion of breaker failure protection at side x of transformer is
7 x.50BF.Alm_Curr
satisfied for over 3s.
Breaker failure protection at side x of transformer picks up to trigger DFR
8 x.50BF.TrigDFR
function.
9.3.2.21 Pole Disagreement Protection

1 x.62PD.St Pole disagreement protection at side x of transformer starts.
2 x.62PD.On Pole disagreement protection at side x of transformer is enabled.
3 x.62PD.Op Pole disagreement protection at side x of transformer operates to trip.
4 x.62PD.Alm Pole disagreement protection at side x of transformer operates to alarm.
Pole disagreement protection at side x of transformer picks up to trigger DFR
5 x.62PD.TrigDFR
function.
9.3.2.22 Phase Overcurrent Alarm

1 x.51PAlmn.St Stage n of phase overcurrent alarm at side x of transformer starts. (n=1, 2)
2 x.51PAlmn.On Stage n of phase overcurrent alarm at side x of transformer is enabled. (n=1, 2)
Stage n of phase overcurrent alarm at side x of transformer operates to alarm.
3 x.51PAlmn.Alm
(n=1, 2)
9.3.2.23 Residual Overvoltage Alarm

1 x.59GAlm.St Residual overvoltage alarm at side x of transformer starts.
2 x.59GAlm.On Residual overvoltage alarm at side x of transformer is enabled.
3 x.59GAlm.Alm Residual overvoltage alarm at side x of transformer operates to alarm.
9.3.2.24 Mechanical Protection


Date: 2016-06-22

9.3.2.25 Temperature Protection

1 26.T_PhA Calculated temperature of phase-A signal from external transducer.
2 26.T_PhB Calculated temperature of phase-B signal from external transducer.
3 26.T_PhC Calculated temperature of phase-C signal from external transducer.
4 26.St Temperature protection starts.
5 26.On Temperature protection is enabled.
6 26.Op Temperature protection operates to trip.
7 26.Alm Temperature protection operates to alarm.
8 26.TrigDFR Temperature protection picks up to trigger DFR function.
9.3.3 Intermediate Signals

The following signals provided by intermediate variable element are used to transfer signals by
programmable logic, so they are input signals and the corresponding output signals at the same
time.

1 Sig_Spare01 Signal of intermediate variable 1 for logic programming.

Date: 2016-06-22

9.4 Configurable LED Indicators

LED indicator No.1 is not configurable, and it always used to indicate the
1 HEALTHY
operation state of the device.
LED indicator No.2 is not configurable, and it always used to indicate the the
2 ALARM
abnormality alarm of the device.
Configurable LED indicator No.03
3 in3 It is configured as “TRIP” by default, and it is used to indicate the tripping of
the device
4 in4 Configurable LED indicator No.04

Date: 2016-06-22
10 Communication
10 Communication
Table of Contents
10 Communication .............................................................................................. 10-a
10.1 Overview ...................................................................................................... 10-1
10.2 Rear Communication Port Information ...................................................... 10-1
10.2.1 RS-485 Interface .............................................................................................................. 10-1
10.2.2 Ethernet Interface ............................................................................................................. 10-3
10.2.3 IEC60870-5-103 Communication..................................................................................... 10-4
10.2.4 DNP3.0 Communication................................................................................................... 10-4
10.3 IEC60870-5-103 Interface over Serial Port ................................................. 10-4

10.3.1 Physical Connection and Link Layer ................................................................................ 10-5
10.3.2 Initialization ....................................................................................................................... 10-5
10.3.3 Time Synchronization ....................................................................................................... 10-5
10.3.4 Spontaneous Events ........................................................................................................ 10-5
10.3.5 General Interrogation ....................................................................................................... 10-6
10.3.6 General Service................................................................................................................ 10-6
10.3.7 Disturbance Records ........................................................................................................ 10-6
10.4 Messages Description for IEC61850 Protocol........................................... 10-6

10.4.1 Overview .......................................................................................................................... 10-6
10.4.2 Communication Profiles ................................................................................................... 10-7
10.4.3 MMS Communication Network Deployment .................................................................... 10-8
10.4.4 Server Data Organization................................................................................................10-11
10.4.5 Server Features and Configuration ................................................................................ 10-14
10.4.6 ACSI Conformance ........................................................................................................ 10-16
10.4.7 Logical Nodes................................................................................................................. 10-20
10.5 DNP3.0 Interface ........................................................................................ 10-23

10.1.1 Overview ........................................................................................................................ 10-23
10.1.2 Link Layer Functions ...................................................................................................... 10-23

Date: 2015-06-30
10 Communication
10.1.3 Transport Functions ....................................................................................................... 10-23
10.1.4 Application Layer Functions ........................................................................................... 10-23
List of Figures
Figure 10.2-1 EIA RS-485 bus connection arrangements ..................................................... 10-2
Figure 10.2-2 Ethernet communication cable ........................................................................ 10-3
Figure 10.2-3 Ethernet communication structure .................................................................. 10-4
Figure 10.4-1 Dual-net full duplex mode sharing the RCB block instance ......................... 10-9
Figure 10.4-2 Dual-net hot-standby mode sharing the same RCB instance..................... 10-10
Figure 10.4-3 Dual-net full duplex mode with 2 independent RCB instances .................. 10-11

Date: 2015-06-30
10 Communication
10.1 Overview
This section outlines the remote communications interfaces of NR Relays. The protective device
supports a choice of three protocols via the rear communication interface (RS-485 or Ethernet),
selected via the model number by setting. The protocol provided by the protective device is
indicated in the menu “Settings→Device Setup→Comm Settings”.
The rear EIA RS-485 interface is isolated and is suitable for permanent connection of whichever
protocol is selected. The advantage of this type of connection is that up to 32 protective devices
can be “daisy chained” together using a simple twisted pair electrical connection.
It should be noted that the descriptions contained within this section do not aim to fully detail the
protocol itself. The relevant documentation for the protocol should be referred to for this
information. This section serves to describe the specific implementation of the protocol in the relay.
10.2 Rear Communication Port Information
10.2.1 RS-485 Interface
This protective device provides two rear RS-485 communication ports, and each port has three
terminals in the 12-terminal screw connector located on the back of the relay and each port has a
ground terminal for the earth shield of the communication cable. The rear ports provide RS-485
serial data communication and are intended for use with a permanently wired connection to a
remote control center.
10.2.1.1 EIA RS-485 Standardized Bus
The EIA RS-485 two-wire connection provides a half-duplex fully isolated serial connection to the
product. The connection is polarized and whilst the product’s connection diagrams indicate the
polarization of the connection terminals it should be borne in mind that there is no agreed
definition of which terminal is which. If the master is unable to communicate with the product, and
the communication parameters match, then it is possible that the two-wire connection is reversed.
10.2.1.2 Bus Termination
The EIA RS-485 bus must have 120Ω (Ohm) ½ Watt terminating resistors fitted at either end
across the signal wires (refer to Figure 10.2-1). Some devices may be able to provide the bus
terminating resistors by different connection or configuration arrangements, in which case
separate external components will not be required. However, this product does not provide such a
facility, so if it is located at the bus terminus then an external termination resistor will be required.

Date: 2015-06-30
10 Communication
EIA RS-485
Master 120 Ohm
120 Ohm
Slave Slave Slave
Figure 10.2-1 EIA RS-485 bus connection arrangements
10.2.1.3 Bus Connections & Topologies
The EIA RS-485 standard requires that each device is directly connected to the physical cable that
is the communications bus. Stubs and tees are expressly forbidden, such as star topologies. Loop
bus topologies are not part of the EIA RS-485 standard and are forbidden by it also.
Two-core screened cable is recommended. The specification of the cable will be dependent on the
application, although a multi-strand 0.5mm 2 per core is normally adequate. Total cable length must
not exceed 500m. The screen must be continuous and connected to ground at one end, normally
at the master connection point; it is important to avoid circulating currents, especially when the
cable runs between buildings, for both safety and noise reasons.
This product does not provide a signal ground connection. If a signal ground connection is present
in the bus cable then it must be ignored, although it must have continuity for the benefit of other
devices connected to the bus. At no stage must the signal ground be connected to the cables
screen or to the product’s chassis. This is for both safety and noise reasons.
10.2.1.4 Biasing
It may also be necessary to bias the signal wires to prevent jabber. Jabber occurs when the signal
level has an indeterminate state because the bus is not being actively driven. This can occur when
all the slaves are in receive mode and the master is slow to turn from receive mode to transmit
mode. This may be because the master purposefully waits in receive mode, or even in a high
impedance state, until it has something to transmit. Jabber causes the receiving device(s) to miss
the first bits of the first character in the packet, which results in the slave rejecting the message
and consequentially not responding. Symptoms of these are poor response times (due to retries),
increasing message error counters, erratic communications, and even a complete failure to
communicate.
Biasing requires that the signal lines be weakly pulled to a defined voltage level of about 1V. There
should only be one bias point on the bus, which is best situated at the master connection point.
The DC source used for the bias must be clean; otherwise noise will be injected. Note that some
devices may (optionally) be able to provide the bus bias, in which case external components will
not be required.

Date: 2015-06-30
10 Communication
NOTICE!
It is extremely important that the 120Ω termination resistors are fitted. Failure to do so
will result in an excessive bias voltage that may damage the devices connected to the
bus.
As the field voltage is much higher than that required, NR cannot assume responsibility
for any damage that may occur to a device connected to the network as a result of
incorrect application of this voltage.
Ensure that the field voltage is not being used for other purposes (i.e. powering logic
inputs) as this may cause noise to be passed to the communication network.
10.2.2 Ethernet Interface

This protective device can provide four rear Ethernet interfaces (optional) and they are unattached
each other. Parameters of each Ethernet port can be configured in the menu “Settings→Device
Setup→Comm Settings”.
10.2.2.1 Ethernet Standardized Communication Cable
It is recommended to use twisted screened eight-core cable as the communication cable. A picture
is shown bellow.
Figure 10.2-2 Ethernet communication cable
10.2.2.2 Connections and Topologies
Each device is connected with an exchanger via communication cable, and thereby it forms a star
structure network. Dual-network is recommended in order to increase reliability. SCADA is also
connected to the exchanger and will play a role of master station, so the every equipment which
has been connected to the exchanger will play a role of slave unit.

Date: 2015-06-30
10 Communication
SCADA
Switch: Net A
Switch: Net B
……
Figure 10.2-3 Ethernet communication structure
10.2.3 IEC60870-5-103 Communication
The IEC specification IEC60870-5-103: Telecontrol Equipment and Systems, Part 5: Transmission
Protocols Section 103 defines the use of standards IEC60870-5-1 to IEC60870-5-5 to perform
communication with protective device. The standard configuration for the IEC60870-5-103
protocol is to use a twisted pair EIA RS-485 connection over distances up to 500m. It also supports
to use an Ethernet connection. The relay operates as a slave in the system, responding to
commands from a master station.
To use the rear port with IEC60870-5-103 communication, the relevant settings to the protective
device must be configured.
10.2.4 DNP3.0 Communication

The DNP3.0 (Distributed Network Protocol) protocol can support the OSI/EPA model of the ISO
(International Organization for Standards), and it includes four parts: application layer protocol,
transport functions, data link layer protocol and data object library. The DNP3.0 protocol is
recommended to use the Ethernet network. This relay operates as a slave in the system,
responding to commands from a master station.
10.3 IEC60870-5-103 Interface over Serial Port
The IEC60870-5-103 interface over serial port (RS-485) is a master/slave interface with the
protective device as the slave device. It is properly developed by NR.
The protective device conforms to compatibility level 3.
The following IEC60870-5-103 facilities are supported by this interface:
1. Initialization (reset)
2. Time synchronization
3. Event record extraction

Date: 2015-06-30
10 Communication
4. General interrogation
5. General commands
6. Disturbance records
10.3.1 Physical Connection and Link Layer
Two EIA RS-485 standardized ports are available for IEC60870-5-103 in this protective device.
The transmission speed is optional: 4800 bit/s, 9600 bit/s, 19200 bit/s or 38400 bit/s.
The link layer strictly abides by the rules defined in the IEC60870-5-103.
10.3.2 Initialization
Whenever the protective device has been powered up, or if the communication parameters have
been changed, a reset command is required to initialize the communications. The protective
device will respond to either of the two reset commands (Reset CU or Reset FCB), the difference
is that the Reset CU will clear any unsent messages in the transmit buffer.
The protective device will respond to the reset command with an identification message ASDU 5,
the COT (Cause Of Transmission) of this response will be either Reset CU or Reset FCB
depending on the nature of the reset command.
10.3.3 Time Synchronization
The protective device time and date can be set using the time synchronization feature of the
IEC60870-5-103 protocol. The protective device will correct for the transmission delay as specified
in IEC60870-5-103. If the time synchronization message is sent as a send/confirm message then
the protective device will respond with a confirmation. Whether the time-synchronization message
is sent as a send confirmation or a broadcast (send/no reply) message, a time synchronization
class 1 event will be generated/produced.
If the protective device clock is synchronized using the IRIG-B input then it will not be possible to
set the protective device time using the IEC60870-5-103 interface. An attempt to set the time via
the interface will cause the protective device to create an event with the current date and time
taken from the IRIG-B synchronized internal clock.
10.3.4 Spontaneous Events

Events are categorized using the following information:
1. Type identification (TYP)
2. Function type (FUN)
3. Information number (INF)
Messages sent to substation automation system are grouped according to IEC60870-5-103

protocol. Operating elements are sent by ASDU2 (time-tagged message with relative time), and
status of binary signal and alarm element are sent by ASDU1 (time-tagged message). The cause
of transmission (COT) of these responses is 1.

Date: 2015-06-30
10 Communication
All spontaneous events can be gained by printing, implementing submenu “IEC103 Info” in the
menu “Print”.
10.3.5 General Interrogation
The GI can be used to read the status of the relay, the function numbers, and information numbers
that will be returned during the GI cycle. The GI cycle strictly abides by the rules defined in the
IEC60870-5-103.
Refer the IEC60870-5-103 standard can get the enough details about general interrogation.
10.3.6 General Service

The generic functions can be used to read the setting and protection measurement of the
protective device, and modify the setting. Two supported type identifications are ASDU 21 and
ASDU 10. For more details about generic functions, see the IEC60870-5-103 standard.
All general classification service group numbers can be gained by printing, implementing submenu
“IEC103 Info” in the menu “Print”.
10.3.7 Disturbance Records
This protective device can store up to 32 disturbance records in its memory. A pickup of the fault
detector or an operation of the relay can make the protective device store the disturbance records.
The disturbance records are stored in uncompressed format and can be extracted using the
standard mechanisms described in IEC60870-5-103.
All channel numbers (ACC) of disturbance data can be gained by printing, implementing submenu
“IEC103 Info” in the menu “Print”.
10.4 Messages Description for IEC61850 Protocol
10.4.1 Overview
The IEC 61850 standard is the result of years of work by electric utilities and vendors of electronic
equipment to produce standardized communications systems. IEC 61850 is a series of standards
describing client/server and peer-to-peer communications, substation design and configuration,
testing, environmental and project standards. The complete set includes:
 IEC 61850-1: Introduction and overview
 IEC 61850-2: Glossary
 IEC 61850-3: General requirements
 IEC 61850-4: System and project management
 IEC 61850-5: Communications and requirements for functions and device models
 IEC 61850-6: Configuration description language for communication in electrical substations

related to IEDs

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10 Communication
 IEC 61850-7-1: Basic communication structure for substation and feeder equipment -
Principles and models
 IEC 61850-7-2: Basic communication structure for substation and feeder equipment - Abstract
communication service interface (ACSI)
 IEC 61850-7-3: Basic communication structure for substation and feeder equipment –
Common data classes
 IEC 61850-7-4: Basic communication structure for substation and feeder equipment –
Compatible logical node classes and data classes
 IEC 61850-8-1: Specific Communication Service Mapping (SCSM) – Mappings to MMS (ISO
9506-1 and ISO 9506-2) and to ISO/IEC 8802-3
 IEC 61850-9-1: Specific Communication Service Mapping (SCSM) – Sampled values over
serial unidirectional multidrop point to point link
 IEC 61850-9-2: Specific Communication Service Mapping (SCSM) – Sampled values over
ISO/IEC 8802-3
 IEC 61850-10: Conformance testing
These documents can be obtained from the IEC (http://www.iec.ch). It is strongly recommended
that all those involved with any IEC 61850 implementation obtain this document set.
10.4.2 Communication Profiles
PCS-978 supports IEC 61850 server services over TCP/IP communication protocol stacks. The
TCP/IP profile requires PCS-978 to have an IP address to establish communications. These
addresses are located in the menu “Settings→Device Setup→Comm Settings”.
1. MMS protocol
IEC 61850 specifies the use of the Manufacturing Message Specification (MMS) at the upper
(application) layer for transfer of real-time data. This protocol has been in existence for a number
of years and provides a set of services suitable for the transfer of data within a substation LAN
environment. IEC 61850-7-2 abstract services and objects are mapped to actual MMS protocol
services in IEC61850-8-1.
2. Client/server
This is a connection-oriented type of communication. The connection is initiated by the client, and
communication activity is controlled by the client. IEC61850 clients are often substation computers
running HMI programs or SOE logging software. Servers are usually substation equipment such
as protection relays, meters, RTUs, transformer, tap changers, or bay controllers.
3. Peer-to-peer
This is a non-connection-oriented, high speed type of communication usually between substation

equipment, such as protection relays, intelligent terminal. GOOSE is the method of peer-to-peer
communication.

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10 Communication
4. Substation configuration language (SCL)
A substation configuration language is a number of files used to describe IED configurations and
communication systems according to IEC 61850-5 and IEC 61850-7. Each configured device has
an IED Capability Description (ICD) file and a Configured IED Description (CID) file. The
substation single line information is stored in a System Specification Description (SSD) file. The
entire substation configuration is stored in a Substation Configuration Description (SCD) file. The
SCD file is the combination of the individual ICD files and the SSD file, moreover, add
communication system parameters (MMS, GOOSE, control block, SV control block) and the
connection relationship of GOOSE and SV to SCD file.
10.4.3 MMS Communication Network Deployment

In order to enhance the stability and reliability of SAS, dual-MMS Ethernet is widely adopted. This
section is applied to introduce the details of dual-MMS Ethernet technology. Generally,
single-MMS Ethernet is recommended to be adopted in the SAS of 110kV and lower voltage levels,
while dual-MMS Ethernet is recommended to be adopted in the SAS of voltage levels above
110kV.
Client-server mode is adopted: clients (SCADA, control center and etc.) communicate with the
IEDs via MMS communication network, and the IEDs operate as the servers. IEDs are connected
to clients passively, and they can interact with the clients according to the configuration and the
issued command of the clients.
Three modes for dual-MMS Ethernet (abbreviated as dual-net) are provided as below.
NOTICE!
Hereinafter, the normal operation status of net means the physical link and TCP link are
both ok. The abnormal operation status of net means physical link or TCP link is
broken.

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10 Communication
10.4.3.1 Dual-net Full Duplex Mode Sharing the Same RCB Instance
Client Client
Net A Net B Net A Net B
Report Instance 1 Report Instance 1

RptEna = true RptEna = true
Report Control Block Report Control Block
IED (Server) IED (Server)

Normal operation status Abnormal operation status
TCP Link MMS Link
Figure 10.4-1 Dual-net full duplex mode sharing the RCB block instance
Net A and Net B share the same report control block (abbreviated as RCB) enabled by the client.
IED sends undifferentiated date through dual-net to the clients. If one net is physically
disconnected, the flag of RCB instance (i.e.: “RptEna” in above figure) is still “true”. Only when
both Net A and Net B are disconnected, the flag of the RCB instance will automatically change to
“false”.
In normal operation status of this mode, IED provides the same MMS service for Net A and Net B.
If one net is physically disconnected (i.e.: “Abnormal operation status” in above figure), the
working mode will switch to single-net mode seamlessly and immediately. Network communication
supervision is unnecessary here, and Buffered Report Control Block (abbreviated as BRCB) need
not to be used. On the other net, date alternation works normally. Therefore, MMS service can
interact normally without interruption. This mode ensures no data loss during one net is in
abnormal operation status.
In this mode, one report will be transmitted twice via dual nets for the same report instance, so the
client needs to distinguish whether two reports are same according to corresponding EntryIDs.

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10 Communication
10.4.3.2 Dual-net Hot-standby Mode Sharing the Same RCB Instance
Client Client
Report Instance 1 Report Instance 1

RptEna = true RptEna = true

TCP Link Main MMS Link Standby MMS Link
Figure 10.4-2 Dual-net hot-standby mode sharing the same RCB instance
In this mode, the MMS service is provided on main MMS link, no MMS service interacts on the
standby MMS link. The definitions of two links are as follows:
 Main MMS Link: Physically connected, TCP level connected, MMS report service available.
 Standby MMS Link: Physically connected, TCP level connected, MMS report service not
available.
If the main net fails to operate (i.e.: “Abnormal operation status” in the above figure), the IED will
set “RptEna” to “false”. Meanwhile the client will detect the failure by heartbeat message or
“keep-alive”, it will automatically enable the RCB instance by setting “RptEna” back to “true”
through standby MMS link. By the buffer function of BRCB, the IED can provide uninterrupted
MMS service on the standby net. However, the differences of BRCB standards among different
manufacturers may cause data loss. Moreover, if duration of net switch is too long, the data loss is
positively as the capacity of BRCB’s buffer function is limited.
NOTICE!
The first mode and second mode, Net A IED host address and Net B IED host address
must be the same.
For example, if the subnet mask is “255.255.0.0”, network prefix of Net A is

“198.120.0.0”, network prefix of Net B is “198.121.0.0”, Net A IP address of the IED is
“198.120.1.2”, and then Net B IP address of the IED must be configured as
“198.121.1.2”, i.e., Net A IED host address =1x256+2=258, Net B IED host address
=1x256+2=258, Net A IED host address equals to Net B IED host address.

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10 Communication
10.4.3.3 Dual-net Full Duplex Mode with 2 Independent RCB Instances
Client Client
Report Instance 1 Report Instance 2 Report Instance 1 Report Instance 2

RptEna = true RptEna = true RptEna = true RptEna = true

TCP Link MMS Link
Figure 10.4-3 Dual-net full duplex mode with 2 independent RCB instances
In this mode, IED provides 2 report instances for each RCB, Net A and Net B work independently
from each other, failures of any net will not affect the other net at all. Tow report instances are
required for each client. Therefore, the IED may be unable to provide enough report instances if
there are too many clients.
Net A and Net B send the same report separately when they operates normally, To ensure no
repeated data is saved into database, massive calculation is required for the client.
Moreover, accurate clock synchronization of the IED is required to distinguish whether 2 reports
are the same report according to the timestamps. Clock synchronization error of the IED may lead
to report loss/redundancy.
As a conclusion, for the second mode, it’s difficult to realize seamless switchover between dual
nets, however, for the third mode, the IED may be unable to provide enough report instances if too
many clients are applied on site. Considering client treatment and IED implementation, the first
mode (Dual-net full duplex mode sharing the same report instance) is recommended for MMS
communication network deployment.
10.4.4 Server Data Organization

IEC61850 defines an object-oriented approach to data and services. An IEC61850 physical device
can contain one or more logical device(s) (for proxy). Each logical device can contain many logical
nodes. Each logical node can contain many data objects. Each data object is composed of data
attributes and data attribute components. Services are available at each level for performing
various functions, such as reading, writing, control commands, and reporting.
Each IED represents one IEC61850 physical device. The physical device contains one or more
logical device(s), and the logical device contains many logical nodes. The logical node LPHD
contains information about the IED physical device. The logical node LLN0 contains common

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10 Communication
information about the IED logical device.
10.4.4.1 Digital Status Values
The GGIO logical node is available in PCS-978 to provide access to digital status points (including
general I/O inputs and warnings) and associated timestamps and quality flags. The data content
must be configured before the data can be used. GGIO provides digital status points for access by
clients. It is intended that clients use GGIO in order to access digital status values from PCS-978.
Clients can utilize the IEC61850 buffered reporting features available from GGIO in order to build
sequence of events (SOE) logs and HMI display screens. Buffered reporting should generally be
used for SOE logs since the buffering capability reduces the chances of missing data state
changes. All needed status data objects are transmitted to HMI clients via buffered reporting, and
the corresponding buffered reporting control block (BRCB) is defined in LLN0.
10.4.4.2 Analog Values
Most of analog measured values are available through the MMXU logical nodes, and metering
values in MMTR, the else in MMXN, MSQI and so on. Each MMXU logical node provides data
from an IED current/voltage “source”. There is one MMXU available for each configurable source.
MMXU1 provides data from CT/VT source 1(usually for protection purpose), and MMXU2 provides
data from CT/VT source 2 (usually for monitor and display purpose). All these analog data objects
are transmitted to HMI clients via unbuffered reporting periodically, and the corresponding
unbuffered reporting control block (URCB) is defined in LLN0. MMXUx logical nodes provide the
following data for each source:
 MMXU.MX.TotW: three-phase active power
 MMXU.MX.TotVAr: three-phase reactive power
 MMXU.MX.TotPF: three-phase power factor
 MMXU.MX.Hz: frequency
 MMXU.MX.PPV.phsAB: phase AB voltage magnitude and angle
 MMXU.MX.PPV.phsBC: phase BC voltage magnitude and angle
 MMXU.MX.PPV.phsCA: Phase CA voltage magnitude and angle
 MMXU.MX.PhV.phsA: phase AG voltage magnitude and angle
 MMXU.MX.PhV.phsB: phase BG voltage magnitude and angle
 MMXU.MX.PhV.phsC: phase CG voltage magnitude and angle
 MMXU.MX.A.phsA: phase A current magnitude and angle
 MMXU.MX.A.phsB: phase B current magnitude and angle
 MMXU.MX.A.phsC: phase C current magnitude and angle
 MMXU.MX.A.neut: ground current magnitude and angle

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10 Communication
10.4.4.3 Protection Logical Nodes
The following list describes the protection elements for PCS-978. The specified relay will contain a
subset of protection elements from this list.
 PDIF: current differential
 PDIS: phase-to-phase distance, phase-to-ground distance and SOTF distance
 PTTR: thermal overload
 PTOC: phase/zero-sequence/negative-sequence overcurrent and overcurrent when VT circuit

failure
 PTUV: undervoltage
 PTUF: underfrequency
 PTOV: overvoltage and auxiliary overvoltage
 PVOC: voltage controlled time overcurrent
 PVPH: volts per Hz
The protection elements listed above contain start (pickup) and operate flags, instead of any
element has its own start (pickup) flag separately, all the elements share a common start (pickup)
flags “PTRC.ST.Str.general”. The operate flag for PTOC1 is “PTOC1.ST.Op.general”. For the
PCS-978 protection elements, these flags take their values from related module for the
corresponding element. Similar to digital status values, the protection trip information is reported
via BRCB, and BRCB also locates in LLN0.
10.4.4.4 LLN0 and Other Logical Nodes
Logical node LLN0 is essential for an IEC61850 based IED. This LN shall be used to address
common issues for Logical Devices. Most of the public services, the common settings, control
values and some device oriented data objects are available here. The public services may be
BRCB, URCB and GSE control blocks and similar global defines for the whole device; the
common settings include all the setting items of communication settings, system settings and
some of the protection setting items, which can be configured to two or more protection elem ents
(logical nodes). In LLN0, the item Loc is a device control object, this Do item indicates the local
operation for complete logical device, when it is true, all the remote control commands to the IED
will be blocked and those commands make effective until the item Loc is changed to false. In
PCS-978, besides the logical nodes we describe above, there are some other logical nodes below
in the IEDs:
 MMXU: This LN shall be used to acquire values from CTs and VTs and calculate measurands
such as r.m.s. values for current and voltage or power flows out of the acquired voltage and
current samples. These values are normally used for operational purposes such as power flow
supervision and management, screen displays, state estimation, etc. The requested accuracy for
these functions has to be provided.
 LPHD: Physical device information, the logical node to model common issues for physical

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10 Communication
device.
 PTRC: Protection trip conditioning, it shall be used to connect the “operate” outputs of one or
more protection functions to a common “trip” to be transmitted to XCBR. In addition or alternatively,
any combination of “operate” outputs of protection functions may be combined to a new “operate”
of PTRC.
 RDRE: Disturbance recorder function. It triggers the fault wave recorder and its output refers
to the “IEEE Standard Format for Transient Data Exchange (COMTRADE) for Power System” (IEC
60255-24). All enabled channels are included in the recording, independently of the trigger mode.
10.4.5 Server Features and Configuration

10.4.5.1 Buffered/unbuffered Reporting
IEC61850 buffered and unbuffered reporting control blocks locate in LLN0, they can be configured
to transmit information of protection trip information (in the Protection logical nodes), binary status
values (in GGIO) and analog measured/calculated values (in MMXU, MMTR and MSQI). The
reporting control blocks can be configured in CID files, and then be sent to the IED via an
IEC61850 client. The following items can be configured.
 TrgOps: Trigger options.
The following bits are supported by PCS-978:
－ Bit 1: Data-change
－ Bit 4: Integrity
－ Bit 5: General interrogation
 OptFlds: Option Fields.
The following bits are supported by PCS-978:
－ Bit 1: Sequence-number
－ Bit 2: Report-time-stamp
－ Bit 3: Reason-for-inclusion
－ Bit 4: Data-set-name
－ Bit 5: Data-reference
－ Bit 7: EntryID (for buffered reports only)
－ Bit 8: Conf-revision
－ Bit 9: Segmentation
 IntgPd: Integrity period.
10.4.5.2 File Transfer
MMS file services are supported to allow transfer of oscillography, event record or other files from

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10 Communication
PCS-978.
10.4.5.3 Timestamps
The Universal Time Coordinated (UTC for short) timestamp associated with all IEC61850 data
items represents the latest change time of either the value or quality flags of the data item
10.4.5.4 Logical Node Name Prefixes
IEC61850 specifies that each logical node can have a name with a total length of 11 characters.
The name is composed of:
 A five or six-character name prefix.
 A four-character standard name (for example, MMXU, GGIO, PIOC, etc.).
 A one or two-character instantiation index.
Complete names are of the form xxxxxxPTOC1, where the xxxxxx character string is configurable.
Details regarding the logical node naming rules are given in IEC61850 parts 6 and 7-2. It is
recommended that a consistent naming convention be used for an entire substation project.
10.4.5.5 GOOSE Services
IEC61850 specifies the type of broadcast data transfer services: Generic Object Oriented
Substation Events (GOOSE). IEC61850 GOOSE services provide virtual LAN (VLAN) support,
Ethernet priority tagging, and Ether-type Application ID configuration. The support for VLANs and
priority tagging allows for the optimization of Ethernet network traffic. GOOSE messages can be
given a higher priority than standard Ethernet traffic, and they can be separated onto specific
VLANs. Devices that transmit GOOSE messages also function as servers. Each GOOSE
publisher contains a “GOOSE control block” to configure and control the transmission.
The GOOSE transmission (including subscribing and publishing) is controlled by GOOSE logic link
settings in device.
PCS-978 supports IEC61850 Generic Object Oriented Substation Event (GOOSE) communication.
All GOOSE messages contain IEC61850 data collected into a dataset. It is this dataset that is
transferred using GOOSE message services. The GOOSE related dataset is configured in the CID
file and it is recommended that the fixed GOOSE be used for implementations that require
GOOSE data transfer between PCS-978 devices.
IEC61850 GOOSE messaging contains a number of configurable parameters, all of which must be
correct to achieve the successful transfer of data. It is critical that the configured datasets at the
transmission and reception devices are an exact match in terms of data structure, and that the
GOOSE addresses and name strings match exactly.

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10 Communication
10.4.6 ACSI Conformance

10.4.6.1 ACSI Basic Conformance Statement
Services Client Server PCS-978
Client-Server Roles
B11 Server side (of Two-party Application-Association) － C1 Y
B12 Client side (of Two-party Application-Association) C1 － N
SCSMS Supported
B21 SCSM: IEC 61850-8-1 used Y Y Y
B22 SCSM: IEC 61850-9-1 used N N N
B23 SCSM: IEC 61850-9-2 used Y N Y
B24 SCSM: other N N N
Generic Substation Event Model (GSE)
B31 Publisher side － O Y
B32 Subscriber side O － Y
Transmission Of Sampled Value Model (SVC)
B41 Publisher side － O N
B42 Subscriber side O － N
Where:
C1: Shall be "M" if support for LOGICAL-DEVICE model has been declared
O: Optional
M: Mandatory
Y: Supported by PCS-978
N: Currently not supported by PCS-978
10.4.6.2 ACSI Models Conformance Statement
M1 Logical device C2 C2 Y
M2 Logical node C3 C3 Y
M3 Data C4 C4 Y
M4 Data set C5 C5 Y
M5 Substitution O O Y
M6 Setting group control O O Y
Reporting
M7 Buffered report control O O Y

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M7-1 sequence-number Y Y Y
M7-2 report-time-stamp Y Y Y
M7-3 reason-for-inclusion Y Y Y
M7-4 data-set-name Y Y Y
M7-5 data-reference Y Y Y
M7-6 buffer-overflow Y Y N
M7-7 entryID Y Y Y
M7-8 BufTm N N N
M7-9 IntgPd Y Y Y
M7-10 GI Y Y Y
M8 Unbuffered report control M M Y
M8-1 sequence-number Y Y Y
M8-2 report-time-stamp Y Y Y
M8-3 reason-for-inclusion Y Y Y
M8-4 data-set-name Y Y Y
M8-5 data-reference Y Y Y
M8-6 BufTm N N N
M8-7 IntgPd N Y Y
Logging
M9 Log control O O N
M9-1 IntgPd N N N
M10 Log O O N
GSE
M12 GOOSE O O Y
M13 GSSE O O N
M14 Multicast SVC O O N
M15 Unicast SVC O O N
M16 Time M M Y
M17 File transfer O O Y
Where:
C2: Shall be "M" if support for LOGICAL-NODE model has been declared
C3: Shall be "M" if support for DATA model has been declared
C4: Shall be "M" if support for DATA-SET, Substitution, Report, Log Control, or Time models has
been declared

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10 Communication
C5: Shall be "M" if support for Report, GSE, or SMV models has been declared
M: Mandatory
Y: Supported by PCS-978
N: Currently not supported by PCS-978
10.4.6.3 ACSI Services Conformance Statement
Service Server/Publisher PCS-978
Server
S1 ServerDirectory M Y
Application association
S2 Associate M Y
S3 Abort M Y
S4 Release M Y
Logical device
S5 LogicalDeviceDirectory M Y
Logical node
S6 LogicalNodeDirectory M Y
S7 GetAllDataValues M Y
Data
S8 GetDataValues M Y
S9 SetDataValues M Y
S10 GetDataDirectory M Y
S11 GetDataDefinition M Y
Data set
S12 GetDataSetValues M Y
S13 SetDataSetValues O Y
S14 CreateDataSet O N
S15 DeleteDataSet O N
S16 GetDataSetDirectory M Y
Substitution
S17 SetDataValues M Y
Setting group control
S18 SelectActiveSG M/O Y
S19 SelectEditSG M/O Y
S20 SetSGValuess M/O Y
S21 ConfirmEditSGValues M/O Y

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S22 GetSGValues M/O Y
S23 GetSGCBValues M/O Y
Reporting
Buffered report control block
S24 Report M Y
S24-1 data-change M Y
S24-2 qchg-change M N
S24-3 data-update M N
S25 GetBRCBValues M Y
S26 SetBRCBValues M Y
Unbuffered report control block
S27 Report M Y
S27-1 data-change M Y
S27-2 qchg-change M N
S27-3 data-update M N
S28 GetURCBValues M Y
S29 SetURCBValues M Y
Logging
Log control block
S30 GetLCBValues O N
S31 SetLCBValues O N
Log
S32 QueryLogByTime O N
S33 QueryLogAfter O N
S34 GetLogStatusValues O N
Generic substation event model (GSE)
GOOSE control block
S35 SendGOOSEMessage M Y
S36 GetGoReference O Y
S37 GetGOOSEElementNumber O N
S38 GetGoCBValues M Y
S39 SetGoCBValuess M N
Control
S51 Select O N
S52 SelectWithValue M Y

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S53 Cancel M Y
S54 Operate M Y
S55 Command-Termination O Y
S56 TimeActivated-Operate O N
File transfer
S57 GetFile M/O Y
S58 SetFile O N
S59 DeleteFile O N
S60 GetFileAttributeValues M/O Y
Time
SNTP M Y
10.4.7 Logical Nodes

10.4.7.1 Logical Nodes Table
The PCS-978 relay supports IEC61850 logical nodes as indicated in the following table. Note that
the actual instantiation of each logical node is determined by the product order code.
Nodes PCS-978
L: System Logical Nodes
LPHD: Physical device information YES
LLN0: Logical node zero YES
P: Logical Nodes For Protection Functions
PDIF: Differential YES
PDIR: Direction comparison －
PDIS: Distance YES
PDOP: Directional overpower －
PDUP: Directional underpower －
PFRC: Rate of change of frequency －
PHAR: Harmonic restraint YES
PHIZ: Ground detector －
PIOC: Instantaneous overcurrent YES
PMRI: Motor restart inhibition －
PMSS: Motor starting time supervision －
POPF: Over power factor －
PPAM: Phase angle measuring －
PSCH: Protection scheme －

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Nodes PCS-978
PSDE: Sensitive directional earth fault YES
PTEF: Transient earth fault －
PTOC: Time overcurrent YES
PTOF: Overfrequency YES
PTOV: Overvoltage YES
PTRC: Protection trip conditioning YES
PTTR: Thermal overload YES
PTUC: Undercurrent －
PTUV: Undervoltage YES
PUPF: Underpower factor －
PTUF: Underfrequency YES
PVOC: Voltage controlled time overcurrent YES
PVPH: Volts per Hz YES
PZSU: Zero speed or underspeed －
R: Logical Nodes For Protection Related Functions
RDRE: Disturbance recorder function YES
RADR: Disturbance recorder channel analogue －
RBDR: Disturbance recorder channel binary －
RDRS: Disturbance record handling －
RBRF: Breaker failure YES
RDIR: Directional element YES
RFLO: Fault locator －
RPSB: Power swing detection/blocking YES
RREC: Autoreclosing －
RSYN: Synchronism-check or synchronizing －
C: Logical Nodes For Control
CALH: Alarm handling －
CCGR: Cooling group control －
CILO: Interlocking －
CPOW: Point-on-wave switching －
CSWI: Switch controller －
G: Logical Nodes For Generic References
GAPC: Generic automatic process control －
GGIO: Generic process I/O YES
GSAL: Generic security application －

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Nodes PCS-978
I: Logical Nodes For Interfacing And Archiving
IARC: Archiving －
IHMI: Human machine interface －
ITCI: Telecontrol interface －
ITMI: Telemonitoring interface －
A: Logical Nodes For Automatic Control
ANCR: Neutral current regulator －
ARCO: Reactive power control －
ATCC: Automatic tap changer controller －
AVCO: Voltage control －
M: Logical Nodes For Metering And Measurement
MDIF: Differential measurements YES
MHAI: Harmonics or interharmonics －
MHAN: Non phase related harmonics or interharmonic －
MMTR: Metering －
MMXN: Non phase related measurement －
MMXU: Measurement YES
MSQI: Sequence and imbalance －
MSTA: Metering statistics －
S: Logical Nodes For Sensors And Monitoring
SARC: Monitoring and diagnostics for arcs －
SIMG: Insulation medium supervision (gas) －
SIML: Insulation medium supervision (liquid) －
SPDC: Monitoring and diagnostics for partial discharges －
X: Logical Nodes For Switchgear
TCTR: Current transformer YES
TVTR: Voltage transformer YES
Y: Logical Nodes For Power Transformers
YEFN: Earth fault neutralizer (Peterson coil) －
YLTC: Tap changer －
YPSH: Power shunt －
YPTR: Power transformer YES
Z: Logical Nodes For Further Power System Equipment
ZAXN: Auxiliary network －
ZBAT: Battery －

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10 Communication
Nodes PCS-978
ZBSH: Bushing －
ZCAB: Power cable －
ZCAP: Capacitor bank －
ZCON: Converter －
ZGEN: Generator －
ZGIL: Gas insulated line －
ZLIN: Power overhead line －
ZMOT: Motor －
ZREA: Reactor YES
ZRRC: Rotating reactive component －
ZSAR: Surge arrestor －
ZTCF: Thyristor controlled frequency converter －
ZTRC: Thyristor controlled reactive component －
10.5 DNP3.0 Interface
10.5.1 Overview
The descriptions given here are intended to accompany this relay. The DNP3.0 protocol is not
described here; please refer to the DNP3.0 protocol standard for the details about the DNP3.0
implementation. This manual only specifies which objects, variations and qualifiers are supported
in this relay, and also specifies what data is available from this relay via DNP3.0.
The relay operates as a DNP3.0 slave and supports subset level 3 of the protocol, plus some of
the features from level 4. The DNP3.0 communication uses the Ethernet ports (electrical or optical)
at the rear side of this relay.
10.5.2 Link Layer Functions

Please see the DNP3.0 protocol standard for the details about the linker layer functions.
10.5.3 Transport Functions

Please see the DNP3.0 protocol standard for the details about the transport functions.
10.5.4 Application Layer Functions

10.5.4.1 Function Code
Function Code Function

0 (0x00) Confirm
1 (0x01) Read
2 (0x02) Write

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10 Communication
Function Code Function

3 (0x03) Select
4 (0x04) Operate
5 (0x05) Direct Operate
6 (0x06) Direct Operate No Acknowledgment
13 (0x0D) Cold Restart
14 (0x0E) Warm Restart
20 (0x14) Enable Unsolicited Responses
21 (0x15) Disable Unsolicited Responses
22 (0x16) Assign Class
23 (0x17) Delay Measurement
10.5.4.2 Supported Object List
The supported object groups and object variations are show in the following table.
Request: Master may issue/Outstation shall parse
Function code: decimalism
Qualifier code: hexadecimal
OBJECT GROUP & VARIATION REQUEST

Group/Variation
Description Function code Qualifier code
No.
1 (read) 00, 01 (start ~ stop)
1 0 Binary Input: Any Variation
22 (assign class) 06 (no range, or all)
00, 01 (start ~ stop)
1 1 Binary Input: Packed format 1 (read)
06 (no range, or all)
1 2 Binary Input: With flags 1 (read)
2 0 Binary Input Event: Any Variation 1 (read)
07, 08 (limited qty)
2 1 Binary Input Event: Without time 1 (read)
2 2 Binary Input Event: With absolute time 1 (read)
2 3 Binary Input Event: With relative time 1 (read)
10 0 Binary output: Any Variation 1 (read)
10 0 Binary output: Any Variation 1 (read)
10 1 Binary output: Packed format 2 (write) 00, 01 (start ~ stop)

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Group/Variation
No.
3 (select)
Binary Command: Control relay output block 4 (operate) 17, 28 (index)
12 1
(CROB) 5 (direct op)
6 (dir. op, no ack) 17, 28 (index)
1 (read) 00, 01 (start ~ stop)
30 0 Analog Input: Any Variation
22 (assign class) 06 (no range, or all)
30 1 Analog Input: 32 ~ bit with flag 1 (read)
30 2 Analog Input: 16 ~ bit with flag 1 (read)
30 3 Analog Input: 32 ~ bit without flag 1 (read)
30 4 Analog Input: 16 ~ bit without flag 1 (read)
30 5 Analog Input: Single ~ prec flt ~ pt with flag 1 (read)
32 0 Analog Input Event: Any Variation 1 (read)
07,08 (limited qty)
32 1 Analog Input Event: 32 ~ bit without time 1 (read)
07,08 (limited qty)
32 2 Analog Input Event: 16 ~ bit without time 1 (read)
07,08 (limited qty)
Analog Input Event: Single ~ prec flt ~ pt 06 (no range, or all)
32 5 1 (read)
without time 07,08 (limited qty)
34 0 Analog Input Deadband: Any Variation 1 (read)
1 (read)
34 1 Analog Input Deadband: 16 ~ bit
2 (write)
17,28 (index)
1 (read)
2 (write)
17,28 (index)
1 (read)
34 3 Analog Input Deadband: Single ~ prec flt ~ pt
2 (write)
17,28 (index)
40 0 Analog Output Status: Any Variation 1 (read)

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Group/Variation
No.
40 1 Analog Output Status: 32 ~ bit with flag 1 (read)
40 2 Analog Output Status: 16 ~ bit with flag 1 (read)
Analog Output Status: single ~ prec flt ~ pt with 00, 01 (start ~ stop)
40 3 1 (read)
flag 06 (no range, or all)
3 (select)
4 (operate) 17,28 (index)
41 1 Analog Output: 32 ~ bit
5 (direct op)
6 (dir. Op, no ack) 17,28 (index)
3 (select)
41 2 Analog Output: 16 ~ bit
5 (direct op)
3 (select)
41 3 Analog Output: Single ~ prec ft ~ pt
5 (direct op)
1 (read) 07 (limited qty = 1)
50 1 Time and Data: Absolute time
2 (write) 07 (limited qty = 1)
Time and Data: Absolute time at last recorded
50 3 2 (write) 07 (limited qty = 1)
time
Time and Data CTO: Absolute time,
51 1
synchronized
Time and Data CTO: Absolute time,
51 2
unsynchronized
1 (read)
60 1 Class Objects: Class 0 data 06 (no range, or all)
22 (assign class)
1 (read)
07,08 (limited qty)
60 2 Class Objects: Class 1 data 20 (enable unsol.)
21 (disable unsol.) 06 (no range, or all)
22 (assign class)
1 (read)
07,08 (limited qty)
60 3 Class Objects: Class 2 data 20 (enable unsol.)
22 (assign class)
60 4 Class Objects : Class 3 data 1 (read)
07,08 (limited qty)

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Group/Variation
No.
20 (enable unsol.)
22 (assign class)
Response: Master shall parse\Outstation may issue
Function code: decimalism
Qualifier code: hexadecimal
OBJECT GROUP & VARIATION RESPONSE

Group/Variation
No.
1 0 Binary Input: Any Variation
1 1 Binary Input: Packed format 129 (response) 00, 01 (start ~ stop)
1 2 Binary Input: With flags 129 (response) 00, 01 (start ~ stop)
2 0 Binary Input Event: Any Variation
129 (response)
2 1 Binary Input Event: Without time 17, 28 (index)
130 (unsol. resp)
129 (response)
2 2 Binary Input Event: With absolute time 17, 28 (index)
130 (unsol. resp)
129 (response)
2 3 Binary Input Event: With relative time 17, 28 (index)
130 (unsol. resp)
10 0 Binary output: Any Variation
10 0 Binary output: Any Variation
10 1 Binary output: Packed format
Binary Command: Control relay output block 129 (response) echo of request
12 1
(CROB)
30 0 Analog Input: Any Variation
30 1 Analog Input: 32 ~ bit with flag 129 (response) 00, 01 (start ~ stop)
30 2 Analog Input: 16 ~ bit with flag 129 (response) 00, 01 (start ~ stop)
30 3 Analog Input: 32 ~ bit without flag 129 (response) 00, 01 (start ~ stop)
30 4 Analog Input: 16 ~ bit without flag 129 (response) 00, 01 (start ~ stop)
30 5 Analog Input: Single ~ prec flt ~ pt with flag 129 (response) 00, 01 (start ~ stop)
32 0 Analog Input Event: Any Variation
129 (response)
32 1 Analog Input Event: 32 ~ bit without time 17,28 (index)
130 (unsol. resp)
129 (response)
32 2 Analog Input Event: 16 ~ bit without time 17,28 (index)
130 (unsol. resp)
Analog Input Event: Single ~ prec flt ~ pt without 129 (response)
32 5 17,28 (index)
time 130 (unsol. resp)
34 0 Analog Input Deadband: Any Variation

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OBJECT GROUP & VARIATION RESPONSE

Group/Variation
No.
129 (response) 00, 01 (start ~ stop)


34 3 Analog Input Deadband: Single ~ prec flt ~ pt
40 0 Analog Output Status: Any Variation

40 1 Analog Output Status: 32 ~ bit with flag 129 (response) 00, 01 (start ~ stop)
40 2 Analog Output Status: 16 ~ bit with flag 129 (response) 00, 01 (start ~ stop)
Analog Output Status: single ~ prec flt ~ pt with
40 3 129 (response) 00, 01 (start ~ stop)
flag
Analog Output: 129 (response) echo of request
41 1
32 ~ bit
41 2
16 ~ bit
41 3
Single ~ prec ft ~ pt
129 (response) 07 (limited qty = 1)
50 1 Time and Data: Absolute time
Time and Data: Absolute time at last recorded

50 3
time
Time and Data CTO: Absolute time, 129 (response)
51 1 07 (limited qty = 1)
synchronized 130 (unsol. resp)
Time and Data CTO: Absolute time, 129 (response)
51 2 07 (limited qty = 1)
unsynchronized 130 (unsol. resp)
60 1 Class Objects: Class 0 data
60 4 Class Objects : Class 3 data
10.5.4.3 Communication Table Configuration
This relay now supports 4 Ethernet clients and 2 serial port clients. Each client can be set the DNP
related communication parameters respectively and be selected the user-defined communication
table. This relay supports a default communication table and 4 user-defined communication tables,
and the default communication table is fixed by the manufacturer and not permitted to configure by
the user.
The user can configure the user-defined communication table through the PCS-Explorer

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10 Communication
configuration tool auxiliary software. The object groups “Binary Input”, “Binary Output”, “Analog
Input” and “Analog Output” can be configured according to the practical engineering demand.
10.5.4.4 Analog Input and Output Configuration
To the analog inputs, the attributes “deadband” and “factor” of each analog input can be configured
independently. To the analog outputs, only the attribute “factor” of each analog output needs to be
configured. If the integer mode is adopted for the data formats of analog values (to “Analog Input”,
“Object Variation” is 1, 2 and 3; to “Analog Output”, “Object Variation” is 1 and 2.), the analog
values will be multiplied by the “factor” respectively to ensure their accuracy. And if the float mode
is adopted for the data formats of analog values, the actual float analog values will be sent directly.
The judgment method of the analog input change is as below: Calculate the difference between
the current new value and the stored history value and make the difference value multiply by the
“factor”, then compare the result with the “deadband” value. If the result is greater than the
“deadband” value, then an event message of corresponding analog input change will be created.
In normal communication process, the master can online read or modify a “deadband” value by
reading or modifying the variation in “Group34”.
10.5.4.5 Binary Output Configuration
The remote control signals, logic links and external extended output commands can be configured
into the “Binary Output” group. The supported control functions are listed as below.
Information Point Pulse On/Null Pulse On/Close Pulse On/Trip Latch On/Null Latch Off/Null
Remote Control Not supported Close Trip Close Trip
Logic Link Not supported Set Clear Set Clear
Extended Output See following description
To an extended output command, if a selected command is controlled remotely, this command

point will output a high ~ level pulse. The pulse width can be decided by the “On ~ time” in the
related “Binary Command” which is from the DNP3.0 master. If the “On ~ time” is set as “0”, the
default pulse width is 500ms.
10.5.4.6 Unsolicited Messages
This relay does not transmit the unsolicited messages if the related logic setting is set as “0”. If the
unsolicited messages want to be transmitted, the related logic setting should be set as “1” or the
DNP3.0 master will transmit “Enable Unsolicited” command to this relay through “Function Code
20” (Enable Unsolicited Messages). If the “Binary Input” state changes or the difference value of
the “Analog Input” is greater than the “deadband” value, this device will transmit unsolicited
messages. If the DNP3.0 master needs not to receive the unsolicited messages, it should forbid
this relay to transmit the unsolicited messages by setting the related logic setting as “0” or through
the “Function Code 21” (Disable Unsolicited Messages).
10.5.4.7 Class Configuration
If the DNP3.0 master calls the Class0 data, this relay will transmit all actual values of the “Analog
Input”, “Binary Input” and “Analog Output”. The classes of the “Analog Input” and “Binary Input”
can be defined by modifying relevant settings. In communication process, the DNP3.0 master can

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10 Communication
online modify the class of an “Analog Input” or a “Binary Input” through “Function Code 22” (Assign
Class).

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11 Installation
11 Installation
Table of Contents
11 Installation ...................................................................................... 11-a
11.1 Overview ........................................................................................................ 11-1
11.2 Safety Information ........................................................................................ 11-1
11.3 Checking Shipment ...................................................................................... 11-2
11.4 Material and Tools Required ........................................................................ 11-2
11.5 Device Location and Ambient Conditions .................................................. 11-2
11.6 Mechanical Installation................................................................................. 11-3
11.7 Electrical Installation and Wiring................................................................. 11-4
11.7.1 Grounding Guidelines ........................................................................................................11-4
11.7.2 Cubicle Grounding .............................................................................................................11-4
11.7.3 Ground Connection on the Device ....................................................................................11-5
11.7.4 Grounding Strips and their Installation ..............................................................................11-6
11.7.5 Guidelines for Wiring .........................................................................................................11-6
11.7.6 Wiring for Electrical Cables ...............................................................................................11-6
List of Figures
Figure 11.6-1 Dimensions and panel cut-out of PCS-978 ..................................................... 11-3
Figure 11.6-2 Demonstration of plugging a board into its corresponding slot .................. 11-4
Figure 11.7-1 Cubicle grounding system ................................................................................ 11-5
Figure 11.7-2 Ground terminal of this relay ............................................................................ 11-5
Figure 11.7-3 Ground strip and termination ........................................................................... 11-6
Figure 11.7-4 Glancing demo about the wiring for electrical cables ................................... 11-7

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11 Installation
11.1 Overview
The device must be shipped, stored and installed with the greatest care. Choose the place of
installation such that the communication interface and the controls on the front of the device are
easily accessible.
Air must circulate freely around the equipment. Observe all the requirements regarding place of
installation and ambient conditions given in this instruction manual.
Take care that the external wiring is properly brought into the equipment and terminated correctly
and pay special attention to grounding. Strictly observe the corresponding guidelines contained in
this section.
11.2 Safety Information
Modules and units may only be replaced by correspondingly trained personnel. Always observe
the basic precautions to avoid damage due to electrostatic discharge when handling the
equipment.
In certain cases, the settings have to be configured according to the demands of the engineering
configuration after replacement. It is therefore assumed that the personnel who replace modules
and units are familiar with the use of the operator program on the service PC.
WARNING!
ONLY insert or withdraw a module while the device power supply is switched off. To this
end, disconnect the power supply cable that connects with the PWR module.
NOTICE!
Industry packs and ribbon cables may ONLY be replaced on a workbench for electronic
equipment. Electronic components are sensitive to electrostatic discharge when not in
the unit's housing.
Jumper links may ONLY be changed on a workbench for electronic equipment.

Electronic components are sensitive to electrostatic discharge when not in the unit's
housing.
A module can ONLY be inserted in the slot designated in the chapter 6. Components
can be damaged or destroyed by inserting module in a wrong slot.
The basic precautions to guard against electrostatic discharge are as follows:
1. Should boards have to be removed from this relay installed in a grounded cubicle in an HV
switchgear installation, please discharge yourself by touching station ground (the cubicle)
beforehand.
2. Only hold electronic boards at the edges, taking care not to touch the components.

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3. Only works on boards that have been removed from the cubicle on a workbench designed for
electronic equipment and wear a grounded wristband. Do not wear a grounded wristband,
however, while inserting or withdrawing units.
4. Always store and ship the electronic boards in their original packing. Place electronic parts in
electrostatic screened packing materials.
11.3 Checking Shipment
Check that the consignment is complete immediately upon receipt. Notify the nearest NR
Company or agent, should departures from the delivery note, the shipping papers or the order be
found.
Visually inspect all the material when unpacking it. When there is evidence of transport damage,
lodge a claim immediately in writing with the last carrier and notify the nearest NR Company or
agent.
If the equipment is not going to be installed immediately, store all the parts in their original packing
in a clean dry place at a moderate temperature. The humidity at a maximum temperature and the
permissible storage temperature range in dry air are listed in Chapter “Technical Data”.
11.4 Material and Tools Required
The necessary mounting kits will be provided, including screws, pincers and assembly
instructions.
A suitable drill and spanners are required to secure the cubicles to the floor using the plugs
provided (if this relay is mounted in cubicles).
11.5 Device Location and Ambient Conditions
NOTICE!
Excessively high temperature can appreciably reduce the operating life of this device.
The place of installation should permit easy access especially to front of the device, i.e. to the
human machine interface of the equipment.
There should also be free access at the rear of the equipment for additions and replacement of
electronic boards.
Since every piece of technical equipment can be damaged or destroyed by inadmissible ambient
conditions, such as:
1. The location should not be exposed to excessive air pollution (dust, aggressive substances).
2. Severe vibration, extreme changes of temperature, high levels of humidity, surge voltages of
high amplitude and short rise time and strong induced magnetic fields should be avoided as

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far as possible.
3. Air must not be allowed to circulate freely around the equipment.
The equipment can in principle be mounted in any attitude, but it is normally mounted vertically
(visibility of markings).
11.6 Mechanical Installation
NOTICE!
It is necessary to leave enough space top and bottom of the cut-out in the cubicle for
heat emission of this device.
The device adopts IEC standard chassis and is rack with modular structure. It uses an integral
faceplate and plug terminal block on backboard for external connections. PCS-978 is IEC 4U high,
and Figure 11.6-1 shows its dimensions and panel cut-out.
Front Side
Cut-Out
Figure 11.6-1 Dimensions and panel cut-out of PCS-978
The safety instructions must be abided by when installing the boards, please see Section 11.2 for
the details.
Following figure shows the installation way of a module being plugged into a corresponding slot.

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11 Installation
Figure 11.6-2 Demonstration of plugging a board into its corresponding slot
In the case of equipment supplied in cubicles, place the cubicles on the foundations that have
been prepared. Take care while doing so not to jam or otherwise damage any of the cables that
have already been installed. Secure the cubicles to the foundations.
11.7 Electrical Installation and Wiring
11.7.1 Grounding Guidelines

NOTICE!
All these precautions can only be effective if the station ground is of good quality.
Switching operations in HV installations generate transient over voltages on control signal cables.
There is also a background of electromagnetic RF fields in electrical installations that can induce
spurious currents in the devices themselves or the leads connected to them.
All these influences can influence the operation of electronic apparatus.
On the other hand, electronic apparatus can transmit interference that can disrupt the operation of
other apparatus.
In order to minimize these influences as far as possible, certain standards have to be observed
with respect to grounding, wiring and screening.
11.7.2 Cubicle Grounding

The cubicle must be designed and fitted out such that the impedance for RF interference of the
ground path from the electronic device to the cubicle ground terminal is as low as possible.
Metal accessories such as side plates, blanking plates etc., must be effectively connected
surface-to-surface to the grounded frame to ensure a low-impedance path to ground for RF
interference. The contact surfaces must not only conduct well, they must also be non-corroding.
NOTICE!
If the above conditions are not fulfilled, there is a possibility of the cubicle or parts of it
forming a resonant circuit at certain frequencies that would amplify the transmission of
interference by the devices installed and also reduce their immunity to induced

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11 Installation
interference.
Movable parts of the cubicle such as doors (front and back) or hinged equipment frames must be
effectively grounded to the frame by three braided copper strips (see Figure 11.7-1).
The metal parts of the cubicle housing and the ground rail are interconnected electrically
conducting and corrosion proof. The contact surfaces shall be as large as possible.
NOTICE!
For metallic connections please observe the voltage difference of both materials
according to the electrochemical code.
The cubicle ground rail must be effectively connected to the station ground rail by a
grounding strip (braided copper).
Door or hinged
equipment frame
Cubicle ground
rail close to floor
Braided
copper strip
Station
ground
Conducting
connection
Figure 11.7-1 Cubicle grounding system
11.7.3 Ground Connection on the Device

There is a ground terminal on the rear panel, and the ground braided copper strip can be
connected with it. Take care that the grounding strip is always as short as possible. The main thing
is that the device is only grounded at one point. Grounding loops from unit to unit are not allowed.
There are some ground terminals on some connectors of this relay, and the sign is “GND”. All the
ground terminals are connected in the cabinet of this relay. So, the ground terminal on the rear
panel (see Figure 11.7-2) is the only ground terminal of this device.
Figure 11.7-2 Ground terminal of this relay

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11 Installation
11.7.4 Grounding Strips and their Installation

High frequency currents are produced by interference in the ground connections and because of
skin effect at these frequencies, only the surface region of the grounding strips is of consequence.
The grounding strips must therefore be of (preferably tinned) braided copper and not round copper
conductors, as the cross-section of round copper would have to be too large.
Proper terminations must be fitted to both ends (press/pinch fit and tinned) with a hole for bolting
them firmly to the items to be connected.
The surfaces to which the grounding strips are bolted must be electrically conducting and
non-corroding.
The following figure shows the ground strip and termination.
Press/pinch fit
cable terminal
Braided
copper strip Terminal bolt
Contact surface
Figure 11.7-3 Ground strip and termination
11.7.5 Guidelines for Wiring

There are several types of cables that are used in the connection of this relay: braided copper
cable, serial communication cable etc. Recommendation of each cable:
 Grounding: braided copper cable, 2.5mm2 ~ 6.0mm 2
 Power supply, binary inputs & outputs: stranded conductor, 1.0mm 2 ~ 2.5mm 2
 AC voltage inputs: stranded conductor, 1.5mm 2
 AC current inputs: stranded conductor, 2.5mm 2
 Serial communication: 4-core shielded cable
 Ethernet communication: 4-pair twisted shielded cable (category 5E)
11.7.6 Wiring for Electrical Cables
DANGER!
NEVER allow a open current transformer (CT) secondary circuit connected to this
device while the primary system is live. Open CT circuit will produce a dangerously high
voltage that cause death.
A female connector is used for connecting the wires with it, and then a female connector plugs into
a corresponding male connector that is in the front of one board. See Chapter “Hardware” for

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11 Installation
further details about the pin defines of these connectors.
The following figure shows the glancing demo about the wiring for the electrical cables.
01 02
03 04
Tighten 05 06
07 08
09 10
11 12
01
13 14
15 16
17 18
19 20
21 22
23 24
Figure 11.7-4 Glancing demo about the wiring for electrical cables

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12 Commissioning
12 Commissioning
Table of Contents
12 Commissioning.............................................................................. 12-a
12.1 Overview ...................................................................................................... 12-1
12.2 Safety Instructions ...................................................................................... 12-1
12.3 Commission Tools ....................................................................................... 12-2
12.3.1 Minimum Equipment Required ......................................................................................... 12-2
12.3.2 Optional Equipment .......................................................................................................... 12-2
12.4 Setting Familiarization ................................................................................ 12-2

12.5 Product Checks ........................................................................................... 12-3
12.5.1 With the Relay De-energized ........................................................................................... 12-3
12.5.2 With the Relay Energized................................................................................................. 12-5
12.5.3 Print Fault Report ............................................................................................................. 12-8
12.5.4 On-load Checks................................................................................................................ 12-8
12.6 Final Checks ................................................................................................ 12-9

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12 Commissioning
12.1 Overview
This device is fully numerical in their design, implementing all protection and non-protection
functions in software. The relay employs a high degree of self-checking and in the unlikely event of
a failure, will give an alarm. As a result of this, the commissioning test does not need to be as
extensive as with non-numeric electronic or electro-mechanical relays.
To commission numerical relays, it is only necessary to verify that the hardware is functioning
correctly and the application-specific software settings have been applied to the relay.
Blank commissioning test and setting records are provided at the end of this manual for
completion as required.
Before carrying out any work on the equipment, the user should be familiar with the contents of the
safety and technical data sections and the ratings on the equipment’s rating label.
12.2 Safety Instructions
DANGER!
Current transformer secondary circuits MUST be short-circuited BEFORE the current

leads to the device are disconnected.
WARNING!
ONLY qualified personnel should work on or in the vicinity of this device. This personnel
MUST be familiar with all safety regulations and service procedures described in this
manual. During operating of electrical device, certain part of the device is under high
voltage. Severe personal injury and significant device damage could result from
improper behavior.
Particular attention must be drawn to the following:
1. The earthing screw of the device must be connected solidly to the protective earth conductor
before any other electrical connection is made.
2. Hazardous voltages can be present on all circuits and components connected to the supply
voltage or to the measuring and test quantities.
3. Hazardous voltages can be present in the device even after disconnection of the supply
voltage (storage capacitors!)
4. The limit values stated in the Chapter “Technical Data” must not be exceeded at all, not even
during testing and commissioning.
5. When testing the device with secondary test equipment, make sure that no other
measurement quantities are connected. Take also into consideration that the trip circuits and

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12 Commissioning
maybe also close commands to the circuit breakers and other primary switches are
disconnected from the device unless expressly stated.
12.3 Commission Tools
NOTICE!
Modern test set may contain many of the above features in one unit.
12.3.1 Minimum Equipment Required

1. Multifunctional dynamic current and voltage injection test set with interval timer.
2. Multimeter with suitable AC current range and AC/DC voltage ranges of 0~440Vac and
0~250Vdc respectively.
3. Continuity tester (if not included in the multimeter).
4. Phase angle meter
5. Phase rotation meter
12.3.2 Optional Equipment

1. An electronic or brushless insulation tester with a DC output not exceeding 500V (for
insulation resistance test when required).
2. A portable PC, with appropriate software (this enables the rear communications port to be
tested, if this is to be used, and will also save considerable time during commissioning).
3. EIA RS-485 to EIA RS-232 converter (if EIA RS-485 IEC60870-5-103 port is being tested).
4. PCS-978 serials dedicated protection tester HELP-9000.
12.4 Setting Familiarization
When commissioning this device for the first time, sufficient time should be allowed to become
familiar with the method by which the settings are applied. A detailed description of the menu
structure of this relay is contained in Chapter “Operation Theory” and Chapter “Settings”.
With the front cover in place all keys are accessible. All menu cells can be read. The LED
indicators and alarms can be reset. Protection or configuration settings can be changed, or fault
and event records cleared. However, menu cells will require the appropriate password to be
entered before changes can be made.
Alternatively, if a portable PC is available together with suitable setting software (such as

PCS-9700 HMI software), the menu can be viewed one page at a time to display a full column of
data and text. This PC software also allows settings to be entered more easily, saved to a file on
disk for future reference or printed to produce a setting record. Refer to the PC software user
manual for details. If the software is being used for the first time, allow sufficient time to become

Date: 2015-06-30
12 Commissioning
familiar with its operation.
12.5 Product Checks
These product checks cover all aspects of the relay which should be checked to ensure that it has
not been physically damaged prior to commissioning, is functioning correctly and all input quantity
measurements are within the stated tolerances.
If the application-specific settings have been applied to the relay prior to commissioning, it is
advisable to make a copy of the settings so as to allow them restoration later. This could be done
by extracting the settings from the relay itself via printer or manually creating a setting record.
12.5.1 With the Relay De-energized
This relay is fully numerical and the hardware is continuously monitored. Commissioning tests can
be kept to a minimum and need only include hardware tests and conjunctive tests. The function
tests are carried out according to user’s correlative regulations.
The following tests are necessary to ensure the normal operation of the equipment before it is first
put into service.
1. Hardware tests
These tests are performed for the following hardware to ensure that there is no hardware defect.
Defects of hardware circuits other than the following can be detected by self-monitoring when the
DC power is supplied.
2. User interfaces test
3. Binary input circuits and output circuits test
4. AC input circuits test
5. Function tests
These tests are performed for the following functions that are fully software-based. Tests of the
protection schemes and fault locator require a dynamic test set.
6. Measuring elements test
7. Timers test
8. Measurement and recording test
9. Conjunctive tests
The tests are performed after the relay is connected with the primary equipment and other external
equipment.
10. On load test
11. Phase sequence check and polarity check

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12 Commissioning
12.5.1.1 Visual Inspection
After unpacking the product, check for any damage to the relay case. If there is any damage, the
internal module might also have been affected, contact the vendor. The following items listed is
necessary.
1. Protection panel
Carefully examine the protection panel, protection equipment inside and other parts inside to see
that no physical damage has occurred since installation.
The rated information of other auxiliary protections should be checked to ensure it is correct for the
particular installation.
2. Panel wiring
Check the conducting wire which is used in the panel to assure that their cross section meeting the
requirement.
Carefully examine the wiring to see that they are no connection failure exists.
3. Label
Check all the isolator binary inputs, terminal blocks, indicators, switches and push buttons to make
sure that their labels meet the requirements of this project.
4. Device plug-in modules
Check each plug-in module of the device on the panel to make sure that they are well installed into
the equipment without any screw loosened.
5. Earthing cable
Check whether the earthing cable from the panel terminal block is safely screwed to the panel
steel sheet.
6. Switch, keypad, isolator binary inputs and push button
Check whether all the switches, device keypad, isolator binary inputs and push buttons work
normally and smoothly.
12.5.1.2 Insulation Test
Insulation resistance tests are only necessary during commissioning if it is required for them to be
done and they have not been performed during installation.
Isolate all wiring from the earth and test the isolation with an electronic or brushless insulation
tester at a DC voltage not exceeding 500V, The circuits need to be tested should include:
1. Voltage transformer circuits
2. Current transformer circuits
3. DC power supply

Date: 2015-06-30
12 Commissioning
4. Optic-isolated control inputs
5. Output contacts
6. Communication ports
The insulation resistance should be greater than 100MΩ at 500V.
Test method:
To unplug all the terminals sockets of this relay, and do the Insulation resistance test for each
circuit above with an electronic or brushless insulation tester.
On completion of the insulation resistance tests, ensure all external wiring is correctly reconnected
to the protection.
12.5.1.3 External Wiring
Check that the external wiring is correct to the relevant relay diagram and scheme diagram.
Ensure as far as practical that phasing/phase rotation appears to be as expected.
Check the wiring against the schematic diagram for the installation to ensure compliance with the
customer’s normal practice.
12.5.1.4 Auxiliary Power Supply
WARNING!
Energize this device ONLY if the power supply is within the specified operating range in
Chapter “Technical Data”.
The relay only can be operated under the auxiliary power supply depending on the relay’s nominal
power supply rating.
The incoming voltage must be within the operating range specified in Chapter “Technical Data”,
before energizing the relay, measure the auxiliary supply to ensure it within the operating range.
Other requirements to the auxiliary power supply are specified in Chapter “Technical Data”. See
this section for further details about the parameters of the power supply.
12.5.2 With the Relay Energized

The following groups of checks verify that the relay hardware and software is functioning correctly
and should be carried out with the auxiliary supply applied to the relay.
The current and voltage transformer connections must remain isolated from the relay for these
checks. The trip circuit should also remain isolated to prevent accidental operation of the
associated circuit breaker.
12.5.2.1 Front Panel LCD Display
Connect the relay to DC power supply correctly and turn the relay on. Check program version and
forming time displayed in command menu to ensure that are corresponding to what ordered.

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12 Commissioning
12.5.2.2 Date and Time
If the time and date is not being maintained by substation automation system, the date and time
should be set manually.
Set the date and time to the correct local time and date using menu item “Clock”.
In the event of the auxiliary supply failing, with a super capacitor fitted on MON board, the time and
date will be maintained. Therefore when the auxiliary supply is restored the time and date w ill be
correct and not need to set again.
To test this, remove the auxiliary supply from the relay for approximately 30s. After being
re-energized, the time and date should be correct.
12.5.2.3 Light Emitting Diodes (LEDs)
On power up, the green LED “HEALTHY” should have illuminated and stayed on indicating that
the relay is healthy.
The relay has latched signal relays which remember the state of the trip, auto-reclose when the
relay was last energized from an auxiliary supply. Therefore these indicators may also illuminate
when the auxiliary supply is applied. If any of these LEDs are on then they should be reset before
proceeding with further testing. If the LED successfully reset, the LED goes out. There is no testing
required for that that LED because it is known to be operational.
It is likely that alarms related to voltage transformer supervision will not reset at this stage.
12.5.2.4 Testing HEALTHY and ALARM LEDs
Apply the rated DC power supply and check that the “HEALTHY” LED is lighting in green. We
need to emphasize that the “HEALTHY” LED is always lighting in operation course except that the
equipment find serious errors in it.
Produce one of the abnormal conditions listed in Chapter “Supervision”, the “ALARM” LED will
light in yellow. When abnormal condition reset, the “ALARM” LED extinguishes.
12.5.2.5 Testing the TRIP LED
The “TRIP” LED will light in red during the setting checks. Therefore no further testing of the
“TRIP” LED is required at this stage.
12.5.2.6 Testing AC Current Inputs
NOTICE!
The closing circuit should remain isolated during these checks to prevent accidental
operation of the associated circuit breaker.
This test verified that the accuracy of current measurement is within the acceptable tolerances.
Apply rated current to each current transformer input in turn; checking its magnitude using a
multimeter/test set readout. The corresponding reading can then be checked in the relays menu.
The measurement accuracy of the protection is 2.5% or 0.02In. However, an additional allowance

Date: 2015-06-30
12 Commissioning
must be made for the accuracy of the test equipment being used.
Group No. Item Input Value Input Angle Display Value Display Angle
Ia
Three-phase current 1 Ib
Ic
Ia
Ic
Ia
Ic
Ia
Three-phase current …… Ib
Ic
Neutral current 1 3I0
Neutral current … 3I0
12.5.2.7 Testing AC Voltage Inputs
NOTICE!
The closing circuit should remain isolated during these checks to prevent accidental
operation of the associated circuit breaker.
This test verified that the accuracy of voltage measurement is within the acceptable tolerances.
Apply rated voltage to each voltage transformer input in turn; checking its magnitude using a
multimeter/test set readout. The corresponding reading can then be checked in the relays menu.
The measurement accuracy of the relay is 2.5% or 0.1V. However an additional allowance must be
made for the accuracy of the test equipment being used.
Ua
Three-phase voltage 1 Ub
Uc
Ua
Three-phase voltage 2 Ub
Uc
Ua
Three-phase voltage 3
Ub

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12 Commissioning
Uc
Ua
Three-phase voltage…… Ub
Uc
Residual voltage 1 3U0
12.5.2.8 Testing Binary Inputs
This test checks that all the binary inputs on the equipment are functioning correctly. The binary
inputs should be energized one at a time, see external connection diagrams for terminal numbers.
Ensure that the voltage applied on the binary input must be within the operating range. The status
of each binary input can be viewed by using relay menu. Sign “1” denotes an energized input and
sign “0” denotes a de-energized input.
Terminal No. Signal Name BI Status on LCD Correct?
12.5.3 Print Fault Report
In order to acquire the details of protection operation, it is convenient to print the fault report of
protection device. The printing work can be easily finished when operator presses the print button
on panel of protection device to energize binary input [BI_Print] or operate control menu. What
should be noticed is that only the latest fault report can be printed if operator presses the print
button. A complete fault report includes the content shown as follows.
1. Trip event report
2. Binary input when protection devices start
3. Self-check and the transition of binary input in the process of devices start
4. Fault wave forms compatible with COMTRADE
5. The setting value when the protection device trips
12.5.4 On-load Checks

The objectives of the on-load checks are:
1. Confirm the external wiring to the current and voltage inputs is correct.
2. Measure the magnitude of on-load current and voltage (if applicable).
3. Check the polarity of each current transformer.

Date: 2015-06-30
12 Commissioning
However, these checks can only be carried out if there are no restrictions preventing the
tenderization of the plant being protected.
Remove all test leads, temporary shorting leads, etc. and replace any external wiring that has
been removed to allow testing.
If it has been necessary to disconnect any of the external wiring from the protection in order to
perform any of the foregoing tests, it should be ensured that all connections are replaced in
accordance with the relevant external connection or scheme diagram. Confirm current and voltage
transformer wiring.
12.6 Final Checks
After the above tests are completed, remove all test or temporary shorting leads, etc. If it has been
necessary to disconnect any of the external wiring from the protection in order to perform the
wiring verification tests, it should be ensured that all connections are replaced in accordance with
the relevant external connection or scheme diagram.
Ensure that the protection has been restored to service.
If the protection is in a new installation or the circuit breaker has just been maintained, the circuit
breaker maintenance and current counters should be zero. If a test block is installed, remove the
test plug and replace the cover so that the protection is put into service.
Ensure that all event records, fault records, disturbance records and alarms have been cleared
and LED’s has been reset before leaving the protection.

Date: 2015-06-30
12 Commissioning

Date: 2015-06-30
13 Maintenance
13 Maintenance
Table of Contents
13 Maintenance ................................................................................... 13-a
13.1 Overview ...................................................................................................... 13-1
13.2 Appearance Check ...................................................................................... 13-1
13.3 Failure Tracing and Repair.......................................................................... 13-1
13.4 Replace Failed Modules .............................................................................. 13-2
13.4.1 Preparation for Replace Module ...................................................................................... 13-2
13.4.2 Replace HMI Module (Front Panel) ................................................................................. 13-3
13.4.3 Replace Module ............................................................................................................... 13-3
13.5 Cleaning ....................................................................................................... 13-3

13.6 Storage ......................................................................................................... 13-3

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13 Maintenance

Date: 2015-06-30
13 Maintenance
13.1 Overview
PCS-978 is designed to require no special maintenance. All measurement and signal processing
circuit are fully solid state. All input modules are also fully solid state. The output relays are
hermetically sealed.
Since the device is almost completely self-monitored, from the measuring inputs to the output
relays, hardware and software defects are automatically detected and reported. The
self-monitoring ensures the high availability of the device and generally allows for a corrective
rather than preventive maintenance strategy. Therefore, maintenance checks in short intervals are
not required.
Operation of the device is automatically blocked when a hardware failure is detected. If a problem
is detected in the external measuring circuits, the device normally only provides alarm messages.
13.2 Appearance Check
1. The relay case should be clean without any dust stratification. Case cover should be sealed
well. No component has any mechanical damage and distortion, and they should be firmly fixed in
the case. Relay terminals should be in good condition. The keys on the front panel with very good
feeling can be operated flexibly.
2. It is only allowed to plug or withdraw relay board when the supply is reliably switched off.
Never allow the CT secondary circuit connected to this equipment to be opened while the primary
system is live when withdrawing an AC module. Never try to insert or withdraw the relay board
when it is unnecessary.
3. Check weld spots on PCB whether they are well soldered without any rosin joint. All dual
inline components must be well plugged.
13.3 Failure Tracing and Repair
Failures will be detected by automatic supervision or regular testing.
When a failure is detected by supervision, a remote alarm is issued and the failure is indicated on
the front panel with LED indicators and LCD display. It is also recorded in the event record.
Failures detected by supervision are traced by checking the “Superv Events” screen on the LCD.
When a failure is detected during regular testing, confirm the following:
1. Test circuit connections are correct
2. Modules are securely inserted in position
3. Correct DC power voltage is applied
4. Correct AC inputs are applied

Date: 2015-06-30
13 Maintenance
5. Test procedures comply with those stated in the manual
13.4 Replace Failed Modules
WARNING!
Module can ONLY be replaced while the device power supply is switched off.
ONLY appropriately trained and qualified personnel can perform the replacement by
strictly observing the precautions against electrostatic discharge.
WARNING!
Five seconds is NECESSARY for discharging the voltage. Hazardous voltage can be
present in the DC circuit just after switching off the DC power supply.
CAUTION!
Take anti-static measures such as wearing an earthed wristband and placing modules
on an earthed conductive mat when handling a module. Otherwise, electronic
components could be damaged.
CAUTION!
Check the device configuration after a replacement of module. Unintended operation of

device may occur.
If the failure is identified to be in the relay module and the user has spare modules, the user can
recover the protection by replacing the failed modules.
Repair at the site should be limited to module replacement. Maintenance at the component level is
not recommended.
Check that the replacement module has an identical module name (AI, PWR, MON DSP, BI, BO,
etc.) and hardware type-form as the removed module. Furthermore, MON module replaced should
have the same software version. In addition, AI and PWR module replaced should have the same
ratings.
The module name is indicated on the top front of the module. The software version is indicated in
LCD menu “Version Info”.
13.4.1 Preparation for Replace Module

1. Switch off the DC power supply
2. Disconnect the trip outputs
3. Short circuit all AC current inputs and disconnect all AC voltage inputs

Date: 2015-06-30
13 Maintenance
13.4.2 Replace HMI Module (Front Panel)

1. Open the relay front panel
2. Unplug the ribbon cable on the front panel by pushing the catch outside.
3. Detach the HMI module from the relay
4. Attach the replacement module in the reverse procedure.
13.4.3 Replace Module

1. Unscrew the module connector
2. Unplug the connector from the target module.
3. Unscrew the module.
4. Pull out the module
5. Inset the replacement module in the reverser procedure.
6. After replacing the MON or DSP module, input the application-specific setting values again.
13.5 Cleaning
Before cleaning the relay, ensure that all AC/DC supplies, current transformer connections are
isolated to prevent any chance of an electric shock whilst cleaning. Use a smooth cloth to clean
the front panel. Do not use abrasive material or detergent chemicals.
13.6 Storage
The spare relay or module should be stored in a dry and clean room. Based on IEC standard
60255-1 the storage temperature should be from -40°C to +70°C, but the temperature of from 0°C
to +40°C is recommended for long-term storage.

Date: 2015-06-30
13 Maintenance

Date: 2015-06-30
Table of Contents
14 Decommissioning and Disposal .................................................. 14-a
14.1 Decommissioning ........................................................................................ 14-3
14.2 Disposal ....................................................................................................... 14-3

Date: 2015-06-30

Date: 2015-06-30
14.1 Decommissioning
DANGER!
Switch OFF the circuit breaker for primary CTs and VTs BEFORE disconnecting the
cables of AI module.
WARNING!
Switch OFF the external miniature circuit breaker of device power supply BEFORE
disconnecting the power supply cable connected to the PWR module.
WARNING!
KEEP an adequate safety distance to live parts of the power substation.
1. Switching off
To switch off the PCS-978, switch off the external miniature circuit breaker of the power supply.
2. Disconnecting Cables
Disconnect the cables in accordance with the rules and recommendations made by relational
department.
3. Dismantling
The PCS-978 rack may now be removed from the system cubicle, after which the cubicles may
also be removed.
14.2 Disposal
In every country there are companies specialized in the proper disposal of electronic waste.
NOTICE!
Strictly observe all local and national laws and regulations when disposing the device.

Date: 2015-06-30

Date: 2015-06-30

In the latest version of the instruction manual, several descriptions on existing features have been
modified.
Manual version and modification history records
Manual Version Software

Date Description of change
Source New Version
 Protection modularization.
R1.02 R2.00 2011-04-22  New terminology rules adopting ANSI function code.
R1.10  Loose-leaf format.
 Add breaker failure protection
R2.00 R2.01 2011-08-18
 Add pole disagreement protection
 Mechanical IO module NR1533 is replaced by NR1536
R2.01 R2.02 2011-11-21
 Add description of inrush current blocking
 Hardware module changes: module NR1301A is
R1.11 replaced by module NR1301T, Module NR1520D is
R2.02 R2.03 2012-10-09 replaced by NR1502M, and add NR1521C module.
 Add a typical configuration for protection of a
three-winding transformer.
 Add temperature protection.
 Add impedance protection.
R2.03 R2.04 R1.12 2013-01-16
 Add negative-sequence overcurrent protection.
 Add residual overvoltage alarm element.
 Update the management function and mechanical
specifications in Chapter 2.
 Revise some errors Chapter 3.
 Add logic schematic of inrush current in Chapter 3.
R2.04 R2.05 2013-06-16  Add 59GAlm the time-inverse feature in Chapter 3.
 Revise pin numbers in Chapter 6.
 Update the figure of dimensions in Chapter 11.
 Update AI module’s application 3 in Chapter 6.
 Update configurable input signal table in Chapter 9.
R1.13
 Errors revised in Chapter 3 and Chapter 4.
 Updated the MON module and DC input module in
Chapter 6.
 Updated the setting group switch function in Chapter 8.
R2.05 R2.06 2015-01-05  Updated the front panel of the device in Chapter 6 and
8.
 Update menu descriptions in Section 8.2.
 Update LCD display descriptions in Section 8.3.
 Update Section 3.3.3.10 and 3.3.3.11.

Date: 2016-06-22
 Update Table 3.3-4 and Table 3.3-5.

 Improve the descriptions and modify corresponding the
2015-04-10
definition of settings, alarms and signals.
 Modify thermal overload protection, add another
realization method, by calculating temperature
2015-06-26 difference
 Modify the indication of Warning, Caution, Danger and
Notice
 Add the output signal “Output_q” and its corresponding
descriptions
R2.05 R2.06
2015-06-29  Add new BO plug-in module, NR1580A
 Add new BI plug-in module, NR1503AR, NR1504AR,
R1.50
NR1508A
 Add the setting [Cfg_NetPorts_Bond], and modify the
menu
 Add function shortcuts key
2015-06-30
 Add access authority management
 Add the setting [Num_Cyc_PreTrigDFR], and modify
the description about disturbance recorder
2015-07-15  Update the age of corresponding IEC standards
R2.05 R2.06
2015-07-20  Add the caution lable about optical fibre and its interface
 Modify the technical datas of protection class for front
R2.06 R2.07 2015-10-19
side and terminal
 Add new AC plug-in module, NR1408 and NR1409
 Update DNP 3.0
 Modify the setting range of [Num_Cyc_PreTrigDFR]
R1.51
 Add dual branches application of breaker failure
protection
 Support system phase sequence: ABC or ACB
 Add the settings [x.En_RevCT] and [x.En_RevCT_NP]
R1.52
 Add the keypad operation: remote control via SLD
 Add the menu “HMI Setup”
R2.07 R2.10 2016-6-22  Add new MON plug-in module, NR1101F
 Modify the lower limit of the time delay of frequency
protection
 Modify the upper limit of the settings
R1.53 [87T.K_Hm2_Inrush], [87T.K_Hm3_Inrush] and
[87T.K_Hm3/Hm5_OvExc]
 Delete the setting [x.64REF.Opt_NP_Polar]
 Add the phase angle calculation module
 Modify the setting range of [87T.Slope1]
 Add output sigals of function enabled
Date: 2016-06-22

PCS-978 - X - Instruction Manual - EN - Overseas General - X - R2.10 PDF

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NR Electric Co., Ltd.

Health and Safety

Qualified personnel are individuals who:

 Are trained in emergency procedures (first aid).

Instructions and Warnings

PCS-978 Transformer Relay i

Securely earthed the earthing terminal of the device.

ii PCS-978 Transformer Relay

environment free of abnormal vibration.

 Printed circuit board

Carefully handle connection cables without applying excessive force.

The firmware may be upgraded to add new features or enhance/modify existing

Copyright © 2016 NR. All rights reserved.

We reserve the rights to make technical improvements without notice.

NR ELECTRIC CO., LTD. Tel: +86-25-87178888

P/N: ZL_PCS-978_X_Instruction Manual_EN_Overseas General_X Version: R2.10

PCS-978 Transformer Relay iii

All contents provided by this manual are summarized as below:

8 Human Machine Interface

14 Decommissioning and Disposal

15 Manual Version History

Typographic and Graphical Conventions

The following symbols are used in drawings:

BI Binary signal via opto-coupler

SET I> Input signal from comparator with setting

EN Input signal of logic setting for function enabling

SIG Input of binary signal except those signals via opto-coupler

Input of other signal

PCS-978 Transformer Relay v

XXX Output signal

IDMT Timer (inverse-time characteristic)

Instrument current transformer

Instrument voltage transformer

---xxx is the symbol

Symbol Corresponding Relationship

vi PCS-978 Transformer Relay

1.2.2 Measurements ...................................................................................................................... 1-9

1.2.3 Configurable Functions ........................................................................................................ 1-9

1.2.4 Miscellaneous Functions ...................................................................................................... 1-9

1.2.5 Communication .................................................................................................................. 1-10

1.2.6 User Interface ..................................................................................................................... 1-10

1.3 Features ......................................................................................................... 1-10

Figure 1.1-2 3-winding transformer ........................................................................................... 1-1

Figure 1.1-3 autotransformer with two sides ........................................................................... 1-2

Figure 1.1-4 autotransformer with three sides ......................................................................... 1-2

Figure 1.1-5 Typical application of a 3-windings transformer................................................ 1-3

Figure 1.1-6 Typical application of an auto-transformer......................................................... 1-3

Figure 1.1-7 Typical application of a shunt reactor ................................................................. 1-4

PCS-978 Transformer Relay 1-a

1-b PCS-978 Transformer Relay

PCS-978 can be applied for a two-winding transformer, three-winding transformer or

PCS-978 is adaptive to the following 2/3-windings transformers or autotransformer.

Figure 1.1-1 2-winding transformer

Figure 1.1-2 3-winding transformer

PCS-978 Transformer Relay 1-1

Figure 1.1-3 autotransformer with two sides

Figure 1.1-4 autotransformer with three sides

1-2 PCS-978 Transformer Relay

49 62PD 50BF 50/51G

87T 50/51Q 51PAlm 21

59G 27P 81O 59GAlm 64REF

Figure 1.1-5 Typical application of a 3-windings transformer