PHYSICAL DESIGN

Physical Design is Physical implementation of Design

 In Physical Design mainly Six inputs are present
1. Logical libraries --> format is .lib --->given by Vendors
2. physical libraries -->format is .lef --->given by vendors
3. Technology file -->format is .tf --->given by fabrication peoples
4. TLU+ file -->format is .TLUP-->given by fabrication people
5. Netlist --->format is .v -->given by Synthesis People
6. Synthesis Design Constraints -->format is .SDC -->given by Synthesis People

PHYSICAL DESIGN PROCESS.

1. DATA PREPARATION.
2. FLOOR PLAN.
3. POWER PLAN-->POWER ROUTING [PRE ROUTE]
4. PLACEMENT.
5. CLOCK TREE SYNTHESIS.-->CLOCK ROUTING.
6. ROUTING.-->DATA ROUTING.-->[POST ROUTE]
7. CHIP FINISHING.
8. VERIFICATION.
9. GDSII FILE.

LOGIC LIBRARIES
Logical libraries :format is .lib
1. Timing information of Standard cells,Soft macros,Hard macros.
2. functionality information of Standard cells,Soft macros.
3. And design rules like max transition ,max capacitance, max fanout.
4. In timing information Cell delays ,Setup,Hold time are present.
5. Cell delay is Function of input transition and output load.
6. Cell delay is calculated based on lookup tables.
7. Cell delays are calculated by using linear delay models, Non linear delay models,CCS models.
8. functionality is used for Optimization Purpose.
9. And also Contain Power information.
10. And contains Leakage power for Default cell,Leakage Power Density for cell,Default Input voltage , Out
put voltage.
And PVT contains ------->Cell leakage Power
-------->Internal Power
--------->Rise Transition
----------->fall transition
---------->>Setup rise
----------->setup fall
-------------->Hold rise
------------->Hold fall
----------------->cell rise
---------------->cell fal
-------------------->Pin Capacitance

And it contains A view(sub directory) i.e. LM(Logical Model view)view.

It contains logical libraries.
 PHYSICAL LIBRARIES
Physical libraries: format is .lef:
1. Physical information of std cells,macros,pads.
2. Pin information.
3. Define unit tile placement.
4. Minimum Width of Resolution.
5. Hight of the placement Rows .
6. Preferred routing Directions.
7. Pitch of the routing tracks.
8. Antenna Rules.
9. Routing Blockages
In physical info height,area,width, are present.
and also it contains two views
1)Cell View:
In this all layout information is present,it is used at the time of tapeout
2)FRAM view:
Fram view is abstract view, it is used at the Place & Route

TECHNOLOGY FILE
Technology file: format is .tf:
1. It contains Name,Number conventions of layer and via
2. It contains Physical,electrical characteristics of layer and via
3. In Physical characteristics Min width,area,height are present.
4. In Electrical characteristics Current Density is present.
5. Units and Precisions of layer and via .
6. Colors and pattern of layer and via .
7. Physical Design rules of layer and via
8. In Physical Design rules Wire to Wire Spacing,Min Width between Layer and via are present.

TLU+
TLU+ files: format is .TLUP:
1. R,C parasitics of metal per unit length.
2. These(R,C parasitics) are used for calculating Net Delays.
3. If TLU+ files are not given then these are getting from .ITF file.
4. For Loading TLU+ files we have load three files .
5. Those are Max Tlu+,Min TLU+,MAP file.
6. MAP file maps the .ITF file and .tf file of the layer and via names.

NETLIST
Netlist: Format is .V
It contains Logical connectivity Of all Cell(Std cells,Macros).
It contain List of nets.
In the design for Knowing connectivity by using Fly lines.
 SDC
SDC :Format is .SDC :
These Constraints are timing Constraints .
These Constraints used for to meet timing requirements.
Constraints are

1. CLOCK DEFINITIONS:Create Clock Period.

2. Generated Clock Definitions
3. Input Delay
4. Output Delay
5. I/O delay
6. Max delay
7. Min Delay
8. --------------->Exceptions<-------------------------
9. Multi cycle path
10. False path
11. Half cycle path
12. Disable timing arcs
13. Case Analysis
Multi cycle path, False path are Exceptions.

OPTIMIZATION CONTROLS
Design Optimization Controls :

1. Enable multiple clocks per register

2. Enable constant propagation
3. Enable multiple port net buffering
4. Enable Constant net buffering
5. Apply timing derating for On-Chip variations
6. Define Don't use or preferred cells
7. Keep Spare cells and unloaded cells
8. Apply area constraints and area recovery
9. Apply area and power cricalranges.
10. Organize paths into groups
11. Prevent clock as data networks
12. modify optimization priorities if needed
13. Enable recovery and removal check.

FLOOR PLAN
FLOOR PLAN:
AT CHIP LEVEL:
FLOOR PLAN IS A STEP WHERE WE CREATING THE PAD CELLS AND SPACIFYING POSITIONS,
PLACING PAD CELLS AND INSERTING PAD FILLER CELLS,FOR WELL CONTINITY.

WELL CONTINITY MEANS IF THE WELL IS NOT CONTINOUS THEN WE HAVE TO CREATE SPECIAL
MASKS. IF WELL IS CONTINOUS THEN THERE IS NO NEED OF CREATING SPECIAL MASKS.

IN FLOOR PLAN MAIN IMPORTANT IS MACRO PLACEMENT.

MACRO IS NOTHING BUT MEMORY CELLS.

IF WE HAVE A LARGE CIRCUIT THEN THERE IS NO NEED OF CREATING EVERY TIME.

THE CIRCUIT IS AVAILABLE IN THE MARKET IN THE FORM OF MACRO OR IP.

MACROS ARE TWO TYPES:(i)HARD MACRO.

(ii)SOFT MACRO.

HARD MACRO:THE CIRCUIT IS FIXED.AND WE DON'T NO WHICH TYPE OF GATES USING INSIDE.WE
KNOW THE ONLY TIMING INFORMATION.WE DON'T KNOW THE FUNCTIONALITY INFORMATION.

SOFT MACRO:THE CIRCUIT IS NOT FIXED.WE KNOW WHICH TYPE OF GATES USING INSIDE.WE KNOW
THE TIMING INFORMATION.WE KNOW THE FUNCTIONALITY INFORMATION.

AND IN FLOORPLAN WE ALSO CREATING THE BLOCKAGES.

BLOCKAGES:BLOCKAGES ARE THE IF LET TAKE WE WANT SOME AREA WHERE NO ONE STD
CELL PLACE.FOR THAT PURPOSE WE ARE USING BLOCKAGES.

BLOCKAGES ARE TWO TYPES:(i)SOFT BLOCKAGES

(ii)HARD BLOCKAGES.

SOFT BLOCKAGES MEANS ONLY BUFFERS ARE PLACED, NO STD CELL PLACED,AND THESE ARE
USED AT (i)BETWEEN TWO MACROS,
(ii)AND BETWEEN MACRO AND BOARDERS.

HARD BLOCKAGES MEANS NO ONE STD CELLS PLACED.AND THESE ARE USED AT THE AROUND
THE MACRO.BECAUSE PIN ACCESSING.

IN THE FLOOR PLAN MAIN OBJECTS ARE MACRO PLACEMENT.,

DEFINE ASPECT RATIO(HEIGHT/WIDTH).
I/O PLACEMENTS.
CORE AREA INITIALIZATION.

CORE AREA :CORE AREA IS DEFINED FOR THE PLACEMENT OF STD CELLS,AND MACROS.

CORE AREA DEPENDS ON (i)ASPECT RATIO

(ii)UTILIZATION.

UTILIZATION=(STD CELL AREA+MACRO AREA+BLOCKAGE AREA)/TOTAL AREA.

STD CELL UTILIZATION=(STD CELL AREA)/(CORE AREA -MACRO AREA).

THESE STD CELLS ARE PLACED IN ROWS.

----->I/O PLACEMENT.
IN I/O PLACEMENT WE HAVING PADS.

PADS ARE USED FOR INTERFACING PURPOSE,AND THESE ARE USED FOR PROVIDING POWER
SUPPLY, DATA SIGNAL,CLOCK SIGNAL.

EASILY THESE CAN BE USED AS PORTS.

PADS ARE DIFFERENT TYPES:(i)POWER PADS,

 (ii)SIGNAL PADS.
(iii)CORNER PADS.
(iv)I/O PADS.

MACRO PLACEMENT (GUIDE LINES)

Macro Placement Depend On
1. FLY LINES
2. PORTS COMMUNICATIONS.
3. MACRO'S ARE PLACED AT BOUNDARIES
4. MACRO GROUPING [LOGICAL HIERARCHY]
5. SPACING BETWEEN MACRO'S
6. MACRO ALIGNMENT
7. NOTCHES AVOIDING
8. ORIENTATION
9. BLOCKAGES
 MACROS ARE ROTATED AS REQUIRED TO OPTIMIZE WIRE LENGTH DURING AUTOMATIC MACRO
PLACEMENT.
 TYPICALLY , MACROS ARE PLACED AROUND EDGES OF BLOCKS,KEEPING ARE LARGE MAIN AREA
FOR STD CELLS
 LEAVE A HALO SPACE BETWEEN MACROS ON ALL SIDES
 FOR A NON PIN SIDES OF MACROS A MINIMAL SEPARATION .IS ADEQUATE.
 FOR PIN SIDES OF MACROS A LARGER SEPARATION IS APPROPRIATE.
 ALLOW CHANNELS FOR ROUTING PIN ACCESS AND POSSIBLE BUFFER INSERTION
 LEAVE SPACE BETWEEN MACRO AND THE EDGE OF CHIP/BLOCK, TO ALLOW FOR BUFFERS
INSERTION AND POWER STRIPES TO FEED STD CELL ROWS BETWEEN MACRO AND BLOCK EDGE.

CALCULATION FOR DISTANCE BETWEEN MACROS:

NO.OF PINS (X) PITCH

DISTANCE BETWEEN MACROS= ------------------------------------------------------
AVAILABLE LAYERS/TOTAL LAYERS

FLOOR PLAN (PAD CELLS)

IN FLOOR PLAN

1. CREATE PHYSICAL ONLY PAD CELLS.PHYSICAL ONLY CELLS MEANS ONLY THOSE HAVING
PHYSICAL INFORMATION ONLY.NO LOGICAL INFORMATION PRESENT.AND THEY DON'T HAVE TIMING
INFORATION ALSO.
2. PHYSICAL ONLY PAD CELLS ARE (i)VDD,VSS PADC CELLS,(ii)CORNER PAD CELLS.
3. PAD CELLS ACTS LIKE AS PORTS.
4. CHIP OUTSIDE PINS ARE CONNECTED TO THE INNER CHIP PADS.
5. PADS TYPES:(i)POWER PADS, (ii)DATA PADS .
6. FOR THE POWER SUPPLY TO THE ALL PADS CREATING A PAD POWER RING .
7. VDD,VSS PADS ARE CONNECTED TO THE CORE VDD,VSS POWER RINGS.
8. FOR FILLING THE GAPS BETWEEN THE PADS FILLED BY PAD FILLER CELLS.
9. THESE PAD FILLER CELLS ARE FOR WELL CONTINUITY.
 PHYSICAL ONLY CELLS ARE:
1. PAD CELLS.
2. END CAP CELLS.
3. TAP CELLS.
4. DECAP CELLS.

POWER PLANNING
IN POWER PLANNING
IR DROP :VOLTAGE TRANSFER IN METAL A DROP OCCURS DUE TO RESISTANCE
OF METAL.THIS IS KNOWN AS IR DROP.

IR DROPS ARE TWO TYPES (i)STATIC IR DROP,(ii)DYNAMIC IR DROP.

STATIC IR DROP:INDEPENDENT OF THE CELL SWITCHING THE DROP IS CALCULATED WITH THE
HELP OF WIRE RESISTANCE.

IMPROVE STATIC IR DROP:(i)WIDTH OF WIRE INCREASE,(ii) OR INCREASE THE NO.OF WIRES

DYNAMIC IR DROP:IR DROP IS CALCULATED WITH THE HELP OF THE SWITCHING OF THE CELLS.

IMPROVE DYNAMIC IR DROP:(i)PLACING DCAP CELLS IN BETWEEN THEM,(iii)INCREASE THE NO

OF STRAPS.

ELECTROMIGRATION: WHEN HIGH CURRENT CONTINUOUSLY PASSING THROUGH A METAL DUE

TO THE HIGH CURRENT THE ATOMS ARE MOVING WITH KINETIC ENERGY AND THEY TRANSFER THE
ENERGY TO ANOTHER ATOMS DUE THESE DAMAGE THE METAL.

IMPROVE:INCREASE METAL WIDTH.

1. FIRST SAVE THE DESIGN, BEFORE GOING TO POWER PLAN.

2. DEFINE LOGICAL P/G CONNECTIONS.
3. APPLY POWER NETWORK CONSTRAINTS.
4. POWER NETWORK CONSTRAINTS ARE
5. (i)NO.OF POWER STRAPS,(ii)POWER STRAPS WIDTH,(iii)NO.OF POWER PADS, (iii)POWER RING
WIDTH.
6. SYNTHESIZE THE POWER NETWORK,ANALYZE POWER NET WORK .
7. ANALYZE POWER NETWORK :(i) P/G NETPAIR (ii) POWER BUDGET OF SYNTHESIZED NETS(iii)PNS
CALCULATES THE REQUIRED NO.OF STRAPS BASED ON PROVIDED CONSTRAINTS. (iv) IR DROP. (v)
ELECTROMIGRATION.
8. ANALYZE IR DROP.
9. IF IR DROP IS MORE THEN MODIFY POWER NETWORK CONSTRAINTS ,AND RESYNTHESIZE POWER
NETWORK.
10. IF IR DROP IS NOT SATISFIED ADD P/G PADS.
11. COMMIT THE POWER NETWORK, HERE STRAPS AND RINGS ARE ROUTED ,SO WE CAN'T MODIFY THE
DESIGN.
12. CONNECT THE MACRO P/G PINS AND PAD P/G PINS TO THE CORE RINGS.
13. CREATE POWER RAILS.ALONG THE STD CELL ROWS.
14. AND RE ANALYZE IR DROP.IF STRAPS ARE NOT SUFFICIENT THEN ADD.
15. APPLY P-NET OPTIONS . WHEN A POWER STRAPS IN METAL 7,POWER STRAPS ARE CONNECTED TO
THE POWER RAILS THROUGH VIA'S. SO IF ANY PLACED INN THAT AREA THEN SHORTS OCCURRED
.FOR AVOIDING THESE PROBLEM WE ARE ADDING P-NET OPTIONS.
16. AFTER THIS INCREMENTAL PLACEMENT:IT MEANS EFFECT CELLS MOVING
POWER PLANNING IS ALSO CALLED AS THE PREROUTES.

BECAUSE IN THE CHIP FIRST POWER NETS ROUTED FIRST.

POWER CALCULATIONS:
----->NUMBER OF THE CORE POWER PAD REQUIRED FOR EACH SIDE OF CHIP=(TOTAL CORE
POWER)/{(NUMBER OF SIDE)*(CORE VOLTAGE)*MAXIMUM ALLOWABLE CURRENT FOR A I/O PAD)} .

----->CORE RING WIDTH:

CORE CURRENT(mA)=(CORE POWER)/(CORE VOLTAGE )

CORE P/G RING WIDTH =(TOTAL CORE CURRENT)/{(N0.OF.SIDES)*(MAXIMUM CURRENT DENSITY OF

THE METAL LAYER USED FOR PG RING)}

------->MAXIMUM CURRENT DENSITY Rj mA.

-------->SHEET RESISTANCE :Rs OHMS/SQUARE.

-------->TOTAL CURRENT =TOTAL POWER CONSUMPTION OF CHIP(P)/VOLTAGE(V).

-------->NO.OF POWER PADS(Npads)=Itotal/Ip

------->Itotal =TOTAL CURRENT

------->Ip OBTAINED FROM IO LIBRARY SPACIFICATION.

-------->NO.OF POWER PINS = Itotal/Ip

-------->MAXIMUM CURRENT SPACIFICATION OF EACH METAL LAYER FROM LIBRARY(Rj).

---------->TOTAL METAL WIDTH REQUIRED ON LAYER1=LAYER2=

Wtotalstrap = Itotal/(2*Rj)

----------->ASSUMING SPACINGS BETWEEN STRAPS=Lspace

L<(Vmax)/(Rj*Rs)

Vmax = MAX ALLOWABLE IR DROP

Rj=MAX CURRENT DENSITY
Rs=SHEET RESISTANCE

---------->TOTAL CORE AREA=Wcore*Hcore

H=HEIGHT
W=WIDTH

----------->NUMBER OF VERTICAL STRAPS=Nv=Wcore/L

----------->NUMBER OF HORIZONTAL STRAPS=NH=Hcore/(2*L)

------------> MIN STRAP WIDTH REQUIRED=Wring/(Nv*Nh)

IR DROP:
------>AVG CURRENT THROUGH EACH STRAP=IstrapAvg=(Itotal)/(2*Nstraps)mA
 -------->APPROPRIATE IR DROP AT THE CENTER OF THE STRAP=Vdrop or IRdrop
=IstrapAvg*Rs*(W/2)*(1/Wstrap)

--------->NUMBER OF STRAPS BETWEEN TWO POWER PADS

Nstrappinspace = Dpadspacing/Lspace.

---------->MIN RING WIDTH = Wring = Ip/Rj microm

POWER
-------->TOTAL POWER=STATIC POWER+DYNAMIC POWER
=LEAKAGE POWER+[INTERNAL POWER+EXT SWITCHING POWER]
=LEAKAGE POWER+[{SHORTCKT+INT POWER}]+EXT SWITCHING POWER]
=LEAKAGE POWER+[{(Vdd*Isc)+(C*V*V*F)+(1/2*C*V*V*F)]

Isc=SHORT CIRCUIT POWER

C=LOAD CAP
S=SWITCHING ACTIVITY FACTOR.

FLOORPLAN (CONGESTION)

CONGESTION: REQUIRED NO.OF ROUTING RESOURCES ARE GREATER THAN THE NO.OF
AVAILABLE ROUTING RESOURCES

1. FOR THE CONGESTION ANALYSIS WE HAVE TO DO FIRST PERFORM GLOBAL ROUTING.

2. BY USING GLOBAL ROUTING CALCULATING CONGESTION.
3. ANALYZE THE CONGESTION [IF WE HAVE CONGESTION MEANS ROUTING PROBLEM].
4. IF THE CONGESTION IS PRESENT THEN MODIFY THE PLACEMENT STRATEGY PARAMETERS LIKE
BLOCKAGES,OFFSET,KEEP OUT MARGINS,SLIVER SIZE AND MACRO, STD CELL CONSTRAINTS.
5. PERFORM CONGESTION DRIVEN VIRTUAL FLAT PLACEMENT.CONGESTION DRIVEN MEANS MOVING
STD CELLS FAR AWAY.
6. REANALYZE THE CONGESTION.IF CONGESTION IS NOT SATISFIED.
7. PERFORM HIGH EFFORT CONGESTION DRIVEN VIRTUAL FLAT PLACEMENT.
8. REANALYZE THE CONGESTION.IF CONGESTION IS NOT SATISFIED.
9. MODIFY THE FLOOR PLAN. IF CONGESTION IS SATISFIED.
10. FIX MACRO PLACEMENT.

FLOOR PLAN(VIRTUAL FLAT PLACEMENT)

VIRTUAL FLAT PLACEMENT:

1. APPLY PLACEMENT STRATEGY PARAMETERS.

2. PERFORM VIRTUAL FLAT PLACEMENT.
PLACEMENT STRATEGY PARAMETERS ARE (i)VIPO(VIRTUAL IN PLACEMENT
OPTIMIZATION),(ii)CONGESTION EFFORT,(iii)SLIVER SIZE,(iv)MACRO PLACEMENT,(v)OPTIMIZATION
ALGORITHMS AND EFFORT.
VIRTUAL FLAT PLACEMENT MEANS VIRTUALLY PLACING THE STD CELLS.AND ANALYZE THE
CONGESTION AND TIMING.
 FLOORPLAN(TIMING)
FLOOR PLAN [TIMING]:
IN FLOOR PLAN TIMING IS ALSO IMPORTANT.

1. BEFORE GOING TO TIMING ,PERFORM GLOBAL ROUTING AND ANALYZE CONGESTION.

2. BY PERFORMING THE GLOBAL ROUTING EXTRACT APPROPRIATE R,C VALUES.
3. IF IN THE DESIGN CONGESTION PRESENT GO TO THE CONGESTION STEP AND MODIFY THE P-NET
OPTIONS FULL TO PARTIAL.
4. PERFORM GLOBAL ROUTING AND ANALYZE CONGESTION.
5. IF IN THE DESIGN CONGESTION PRESENT MODIFY THE P-NET OPTIONS PARTIAL TO COMPLETE.
6. EXTRACT R,C VALUES , ANALYZE THE TIMING.
EXTRACT PARASITIC NET R,C VALUES AND GENERATE A TIMING REPORT.

OPTIMIZE TIMING [DEFAULT]-->IF THE TIMING IS NOT ACCEPTED REPEAT

GLOBAL ROUTING ANALYZE CONGESTION ,TIMING IF NOT ACCEPTED.

PERFORM OPTIMIZE TIMING[HIGH EFFORT]---->OPTIMIZE HIGH EFFORT.

IF THE TIMING IS NOT ACCEPTED ,MODIFY THE FLOOR PLAN /RESYNTHESIZE.

AFTER ACCEPTING THE CONGESTION, TIMING THEN WRITE OUT THE .def file

SAVE THE DESIGN .AND THESE .def FILE IS GIVEN AS INPUT TO THE PLACEMENT

PLACEMENT
IN PLACEMENT STEPS ARE
1. PLACEMENT CHECKS,
2. DFT SETUP.
3. POWER SETUP.
4. PLACEMENT OPTIMIZATION.

PLACEMENT :
AFTER GOING TO PLACEMENT WE HAVE TO CHECKS ,FIX

1. FIX MACRO PLACEMENT.(AGAIN)

2. VERIFY THE P-NET, IGNORED ROUTING LAYERS.
3. VERIFY KEEPOUT VARIABLE SETTINGS.
4. SPECIFY NON DEFAULT ROUTING RULES.
5. CHECK PLACEMENT READINESS.
-->FIX MACRO PLACEMENT AGAIN, BECAUSE AFTER INSERTING THE DESIGN IF MACROS ARE
MOVED THE CHECK.

-->P-NET, IGNORED ROUTING LAYERS ALSO.

-- >MAINTAIN KEEPOUT VARIABLE SETTINGS FURTHER STEPS ALSO

-->NON DEFAULT RULES ARE SPECIAL RULES.LIKE DOUBLE SPACING, DOUBLE WIDTHING.THESE
ARE APPLIED FOR CLOCK WIRES.BECAUSE THOSE HIGH ACTIVITY NETS.
 -->BUT HERE WE ARE ONLY SPECIFYING NON DEFAULT ROUTING RULES[NDR'S].

-->CHECK PLACEMENT READINESS IN WE ARE CHECK

1. FLOOR PLAN ,
2. NETLIST,
3. NARROW PLACEMENT REGIONS,
4. R,C FOR ROTING LAYERS,
5. DESIGN CONSTRAINTS.

PLACEMENT (DFT SETUP)

DFT SETUP:
SCAN CHAINS: SCAN CHAINS ARE NOTHING BUT A GROUP OF REGISTERS CONNECTED SERIALLY.

THESE ARE CONNECTED ARE ALPHANUMERIC MANNER.

THERE ARE TWO TYPE OF MODES PRESENT:(i)FUNCTION MODE,(ii)TEST MODE.

THESE MODE SELECTED BY USING MUX DEVICES.

TEST MODE IS DONE AT AT DFT TIME.

DFT(DESIGN FOR TESTABILITY) IS ONE OF THE STEP IN ASIC FLOW.

HERE SCAN INPUT SI , SCAN OUT IS SO.

WE HAVE A PROBLEM WITH PREEXISTING SCAN CHAINS ,

THE ISSUE IS PREEXISTING SCAN CHAINS ARE CONNECTED FAR AWAY , BECAUSE THEY ARE
CONNECTED BASED ON THE FUNCTIONALITY BASED,

SO FOR CONNECTING THESE WE HAVE TO USE MORE ROUTING ROUTING RESOURCES.

IT CAUSED FOR CONGESTION.

INSERT THE SCAN CHAINS FILE. IF PROBLEM WITH PREEXISTING SCAN CHAINS THEN REORDER
THE NAMES OF THE SCAN REGISTER NAMES.

IT ALSO REDUCES THE HOLD TIME.

PLACEMENT (POWER SET UP)

POWER SETUP:
WE HAVE TWO TYPE OF THE POWER DISSIPATIONS:

1. STATIC POWER DISSIPATION

2. DYNAMIC POWER DISSIPATION
STATIC POWER DISSIPATION:
STATIC POWER DISSIPATION IS IF THE CELLS ARE PRESENT AT THE OFF STATE THEN DUE TO THE
LEAKAGE OF CELLS STATIC POWER DISSIPATION OCCURRS.

THE LEAKAGE IS DUE TO THE JUNCTION LEAKAGE, TUNNELING , SUB THRESHOLD LEAKAGE.

FOR REDUCING THE STATIC POWER DISSIPATION REPLACING THE LVT CELLS WITH HVT CELLS.

HVT CELLS ARE SLOWER,AND LOW LEAKAGE ,HIGH Vt .

LVT CELLS ARE FASTER ,AND HIGH LEAKAGE,LOW Vt.

REPLACING THE LVT CELLS WITH HVT CELLS.

LVT CELLS ARE USED AT CRITICAL PATHS.

DYNAMIC POWER DISSIPATION:

DYNAMIC POWER DISSIPATION IS DUE TO THE SHORT CIRCUIT , INTERNAL LOAD,HIGH SWITCHING.

FOR REDUCING THE DYNAMIC POWER DISSIPATION WE HAVE A LOT OF TECHNIQUES THOSE ARE :

REDUCING THE HIGH TOGGLE RATE NET LENGTHS.THESE TOGGLE RATE IS GETTING FROM
SWITCHING FILE THIS IS GETTING FROM SIMULATION PEOPLE.
AND CONNECTED NEARER TO IT.

ANOTHER TECHNIQUE IS ADDING THE BUFFER IN BETWEEN THE HIGH NET LENGTH NETS.FOR
REDUCING THE HIGH COUPLING CAPACITANCE.(REDUCE THE LOAD CAPACITANCE)

ANOTHER TECHNIQUE IS CONNECT HIGH COUPLING CAPACITANCE NET TO THE LOW CAPACITANCE
PIN OF THE CELL.(SWAPPING THE PIN).

ANOTHER TECHNIQUE IS CLONING ,IT IS CREATING THE SAME CELL AND CONNECT THE SOME OF
THE OUTPUT NET TO THESE.

AND ANOTHER TECHNIQUE IS CELL SIZING.

ANOTHER TECHNIQUE IS GATE LEVEL LOGIC OPTIMIZATION.

PLACEMENT OPTIMIIZATION
PLACEMENT OPTIMIZATION:
PLACEMENT OPTIMIZATION WITH WE HAVE OPTIONS (i)CONGESTION,(ii)AREA RECOVERY
,(iii)POWER,(iv)DFT,(v)TIMING.

BY USING THE CONGESTION OPTION WE CAN REDUCE THE CONGESTION.

BY USING THE POWER OPTION WE CAN REDUCE THE STATIC POWER DISSIPATION,DYNAMIC
POWER DISSIPATION.

BY USING THE AREA RECOVERY OPTION WE CAN REDUCE THE CELLS ,POWER,TIMING.

BY USING THE DFT OPTION WE CAN REDUCE THE ROUTING RESOURECES BY REORDER THE SCAN
CHAINS.

AND IF TIMING IS CRITICAL LOGICAL TIMING DRIVEN PLACEMENT.

AND CONGESTION IS CRITICAL CONGESTION DRIVEN PLACEMNT.

CTS (CLOCK TREE SYNTHESIS)

CLOCK TREE SYNTHESIS :
----->CTS IS THE CONNECT THE CLOCKS TO THE ALL CLOCK PIN OF SEQUENTIAL CIRCUITS.

------->ALL CLOCK PINS ARE DRIVEN BY A SINGLE CLOCK SOURCE.

------->CTS TARGETS :(i)skew ,

(ii)insertion delay

-------->CTS GOALS :(i)max transition,

(ii)max capacitance,
(iii)max fanout,
(iv)max buffer levels.

------->A BUFFER TREES IS BUILT TO BALANCE THE LOADS AND MINIMIZE THE SKEW.

-------->A CLOCK TREE WITH BUFFER LEVELS BETWEEN THE CLOCK SOURCE AND CLOCK SINKS(END
POINTS).

-------->CTS STARTING POINT IS CLOCK SOURCE (SDC DEFINED CREATE_CLOCK)

-------->CTS END POINTS ARE CLOCK PINS OF SEQUENTIAL CELLS.

-------->CLOCK PINS ARE ALSO CALLED AS THE CLOCK SINKS.

-------->WHEN THE CLOCK ROOT IS PRIMARY PORT OF BLOCK.

-------->AT CHIP LEVEL PRIMARY PORTS ARE PADS.

-------->CLOCK PINS ARE DIFFERENT TYPES, THOSE ARE (i) STOP PINS,
(ii)FLOAT PINS,
(iii)EXCLUDE PINS.

-------->STOP PINS:CTS OPTIMIZES FOR CLOCK TREE TARGETS,CLOCK TREE GOALS.

-------->FLOAT PIN:LIKE AS STOP PINS,BUT DELAYS ON CLOCK PIN,MACRO INTERNAL DELAY.

 --------->EXCLUDE PIN:CTS IGNORES TARGETS,FIX CLOCK TREE DRC'S.

CTS (START POINTS AND END POINTS)

IN DESIGN WE HAVING

STATIC TIMING ANALYSIS

STATIC TIMING ANALYSIS DO NOT DEPEND ON INPUTS AND WEATHER IT IS PRESENT IN ON STATE
(OR) OF STATE,SWITCHING.

STATIC TIMING ANALYSIS IS PURELY DEPEND ON THE DELAYS.

SETUP TIME :THE MINIMUM AMOUNT OF TIME THE DATA SHOULD BE STABLE BEFORE ARRIVAL OF
SENSITIVE CLOCK.

HOLD TIME :THE MINIMUM AMOUNT OF TIME THE DATA SHOULD BE STABLE AFTER ARRIVAL OF
SENSITIVE CLOCK.

SETUP CHECK:THE DATA LAUNCHED AT SENSITIVE EDGE OF THE LAUNCH FLOP SHOULD BE
CAPTURED AT NEXT SENSITIVE EDGE OF THE CAPTURED FLOP.

BELOW IS THE SETUP CHECK EQ :

Tcq + Tcomb < Tclk-Tsu

HOLD CHECK:THE DATA LAUNCHED AT SENSITIVE EDGE OF THE LAUNCH FLOP
SHOULD NOT BE CAPTURED AT THE SAME SENSITIVE EDGE OF THE CAPTURED FLOP.

BELOW IS THE HOLD CHECK EQ :

Tcq + Tcomb > Thold

IN THE BASING TIMING DIAGRAM

START POINTS ARE (i)INPUT PORT

(ii)CLOCK PIN OF LAUNCH FLOP.

END POINTS ARE (i)DATA INPUT PIN OF CAPTURE FLOP.

(ii)OUTPUT PORT.

BY THE COMBINATION OF THE THESE START AND END POINTS WE HAVE THE PATHS
LIKE ARE

1. INPUT PORT TO DATA INPUT PIN OF LAUNCH FLOP

2. CLOCK PIN OF THE LAUNCH FLOP TO DATA INPUT PIN OF CAPTURE FLOP
3. INPUT PORT TO OUTPUT PORT
4. CLOCK PIN OF THE LAUNCH FLOP TO OUTPUT PORT.

BY DEPENDING ON THE START POINTS AND END POINTS WE HAVE FOUR TIMING GROUPS PRESENT.
1. INPUT GROUP
2. REGISTER GROUP
3. FEED THROUGH GROUP.
4. OUTPUT GROUP.

THIS IS BASIC TIMING DIAGRAM

REGISTER GROUP:
 START POINT IS CLOCK PIN OF LAUNCH FLOP.
 END POINT IS DATA INPUT PIN OF CAPTURE FLOP
SETUP CHECK EQUATION IS :

Tcq + Tcomb < Tclk-Tsu

HOLD CHECK EQUATION IS :

Tcq + Tcomb > Thold

INPUT GROUP:
 START POINT IS INPUT PORT.
 END POINT IS DATA INPUT PIN OF CAPTURE FLOP.
SETUP CHECK EQUATION IS :

Tinputdelay + Tcomb < Tclk -Tsu

HOLD CHECK EQUATION :

Tinputdelay + Tcomb > Thold

OUTPUT GROUP:
 START POINT IS CLOCK PIN OF LAUNCH FLOP.
 END POINT IS OUTPUT PORT.
SETUP CHECK EQUATION IS :

Tcq + Toutputdelay < Tcq.

HOLD CHECK EQUATION IS :

Tcq + Toutputdelay > Thold.

FEED THROUGH GROUP:

 START POINT IS INPUT PORT .

 END POINT IS OUTPUT GROUP.

SETUP CHECK EQUATION IS :

Tinputdelay + Toutputdelay < Tcq

HOLD CHECK EQUATION IS : Tinputdelay + Toutputdelay > Thold

UNCERTAINITY:
UNCERTAINTY = SKEW + ZITTER + MARGIN

JITTER: IT IS THE VARIATIONS IN THE CLOCK CYCLE AT THE CLOCK EDGES BEFORE
(OR) AFTER

SKEW:

SKEW IS THE DIFFERENCE IN THE ARRIVALS TIMES AT THE END POINTS OF THE CLOCK
TREE.

Tl + Tcq + Tcomb < Tclk - Tsu + Tc

Tcq + Tcomb < Tclk - Tsu + (Tc - Tl)

Tcq + Tcomb < Tclk - Tsu + Tskew

Tcq + Tcomb < Tclk - Tsu + SKEW

SKEW = Tc - Tl = Tskew

SKEW TYPES:

1. POSITIVE SKEW
2. NEGATIVE SKEW
POSITIVE SKEW:

Tcq + Tcomb < Tclk - Tsu + (Tc - Tl)

Tcq + Tcomb < Tclk - Tsu + Tskew
Tcq + Tcomb < Tclk - Tsu + SKEW
WHEN (Tc > Tl) IT IS POSITIVE SKEW

IT IS USEFUL FOR SETUP TIME

IT IS BAD FOR HOLD TIME.

NEGATIVE SKEW:
Tcq + Tcomb < Tclk - Tsu + (Tc - Tl)
Tcq + Tcomb < Tclk - Tsu - Tskew
Tcq + Tcomb < Tclk - Tsu - SKEW
WHEN (Tc < Tl) IT IS NEGATIVE SKEW.

IT IS USEFUL FOR HOLD TIME.

IT IS BAD FOR SETUP TIME.
 CALCULATION OF SLACK:
IT IS THE MAIN IMPORTANT FOR THE TIMING ANALYSIS

THERE ARE MAINLY TWO TIMES ARE PRESENT

1. ARRIVAL TIME
2. REQUIRED TIME
SLACK = REQUIRED TIME - ARRIVAL TIME

POSITIVE SLACK IS GOOD FOR DESIGN

NEGATIVE SLACK IS BAD FOR DESIGN

IF IN THE DESIGN WE HAVE NEGATIVE SLACK THEN WE HAVING TIMING VIOLATIONS IN THE DESIGN.
 LATENCY'S:
IT IS DELAY DIFFERENCE FROM THE CLOCK GENERATION POINT TO THE CLOCK END POINTS.

THERE ARE TWO TYPES OF LATENCY'S PRESENT:

1. SOURCE LATENCY
2. NETWORK LATENCY
SOURCE LATENCY :IT IS THE DELAY DIFFERENCE FROM THE CLOCK GENERATION POINT TO THE
CLOCK DEFINITION POINTS.

NETWORK LATENCY:IT IS THE DELAY DIFFERENCE FROM THE CLOCK DEFINITION POINTS TO
THE CLOCK END POINTS.

CTS (APPLYIN NDRS ON CLOCK NETS)

NDR'S:
NDR'S ARE NOTHING BUT NON DEFAULT ROUTING .

THESE ARE APPLIED ON THE CLOCK NETS .

CLOCK NETS ARE HIGH SWITCHING ACTIVITY NETS.

NDR RULES ARE (i)DOUBLE WIDTH,

(ii)DOUBLE SPACING.

BY APPLYING DOUBLE WIDTH WE CAN AVOID THE ELECTROMIGRATION EFFECT.

BY APPLYING DOUBLE SPACING WE CAN AVOID CROSS TALK EFFECT.

CTS OPTOMIZATION
OPTIMIZATIONS TECHNIQUES:

BUFFERING ----------------->IT WILL IMPROVE SETUP TIME

GATE SIZING---------------->BY DECREASING GATE SIZE DELAY MAY DECREASE(UPSIZE)

DELAY INSERTION------->IT WILL IMPROVE HOLD TIME

BUFFER RELOCATION--->REDUCE SKEW & INSERTION DELAY

FIX MAX TRANSITION---->ADD BUFFERS

FIX MAX CAPACITANCE--->DECREASE NET LENGTH,CLONNING.

ROUTING

ROUTING:
---->CREATE PHYSICAL CONNECTIONS TO ALL DATA SIGNAL PINS,CLOCK PINS THROUGH METAL
INTERCONNECTIONS.

---->PATHS MUST MET TIMINGS.

IN THE ROUTING MAINLY THREE STAGES ARE PRESENT:

(i)GLOBAL ROUTING

(ii)TRACK ASSIGNMENT

(iii)DETAIL ROUTING
 ROUTING (GLOBAL ROUTING)

GLOBAL ROUTING:
--->FIRST THE DESIGN IS DIVIDED INTO SMALL BOXES EVERY BOX IS CALLED GLOBAL ROUTING
CELLS (GCELLS OR BUCKETS)

----->EVERY GCELL HAVING THE A NUMBER OF HORIZONTAL ROUTING RESOURCES AND VERTICAL
ROUTING RESOURCES.

----->GLOBAL ROUTING ASSIGNS NETS(LOGICAL CONNECTIVITY NOT METAL CONNECTIVITY) TO

SPACIFIC METAL LAYERS AND GLOBAL ROUTING CELLS.

------>BY USING GLOBAL ROUTING WE CAN ANALYZE CONGESTION.

------->CONGESTION =(REQUIRED ROUTING RESOURCES > AVAILABLE ROUTING RESOURCES)

------->IF ANY GCELL HAVE CONGESTION THEN DETOURING(AVOID THE GCELL ROUTING THROUGH
ANOTHER GCELL).

ROUTING (TRACK ASSIGNMENT)

TRACK ASSIGNMENTS :
---->ASSIGNS EACH NET TO THE SPACIFIC TRACKS.

---->NETS ARE LAYDOWN THE METAL TRACES.

----->TRACES=METAL CONNECTIVITY..

ROUTING (DETAIL ROUTING)

DETAIL ROUTING:
---->DETAIL ROUTE DONES ACTUAL ROUTING.

----->MEANS ACTUAL ROUTING METAL CONNECTIONS.

----->CHECK ALSO PHYSICAL DRC'S.

----->DETAIL ROUTING DOES NOT WORK ON THE ENTIRE CHIP AT THE SAME TIME LIKE TRACK
ASSIGNMENT.

------>INSTEAD IT WORKS BE REROUTING WITHIN THE CONFINES OF A SMALL AREA CALLED AN

"SBOX".

SBOX : DIVIDE THE BLOCK INTO MINI BOXES THESE ARE USED FOR THE DETAIL ROUTE.

ROUTING (SEARCH AND REPAIR)

 SEARCH AND REPAIR :
---->SEARCH AND REPAIR FIXES REMAINING DRC VIOLATIONS THROUGH MULTIPLE LOOPS USING
PROGRESSIVLY LARGE SBOX.

ECO (ENGINEERING CHANGE ORDER)

ECO:
ECO'S ARE TWO TYPE :1)TIMING ECO'S(TO IMPROVE TIMING)
2)FUNCTIONAL ECO'S(TO ADD FUNCTIONALITY)

TIMING ECO FUNCTIONAL ECO

| |
----------------------------- ---------------------------
| | | |
FREEZE NON-FREEZE FREEZE NON-FREEZE

--------->IT IS THE LATE CHANGE IN THE FLOW.

---------->AFTER ROUTING IF WE WANT ANY CHANGES OR ADDING NEW CELLS , THESE ALL ARE
DONE AT THE ECO STAGE.

HERE TWO TYPE OF ECO'S PRESENT :

(i)FREEZE SILICON ECO

(ii)NON FREEZE SILICON ECO

--------->IN FREEZE SILICON ECO WE HAVE NO CHANCE OF ADDING CELL, HERE SPARE CELLS ARE
USED FOR THESE.

----------->IN NON FREEZE SILICON ECO WE CAN ADD THE CELLS AFTER ROUTING.

CHIP FINISHING

CHIP FINISHING:
IN THE CHIP FINISHING:
WE NEED TO DO:

1. ANTENA FIXING:AS TOTAL AREA OF WIRE INCREASE DURING PROCESSING,THE VOLTAGE

STRESSING THE GATE OXIDE INCREASE IT MAY DAMAGE OXIDE LAYER.
2. RANDOM PARTICAL DEFECTS:RANDOM PARTICAL EFFECT IS (i)WIRES AT MINIMUM SPACING ARE
MOST SUSCEPTABLE TO SHORTS.(ii)WIRES AT MAXIMUM WIDTH ARE MOST SUSCEPTABLE TO
OPENS.
3. REDUNDANT VIA INSERTION:VOID IN VIAS IS A SERIOUS ISSUE IN MANUFACTURING.
4. FILLER CELL INSERTION:SOME PLACEMENT SITES REMAIN EMPTY ON SOME ROWS.
5. METAL FILL INSERTION:METAL OVER ETCHING.
6. METAL SLOTTING :METAL EROSION,METAL LIFT OFF.
ANTENA FIXING TECHNIQUES

(THESE ARE FIX AT THE TIME OF THE SEARCH AND REPAIR)

 SPLITTING METAL(LAYER JUMPING).

 ADDING DIODE IN REVERSE BIAS MANNER.
RANDOM PARTICAL DEFECT FIXING TECHNIQUES

 SPREADING (OR) JOG(PUSH ROUTES OFF-TRACKS BY 1/2 PITCH)-------->REDUCE SHORTS

 WIDENING(INCREASE THE WIRE WIDTH)------------>THIS MAY REDUCE OPENS.
REDUNDANT VIA INSERTION

 REDUNDANT VIA IS THE TECHNIQUE FOR REDUCING VOIDS IN THE METAL LAYER.
FILLER CELL INSERTION

 FILLER CELL INSERTION IS THE ONE OF THE TECHNIQUE FOR UTILIZING THE TOTAL AREA WITH OUT
GAPS .
 IT IS GOOD TECHNIQUE BECAUSE IN THE FUTURE WE CAN REPLACE FILLER CELLS WITH SPARE
CELLS WITH A LOGIC.
METAL FILL INSERTION

 AT THE TIME OF ETCHING THEY USE SOME TYPE OF CHEMICALS DUE TO THAT CHEMICALS METAL
LOSSES MORE FOR THAT ONE WE ARE INSERTING THE METAL FILLS.
METAL SLOTTING

 METAL SLOTTING IS TECHNIQUE FOR AVOIDING THE PROBLEMS LIKE METAL LIFT OFF , METAL
EROSION.

FINAL VERIFICATION GDS FILE EXPORT

FINAL VERIFICATION:

1. PARASITICS EXTRACTION:IT EXTRACT R,C VALUES FOR GETTING ORIGINAL DELAYS. TOOL:STAR RC
XT LICENCE
2. TIMING VERIFICATION:IT IS FIND BY USING PRIME TIME TOOL.
3. LVS ,ERC CHECKS:THESE IS FIND OUT BY USING CALIBRE,HERCULIES TOOLS.
4. DRC CHECKS:THESE IS FIND OUT BY USING CALIBRE,HERCULIES TOOLS.

AFTER VERIFICATION:
1. AFTER THIS WE RELEASE THE GDS FILE
2. IN THIS WE HAVE ALL POLYGONS INFORMATION IS PRESENT.

AFTER GDS

AFTER THIS WE ARE FINALLY BASE TAPE OUT(BTO).

AFTER BASE TAPE OUT WE WILL DO METAL TAPE OUT(MTO).

CALCULATIONS:
POWER CALCULATIONS:
----->NUMBER OF THE CORE POWER PAD REQUIRED FOR EACH SIDE OF CHIP=(TOTAL CORE
POWER)/{(NUMBER OF SIDE)*(CORE VOLTAGE)*MAXIMUM ALLOWABLE CURRENT FOR A I/O PAD)} .

----->CORE RING WIDTH:

CORE CURRENT(mA)=(CORE POWER)/(CORE VOLTAGE )

CORE P/G RING WIDTH =(TOTAL CORE CURRENT)/{(N0.OF.SIDES)*(MAXIMUM CURRENT DENSITY OF

THE METAL LAYER USED FOR PG RING)}

------->MAXIMUM CURRENT DENSITY Rj mA.

-------->SHEET RESISTANCE :Rs OHMS/SQUARE.

-------->TOTAL CURRENT =TOTAL POWER CONSUMPTION OF CHIP(P)/VOLTAGE(V).

-------->NO.OF POWER PADS(Npads)=Itotal/Ip

------->Itotal =TOTAL CURRENT

------->Ip OBTAINED FROM IO LIBRARY SPACIFICATION.

-------->NO.OF POWER PINS = Itotal/Ip

-------->MAXIMUM CURRENT SPACIFICATION OF EACH METAL LAYER FROM LIBRARY(Rj).

---------->TOTAL METAL WIDTH REQUIRED ON LAYER1=LAYER2=

Wtotalstrap = Itotal/(2*Rj)

----------->ASSUMING SPACINGS BETWEEN STRAPS=Lspace

L<(Vmax)/(Rj*Rs)

Vmax = MAX ALLOWABLE IR DROP

Rj=MAX CURRENT DENSITY
Rs=SHEET RESISTANCE

---------->TOTAL CORE AREA=Wcore*Hcore

H=HEIGHT
W=WIDTH

----------->NUMBER OF VERTICAL STRAPS=Nv=Wcore/L

----------->NUMBER OF HORIZONTAL STRAPS=NH=Hcore/(2*L)

------------> MIN STRAP WIDTH REQUIRED=Wring/(Nv*Nh)

IR DROP:
------>AVG CURRENT THROUGH EACH STRAP=IstrapAvg=(Itotal)/(2*Nstraps)mA
 -------->APPROPRIATE IR DROP AT THE CENTER OF THE STRAP=Vdrop or IRdrop
=IstrapAvg*Rs*(W/2)*(1/Wstrap)

--------->NUMBER OF STRAPS BETWEEN TWO POWER PADS

Nstrappinspace = Dpadspacing/Lspace.

---------->MIN RING WIDTH = Wring = Ip/Rj microm

POWER
-------->TOTAL POWER=STATIC POWER+DYNAMIC POWER
=LEAKAGE POWER+[INTERNAL POWER+EXT SWITCHING POWER]
=LEAKAGE POWER+[{SHORT CIRCUIT POWER + POWER+INT POWER}]+EXT SWITCHING
POWER]
=LEAKAGE POWER+[{(Vdd*Isc)+(C*V*V*F)+(1/2*C*V*V*F)]

Isc=SHORT CIRCUIT POWER

C=LOAD CAP
S=SWITCHING ACTIVITY FACTOR.

-----CORE RING WIDTH:

CORE CURRENT=(CORE POWER)/(CORE VOLTAGE).

CORE P/G RING WIDTH=(TOTAL CURRENT)/(NO OF SIDES *MAXIMUM CURRENT DENSITY OF THE
METAL LAYER USED FOR P/G PAD RING)

DIFFERENT FILES IN PHYSICAL DESIGN

FILES:

1. LOGICAL LIBRARIES---------------------------> .lib, .db

2. PHYSICAL LIBRARIES -------------------->.lef, .milkyway (OR) .volcano (OR),.plib(OR).enc
3. TECHNOLOGY FILE ----------------------------> .tf
4. TLU+ ---------------------------------------------->.tlup
5. INTER CONNECT TECHNOLOGY FILE ------> .itf
6. MAPPING FILE ----------------------------------> .map
7. NETLIST ------------------------------------------> .v,(OR) .ddc ,(OR) .db
8. SDC------------------------------------------------> .sdc
9. PHYSICAL ONLY PAD CELLS PLACEMENT FILE ---------------------> .tdf
10. SCAN CHAIN FILE -------------------------------> .scandef
11. TOGGLE RATE FILE------------------------------>.saif, (OR) .vcd
12. ECO FILE ----------------------------------------->.eco
13. GDS FILE------------------------------------------>.gds
14. LOG FILE------------------------------------------>.log
15. REPORT FILE-------------------------------------->.rep
16. DESIGN EXCHANGE FORMAT------------------>.def
17. STANDARD DELAY FORMAT------------------->.sdf
18.

DIFFERENT TYPE OF CELLS

 DIFFERENT TYPE OF CELLS:

 STDCELLS-------------------->Nothing But Base cells(Gates,flops).

 TAP CELLS-------------------->Avoids Latch up Problem(Placing these cells with a particular distance).

 TIE CELLS--------------------->It is used for preventing Damage of cells; Tie High cell(Gate One input is
connected to Vdd, another input is connected to signal net);Tie low cells Gate one input is connected to
Vss, another input is connected to signal .

 END CAP CELLS------------->To Know the end of the row,and At the edges endcap cells are placed to avoid
the cells damages at the end of the row to avoid wrong laser wavelength for correct manufacturing.

 DECAP CELLS---------------->Charge Sharing; To avoid the Dynamic IR drop ,charge stores in the cells and
release the charge to Nets.

 ICG CELLS----------------------->Clock gating cells ,to avoid Dynamic power Dissipation.

 POWER GATING CELLS---->Power gating to avoid static power Dissipation.
PAD CELLS ----------------------->To Interface with outside Devices;Input to of Power,Clock,Pins are
connected to pad cells and outside also.
 CORNER CELLS---------------->Corner Pads are used for Well Continity.
 Macro cells------------------------->Memories.
 Spare Cells-------------------------->Used at the ECO.
 Pad filler cells----------------------->Used for Well Continity,placed in between Pads,Std cells.
 JTAG CELLS---------------------->These are used to check the IO connectivity.

FIXING DRC'S
DRC'S FIXING

DRC'S ARE DIFFERENT TYPES :

1. LOGICAL DRC'S.
2. PHYSICAL DRC'S.
LOGICAL DRC'S:
1. MAX TRANSITION
2. MAX CAPACITANCE
3. MAX FANOUT
MAX TRANSITION:

FIXING TECHNIQUES:

 ADD A BUFFER IN MIDDLE OF THE LONG LENGTH WIRE.

 REDUCE THE WIRE LENGTH.
 ADDING A CHAIN OF BUFFERS.
 MAX CAPACITANCE:

FIXING TECHNIQUES:

 DECREASE WIRE LENGTH AT OUTPUT SIDE.

MAX FANOUT:

FIXING TECHNIQUES:
CLONNING=ADDING A SAME CELL LOAD WILL BE DIVIDED.

 SHARING THE LOAD

PHYSICAL DRC'S:
1. WIRE TO WIRE SPACING(MIN SPACING)
2. MIN WIDTH OF WIRES
3. VIA TO VIA SPACINGS
4. NOTCH AVOIDING
FIXING TECHNIQUES:

 SEARCH AND REPAIR

FIXING CROSSTALK
CROSS TALK:

THE VOLTAGE TRANSFER FROM HIGHLY SWITCHING NET(AGGRESSOR NET) TO ANOTHER

NET (LOW SWITCHING (OR) HIGH SWITCHING (OR) VICTIM NET (OR) CONSTANT NET ) THROUGH
COUPLING CAPACITANCE THESE MAY CAUSE CROSS TALK .

REDUCING TECHNIQUES:

 VICTIM NET WIDTH INCREASING THEN RESISTANCE DECREASE IT IS USED AT ROUTING ALSO.
 SPACING BETWEEN AGGRESSOR NET AND VICTIM NET INCREASE.
 BUFFERING ON CONSTANT NETS (OR) VICTIM NETS.
 PLACING AN GROUND NETS ON BETWEEN THE AGGRESSOR NET AND VICTIM NET THEN VOLTAGE
DISCHARGE ON GROUND NET THEN NO SIGNAL INTEGRITY PROBLEM.THIS IS CALLED SHIELDING .
 MAINTAIN STABLE SUPPLY.
 FAST SLEW RATE.
 JOGING(INCRAESE HALF TRACK BY HALF ITCH).
 LAYER JUMPING(JUMP ONE LAYER ABOVE LAYER AND COMES TO SAME LAYER)
 INCREASE DRIVE STRENTH OF CELL
 CELL SIZING(UP SIZING)
 DEEP N-WELL.
 GUARD RING.

FIXING ELECTRO MIGRATION

 ELECTRO MIGRATION :
WHEN HIGH CURRENT DENSITY TRANSFERRING THROUGH A LONG WIRE FOR A LONG TIME DUE TO
THIS ELECTRONS MOVED WITH HIGH ACCELARATIONS ,DUE TO THIS THOSE ARE TRANSFERRING
THEIR MOMENTUM TO THE METAL ATOMS.DUE TO THESE CAN MIGRATE AND MOVE AWAY FROM
THE METAL .

THIS CAN CAUSES THE SHORTS AND OPENS.

FIXES

BY AVOIDING THIS PROBLEM DOUBLE THE WIDTH OF NETS.

AVOID THE BIG DRIVERS AND LARGE BUFFERS.

FIXING SETUP AND FIXING HOLD TIME

SETUP TIME: THE MINIMUM AMOUNT OF TIME THE DATA SHOULD BE STABLE BEFORE ARRIVAL OF
SENSITIVE CLCK.

SETUP CHECK:THE DATA LAUNCHED AT THE SENSITIVE EDGE OF THE LAUNCH FLOP SHOULD BE
CAPTURED AT THE NEXT SENSITIVE EDGE OF THE CAPTURED FLOP.

HOLD TIME: THE MINIMUM AMOUNT OF TIME THE DATA SHOULD BE STABLE AFTER ARRIVAL OF
SENSITIVE CLOCK.

HOLD CHECK: THE DATA LAUNCHED AT THE SENSITIVE EDGE OF THE LAUNCH FLOP SHOULD NOT
BE CAPTURE AT THE SAME SENSITIVE EDGE OF CAPTURED FLOP.

SETUP FIXES:

1. BUFFER INSERTION
2. REDUCE NET LENGTH
3. CELL UP SIZING.
4. DRIVE STRENGTH OF LAUNCH FLOP INCREASE.
5. LOGICAL OPTIMIZATION ON DATA PATH.
6. USEFUL SKEW.
7. PIPELINING.
8. USE SYNC CELLS.
9. NET WIDTH INCREASE.
10. USE LVT CELLS.
11. SPLITTING THE COMBINATIONAL LOGIC.
12. INCREASE CLOCK PERIOD.
13. USING DOUBLE SYNCHRONIZER USING FLIP FLOPS.
14. REDUNDANT VIA.
HOLD FIXES:

1. DELAY BUFFER INSERTION.

2. CELL DOWN SIZING.
3. INCREASE NET LENGTH.
4. USE HVT CELLS.
5. SCAN CHAIN REORDERING.
6. ADJUSTING CLOCK PERIOD.
7. CAN BE FIXED BY ADDING DELAYS ON INPUT PORTS.

VERIFICATION'S
PHYSICAL VERIFICATION:
IN PHYSICAL VERIFICATION IT CHECKS:

1. LVS(LAYOUT VERSUS SCHEMATIC)

2. DRC(DESIGN RULE CONSTRAINTS CHECK)
3. ERC(ELECTRICAL RULE CHECK)
LAYOUT VERSUS SCHEMATIC(LVS):

INPUTS ARE (.LVS.V) AND (.GDSII) FILES.

COMPARISION TWO ELECTRICAL CIRCUITS EQUIVALENT WITH RESPECT TO THEIR "CONNECTIVITY"

AND "TOTAL TRANSISTOR COUNT".

COMPARISION BETWEEN (.GDSII) FILE AND EXTRCTED NETLIST (.LVS.V) FILE.

FINALLY BOTH ARE CONVERTED INTO A SPICE LEVEL .

LVS CHECKS ARE:

EXTRACT ERRORS :

 SHORTS
 OPENS
 FLOATING NETS.

COMPARE ERRORS:

 PIN ERRORS
 PARAMETRIC ERRORS
 DEVICE MISMATCH
 NET MISMATCH
 MALFORMED DEVICES
 PORTS MISMATCH

DESIGN RULE CONSTARINTS CHECK(DRC):

INPUT IS .GDSII FILE.

CHECKS:

 ACTIVE TO ACTIVE SPACINGS.

 WELL TO WELL SPACINGS.
 MINIMUM CHANNEL LENGTH OF THE TRANSISTOR.
 MINIMMUM METAL WIDTH.
 METAL TO METAL SPACINGS.
 ESD(ELECTRO STATIC DISCHARGE).
 I/O RULES.
 METAL FILL DENSITY.
ELECTRICAL RULE CHECK(ERC):

INPUT IS (.GDSII) FILE .

INVOLVES CHECKING A DESIGN FOR ALL ELECTRICAL CONNECTIONS.

CHECKS ARE:

 WELL AND SUBSTRATE AREAS FOR PROPER CONTACTS AND SPCINGS THERE BY ENSURING
CORRECT POWER CONTACTS AND GROUND CONNECTIONS.
 TO LOCATE FLOATING DEVICES AND FLOATING WELLS.
 TO LOCATE DEVICE WICH ARE SHORTED.
 TO LOCATE DEVICES WITH MISSING CONNECTIONS.
 GATE CONNECTRD DIRECTLY TO SUPPLIES.
 FLOATING INPUTS.

FORMAL VERIFICATIONS:
IN FORMAL VERIFICATION CHECKS ARE LEC(LOGICAL EQUIVALENCE CHECK).

CHECKING BETWEEN FINALLY EXTRCCTED NETLIST(.V) AND SYNTHESIZED NETLIST(.V).

INPUTS ARE EXTRCCTED NETLIST(.V) AND SYNTHESIZED NETLIST(.V).

HERE CHECKING FOR FUNCTIONALITY CORRECTNESS.

SCENARIO'S
SCENARIO
SCENARIO = MODE + CORNER.

MODE: MODE IS DEFINED AS A SET OF CLOCKS , SUPPLY VOLTAGES ,TIMING

CONSTRAINTS AND LIBRARIES.

MODES TYPE:

1. FUNCTIONAL MODE.
2. TEST MODE.
IT CONTAINS SDC CONSTRAINTS.
IN DESIGN DIFFERENT FUNCTIONALITY MODES CONTAINS DIFFERENT SDC'S.
IN DESIGN DIFFERENT FUNCTIONALITY MODES ARE PRESENT.
 CONSTRAINTS IN TEST MODE WHILE THE CHIP IS A DEVICES UNDER TEST:

 TESTER CLOCK PERIOD AND CLOCK SOURCES.

 MODEL TESTER SKEW ON THE INPUT PORTS.
 DIFFERENT TIMING EXCEPTIONS.
 DIFFERENT SETUP/HOLD ON THE OUTPUT PORTS.
 THE SCAN CHAIN IS EXCERSIED IN TEST MODE.(NOT IN FUNCTIONAL MODE).
CORNERS:

CORNERS CONTAINS PVT'S.

PVT : BEST CASE CORNER WORST CASE CORNER.

BEST CASE : --------->FASTEST<-------->MIN DELAYS<------------> FOR HOLD

 MAX DELAYS IN DATA PATH .

 MIN DELAYS IN CLOCK PATH.
PVT: PROCESS---------------------->FAST

VOLTAGE--------------------->HIGH

TEMPERATURE------------>LOW

WORST CASE: --------->SLOWEST<-------->MAX DELAYS<------------> FOR SETUP

 MIN DELAYS IN DATA PATH.

 MAX DELAYS IN CLOCK PATH.
PVT: PROCESS-------------------->SLOW

VOLTAGE-------------------->LOW

TEMPERATURE----------->HIGH