7.) CS EEE F241 8086 Pinout PDF

Topic-V
8086 Pin Out and modes of

Operation
T1. Barry B Brey, The Intel Microprocessors .Pearson, Eight Ed. 2009. Chapter 9
March 3rd –12th 2016

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Pin
3/12/2016 3

Pin Diagram & it’s functions
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8086 or 8088
• Pin Diagram and its functions
• Clock generation
• Bus buffering
• Bus latching
• Timing diagram
• Wait states
• Minimum mode operation vs Maximum mode operation.
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Minimum vs Maximum Operation mode
• 8086 can operates in single processor (Minimum mode) or

multiprocessor (Maximum mode) configurations to achieve
high performance.
Minimum Mode Maximum Mode

 8086 generates control signals  It needs 8288 bus controller to generate
for memory and I/O operations control signals for memory and I/O
operations
 Some functions are not  It allows the use of 8087 coprocessor;
available in minimum mode it also provides other functions
 Compatible with 8085-based
systems
3-6

• 8086 & 8088 both are packaged in 40-pin dual in-line

packages (DIPs)
• 8086 is a 16-bit microprocessor with a 16-bit data bus; 8088

has an 8-bit data bus.
–8086 has pin connections AD0–AD15
–8088 has pin connections AD0–AD7
• Data bus width is the only major difference.

• 8086 transfers 16-bit data more efficiently
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• Signal having common functions (in minimum as well as

in maximum mode)
• Signal having special functions for minimum mode.
• Signal having special functions for maximum mode.
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• Signal having common functions (in minimum as well as in

maximum mode)
• Pin Connections AD7 - AD0
8088 address/data bus lines are multiplexed

--contain the rightmost 8 bits of the memory address or I/O -port
number whenever ALE is active (logic 1)
--or data whenever ALE is inactive (logic 0)
These pins are at their high-impedance state during a hold

acknowledge.
3/12/2016 13

Pin Connections A15 – A8
• 8088 address bus provides the upper-half memory address bits
that are present throughout a bus cycle.
• These address connections go to their high-impedance state
during a hold acknowledge.
Pin Connections AD15 – AD8

• 8086 address/data bus lines compose upper multiplexed
address/data bus on the 8086.
• These lines contain address bits A15–A8 whenever ALE is a logic
1, and data bus connections D15–D8 when ALE is a logic 0.
• These pins enter a high-impedance state when a hold
acknowledge occurs.
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Pin Connections A19/S6 - A16/S3
Address/status bus bits are multiplexed to provide address signals

A19–A16 and status bits S6–S3.
• high-impedance state during hold acknowledge
• status bit S6 is always logic 0,
• bit S5 indicates the condition of the IF flag bit
• S4 and S3 show which segment is accessed during the current
bus cycle.
• S4 S3 = 00 = Alternate Data segment
• S4 S3 = 01 = Stack segment
• S4 S3 = 10 = Code segment
• S4 S3 = 11 = Data segment
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Pin Connections BHE / S7
• The bus high enable pin is used in 8086 to enable the most-
significant data bus bits (D15–D8) during a read or a write operation.
• The state of S7 is always a logic 1.
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Pin Connections RD
When read signal is logic 0, the data bus is receptive to data
from memory or I/O devices
Pin Connections Ready

• Inserts wait states into the timing.
–if placed at a logic 0, the microprocessor enters into wait
states and remains idle
–if logic 1, no effect on the operation
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Pin Connections
INTR
• Interrupt request is used to request a hardware interrupt.
– If INTR is held high when IF = 1, 8086/8088

enters an interrupt acknowledge cycle after the current
instruction has completed execution
NMI
• The non-maskable interrupt input is similar to INTR.
– does not check IF flag bit for logic 1
– if activated, uses interrupt vector 2

Pin Connections
TEST
• The TEST pin is an input that is tested by the WAIT instruction.
• If TEST is a logic 0, the WAIT instruction functions as an NOP,

(EXECUTION WILL CONTINUE)
• If TEST is a logic 1, processor remains in idle state.
• The TEST pin is most often connected to

the 8087 numeric coprocessor.

Pin Connections
RESET
• Causes the microprocessor to reset itself if held high a minimum of
four clocking periods.
– when 8086/8088 is reset, it executes instructions at memory
location FFFFOH
– also disables future interrupts by clearing IF flag
CLK
• The clock pin provides the basic timing signal.
– must have a duty cycle of 33 % (high for one third of clocking
period, low for two thirds) to provide proper internal timing
– -range 5-10 MHz
Pin Connections
VCC
• This power supply input provides a +5.0 V, ±10 % signal to the
microprocessor.
GND
• The ground connection is the return for the power supply.
– 8086/8088 microprocessors have two pins labeled GND
– Both must be connected to ground for proper operation

Pin Connections
MN/MX
• Minimum/maximum mode pin selects either minimum or

Maximum mode operation.
– if minimum mode selected, the MN/MX pin must be
connected directly to +5.0 V

(a) The pin-out of the 8086 in maximum mode;
(b) the pin-out of the 8086 in minimum mode.

Minimum Mode Pins
• Minimum mode operation is obtained by connecting the MN/MX

pin directly to +5.0 V
M/IO
• M/IO (8086) or IO/M (8088) pin selects memory or I/O.
– indicates the address bus contains either a memory address or an
I/O port address.
– high-impedance state during hold acknowledge

Minimum Mode Pins
WR
• Write line indicates 8086/8088 is outputting data to a memory or
I/O device.
– during the time WR is a logic 0, the data bus contains valid
data for memory or I/O
– high-impedance during a hold acknowledge
INTA
• The interrupt acknowledge signal is a response to the INTR input
pin.
– normally used to gate the interrupt vector number onto the data
bus in response to an interrupt
Minimum Mode Pins
ALE
• Address latch enable shows the 8086 address/data bus
contains an address.
– can be a memory address or an I/O port number
– ALE signal doesn’t float during hold acknowledge
DT/R
• The data transmit/receive signal shows that the microprocessor
data bus is transmitting (DT/R = 1) or receiving (DT/R = 0) data.
– used to enable external data bus buffers

Minimum Mode Pins
DEN
• Data bus enable activates external data bus buffers.
HOLD, HLDA
• Hold input requests a direct memory access (DMA).
– if HOLD signal is a logic 1, the microprocessor stops executing
software and places address, data, and control bus at high-
impedance
– if a logic 0, software executes normally
– Hold acknowledge (HLDA) send by microprocessor, indicates
the 8086/8088 has entered the hold state.
Minimum Mode Pins
SS0
• The SS0 status line is equivalent to the S0 pin in maximum mode
operation.
• Signal is combined with IO/M and DT/R to decode the function of
the current bus cycle.
IO/M’ DT/R’ SS0’ FUNCTION
0 0 0 INTERRUPT ACKNOWLEDGEMENT
0 0 1 MEMORY READ
0 1 0 MEMORY WRITE
0 1 1 HALT
1 0 0 OPCODE FETCH
1 0 1 I/O READ
1 1 0 I/O WRITE
1 1 1 PASSIVE
Maximum Mode Pins
• In order to achieve maximum mode for use with external
coprocessors, connect the MN/MX pin to ground.
S2, S1, and S0

• Status bits indicate function of the current bus cycle.
– normally decoded by the 8288 bus controller

Maximum Mode Pins
S2, S1, and S0

S2’ S1’ S0’ FUNCTION
0 0 0 INTERRUPT ACKNOWLEDGEMENT
0 0 1 I/O READ
0 1 0 I/O WRITE
0 1 1 HALT
1 0 0 OPCODE FETCH
1 0 1 MEMORY READ
1 1 0 MEMORY WRITE
1 1 1 PASSIVE

Maximum Mode Pins
RQ/GT1 & RQ/GT0 (higher priority)
• The request/grant pins request direct memory accesses (DMA)

during maximum mode operation.
– bidirectional; used to request and grant a DMA operation
LOCK
• The lock output is used to lock peripherals off the system. This pin
is activated by using the LOCK: prefix on any instruction.

Maximum Mode Pins
QS1 & QS0
• The queue status bits show the status of the internal instruction
queue.
– provided for access by the 8087 coprocessor
QS1 QS0 FUNCTION

0 0 QUEUE IS IDLE
0 1 FIRST BYTE OF OPCODE
1 0 QUEUE IS EMPTY
1 1 SUBSEQUENT BYTE OF OPCODE

CLOCK GENERATOR (8284A)
• CLK is crystal controlled clock sent to 8086 from an external

clock generator device such as 8284.
• One cycle of this clock is called a T state.
• A state is measured as falling edge of one clock pulse to falling

edge of next clock pulse


• With no clock generator, many circuits would be required to
generate the clock (CLK).
• 8284A provides the following basic functions:

– clock generation;
– RESET & READY synch;

Different versions of 8086 have maximum clock frequencies of

between 5MHz and 10MHz.
The minimum time of one state will be between 100nS to 200nS
Basic operation such as
• reading a byte from memory /port

• writing a byte to a memory/port
called a machine cycle

The pin-out of the 8284A clock generator.


X1 and X2
• The crystal oscillator pins connect to an external crystal used as the
timing source for the clock generator and all its functions

• The frequency/crystal select input chooses the clocking source for
the 8284A.
– if held high, an external clock is provided to the EFI input pin
– if held low, the internal crystal oscillator provides the timing
signal

CLK
• The clock output pin provides the CLK input signal to 8086/8088
and other components.
– output signal is one third of the crystal or EFI input frequency
– 33% duty cycle required by the 8086/8088
PCLK
• The peripheral clock signal is one sixth the crystal or EFI input
frequency.
– PCLK output provides a clock signal to the peripheral equipment
in the system


RES
• Reset input is an active-low input to 8284A.
– often connected to an RC network that provides power-on
resetting
RESET
Reset output is connected to the 8086/8088 RESET input pin.

BUS BUFFERING & LATCHING
• Before 8086/8088 can be used with memory or I/O interfaces, their

multiplexed buses must be demultiplexed.

CPU pin descriptions:
Minmode operation
signals (MN/MX=1) Time-
0V=“0”, GND 1 40 Vcc multiplexed
referenc AD14 AD15 5V±10% Address Bus
e for all AD13 A16/S3 /Status
voltages AD12 A17/S4 signals
Time-multiplexed AD11 A18/S5 (outputs)
Address (outputs)/ AD10 A19/S6
___
Data Bus AD9 SS0 ___ (HIGH) Contro Operation Mode,
(bidirectional)
AD8 MN/MX
___ l Bus (input):
AD7 RD ___ ____ (in,out) 1 = minmode
Time-multiplexed
AD6 8086 HOLD (RQ/GT0)
___ ____ (8086 generates
Address
AD5 HLDA
___ (RQ/GT1)
______ all the needed
(outputs)/ Data
AD4 WR__ (LOCK)
__ control signals
Bus (bidirectional)
AD3 M/IO__ (S2)
__ Status for a small
Hardware AD2 DT/R
____ (S1)
__ signals system),
interrupt AD1 DEN (S0) (outputs) 0 = maxmode
requests AD0 ALE
_____ (QS0) (8288 Bus
(inputs) NMI INTA
_____ (QS1) Controller
5-10 MHz, INTR TEST Interrupt expands the
(input) CLK READY acknowledge status signals to
GND 20 21 RESET (output) generate more
ELECTRICAL ELECTRONICS COMMUNICATION control signals)
INSTRUMENTATION
• All computer systems have three buses:
– an address bus that provides memory and I/O with the
memory address or the I/O port number
– a data bus that transfers data between the microprocessor and
the memory and I/O
– a control bus that provides control signals to
the memory and I/O
• These buses must be present in order to interface to memory and
I/O.

Demultiplexing the Buses
• The address/data bus of the 8086/8088 is multiplexed (shared)

to reduce the number of pins required for the integrated circuit
– the hardware designer must extract or demultiplex

information from these pins



M/IO’ RD’ WR’ FUNCTION

1 0 1 MEMR’
1 1 0 MEMW’
0 0 1 IOR’
0 1 o IOW’




Bus Cycle
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Machine Cycle
• MEMR - (opcode/ data)

• MEMW -- ( data)
• IOR
• IOW
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Bus Cycle
• MOV AX, BX
• 8B C3
• 1 MEMR (OPCODE FETCH)
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Bus Cycle
• ADD BX, [0110]

• 03 1E 10 01
• 2 MEMR (OPCODE FETCH + MEMR)
• i.e. 2 Machine cycles
• To execute the instruction
• 1 Machine cycle---- Read Data from DS:0110
–(1 MEMR)
• 3 Machine Cycles
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Bus Cycle
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Bus Cycle
• ADD [0110], BX
• 01 1E 10 01
• To instruction fetch:
• 2 MEMR (OPCODE FETCH + MEMR)
• 2 Machine cycle
• To execute the Instruction
• 1 Machine cycle---- Read Data from DS:0110
–(1 MEMR)
• 1 Machine cycle---- Store Results in DS:0110
–(1 MEMW)
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Bus Cycle
• CBW
• 98
• 1 MEMR (OPCODE FETCH)
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Bus Cycle
• ADD AX, [BX]

• 03 07
• To Fetch instruction:
• 1 MEMR (OPCODE FETCH )
• 1 Machine cycle
• To execute the Instruction
• 1 Machine cycle---- Read Data from DS:[BX]
–(1 MEMR)
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TIMING DIAGRAM
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TIMING DIAGRAM
Each cycle equals four system-clocking periods (T states).
If the clock is operated at 5 MHz, one 8086/8088 bus cycle is

complete in 800 ns.
During the first clocking period in a bus cycle, called T1:
• the address of the memory or I/O location is sent out via

the address bus
• During TI, control signals are also output.
• indicating whether the address bus contains a memory

address or an I/O device (port) number
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TIMING DIAGRAM
• During T2, the processors issue the RD or WR signal, DEN.
• READY is sampled at the end of T2.

• if low at this time, T3 becomes a wait state (Tw)
• If a read bus cycle, the data bus is sampled at the end of T3.
• In T4, all bus signals are deactivated in preparation for the

next bus cycle
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TIMING DIAGRAM
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BUS TIMING
for READ OPERATION
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BUS TIMING
for WRITE OPERATION
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MEMORY ACCESS TIME
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MEMORY ACCESS TIME
• Memory access time starts when the address appears on the

memory address bus and continues until the microprocessor
samples the memory data at T3.
• About three T states elapse between these times
• The address does not appear until TCLAV time (time from
clock low to address valid) (110 ns if a 5 MHz clock) after
the start of T1.
• TCLAV time must be subtracted from the three clocking

states (600 ns) separating the appearance of the address (T1)
and the sampling of the data (T3).
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MEMORY ACCESS TIME
• The data setup time TDVCL (Time for data must be valid
before clock goes low) , which occurs before T3 must also
be subtracted.
• Memory access time is thus three clocking states minus

the sum of TCLAV and TDVCL.
• Because TDVCL is 30 ns with a 5 MHz clock, the allowed

memory access time is only 460 ns (access time = 600
ns –110 ns – 30 ns).
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MEMORY ACCESS TIME
• Memory devices chosen for connection to the
8086/8088 operating at 5 MHz must be able to access
data in less than 460 ns.
• Because of the time delay introduced by the address

decoders and buffers in the system a 30- or 40-ns
margin should exist for the operation of these circuits
• The memory speed should be no slower than about 420

ns to operate correctly with the 8086/8088
microprocessors.
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READY AND WAIT STATE
• The READY input causes wait states for slower memory
and I/O components.
• A wait state (Tw) is an extra clocking period between T2

and T3 to lengthen bus cycle .
• On one wait state, memory access time of 460 ns, is

lengthened by one clocking period (200 ns) to 660 ns,
based on a 5 MHz clock.
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READY AND WAIT STATE
• This section covers READY synchronization circuitry

inside the 8284A clock generator.
• If READY is logic 0 at the end of T2, T3 is delayed and Tw

inserted between T2 and T3.
• READY is next sampled at the middle of Tw

to determine if the next state is Tw or T3.
3/12/2016 75

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Topic-V

8086 Pin Out and modes of

March 3rd –12th 2016

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

• 8086 can operates in single processor (Minimum mode) or

Minimum Mode Maximum Mode

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

• 8086 & 8088 both are packaged in 40-pin dual in-line

• 8086 is a 16-bit microprocessor with a 16-bit data bus; 8088

• Data bus width is the only major difference.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

• Signal having common functions (in minimum as well as

• Signal having special functions for minimum mode.

• Signal having special functions for maximum mode.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

• Signal having common functions (in minimum as well as in

• Pin Connections AD7 - AD0

8088 address/data bus lines are multiplexed

These pins are at their high-impedance state during a hold

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Pin Connections AD15 – AD8

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Address/status bus bits are multiplexed to provide address signals

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

• The state of S7 is always a logic 1.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Pin Connections Ready

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

– If INTR is held high when IF = 1, 8086/8088

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

• If TEST is a logic 0, the WAIT instruction functions as an NOP,

• If TEST is a logic 1, processor remains in idle state.

• The TEST pin is most often connected to

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

• Minimum/maximum mode pin selects either minimum or

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

• Minimum mode operation is obtained by connecting the MN/MX

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

S2, S1, and S0

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

S2, S1, and S0

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

RQ/GT1 & RQ/GT0 (higher priority)

• The request/grant pins request direct memory accesses (DMA)

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

QS1 QS0 FUNCTION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

• CLK is crystal controlled clock sent to 8086 from an external

• One cycle of this clock is called a T state.

• A state is measured as falling edge of one clock pulse to falling

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

• 8284A provides the following basic functions:

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Different versions of 8086 have maximum clock frequencies of