signal b00: std_logic_vector(9 downto 0):= "0000000000";
signal b01: std_logic_vector(9 downto 0):= "1111111111";
signal b02: std_logic_vector(9 downto 0):= "1000100000"; signal b03: std_logic_vector(9 downto 0):= "1000010001"; signal b04: std_logic_vector(9 downto 0):= "0100000010"; signal b05: std_logic_vector(9 downto 0):= "1000000001"; signal b06: std_logic_vector(9 downto 0):= "0000100000"; signal b07: std_logic_vector(9 downto 0):= "1000011111"; signal b08: std_logic_vector(9 downto 0):= "1000000000"; signal b09: std_logic_vector(9 downto 0):= "0000000001"; signal b10: std_logic_vector(9 downto 0):= "0100000000";
signal b11: std_logic_vector(9 downto 0):= "0001001000";
signal b12: std_logic_vector(9 downto 0):= "0010000100"; signal b13: std_logic_vector(9 downto 0):= "0100000010"; signal b14: std_logic_vector(9 downto 0):= "0011100000"; signal b15: std_logic_vector(9 downto 0):= "0000111000"; signal b16: std_logic_vector(9 downto 0):= "0000001110"; signal b17: std_logic_vector(9 downto 0):= "1000111000"; signal b18: std_logic_vector(9 downto 0):= "1000001110"; signal b19: std_logic_vector(9 downto 0):= "1111110000"; signal b20: std_logic_vector(9 downto 0):= "1000000011";
signal b21: std_logic_vector(9 downto 0):= "1000000101";
signal b22: std_logic_vector(9 downto 0):= "1000011000"; signal b23: std_logic_vector(9 downto 0):= "1000010100"; signal b24: std_logic_vector(9 downto 0):= "1000010010"; signal b25: std_logic_vector(9 downto 0):= "0111100001"; signal b26: std_logic_vector(9 downto 0):= "1111111110"; signal b27: std_logic_vector(9 downto 0):= "1111111100"; signal b28: std_logic_vector(9 downto 0):= "0000000010"; signal b29: std_logic_vector(9 downto 0):= "0000011110"; signal b30: std_logic_vector(9 downto 0):= "1111000000";
signal b31: std_logic_vector(9 downto 0):= "0000001111";
signal b32: std_logic_vector(9 downto 0):= "1000001111"; signal b33: std_logic_vector(9 downto 0):= "1001110001"; signal b34: std_logic_vector(9 downto 0):= "1011100000"; signal b35: std_logic_vector(9 downto 0):= "1111111001"; signal b36: std_logic_vector(9 downto 0):= "1001111111"; signal b37: std_logic_vector(9 downto 0):= "1000011101"; signal b38: std_logic_vector(9 downto 0):= "1011100001"; signal b39: std_logic_vector(9 downto 0):= "0000000010"; signal b40: std_logic_vector(9 downto 0):= "1100000000";
signal b41: std_logic_vector(9 downto 0):= "0111101110";
signal b42: std_logic_vector(9 downto 0):= "0111111110"; signal b43: std_logic_vector(9 downto 0):= "0010000000"; signal b44: std_logic_vector(9 downto 0):= "0111100010"; signal b45: std_logic_vector(9 downto 0):= "0100001110"; signal b46: std_logic_vector(9 downto 0):= "1100000011"; signal b47: std_logic_vector(9 downto 0):= "0011001100"; signal b48: std_logic_vector(9 downto 0):= "0000110000"; signal b49: std_logic_vector(9 downto 0):= "1100000000"; signal b50: std_logic_vector(9 downto 0):= "0011000000"; signal b51: std_logic_vector(9 downto 0):= "0000111111";
signal b52: std_logic_vector(9 downto 0):= "0010000001";
signal b53: std_logic_vector(9 downto 0):= "0100000001"; signal b54: std_logic_vector(9 downto 0):= "1111110001"; signal b55: std_logic_vector(9 downto 0):= "1000001110";
type memory is array (INTEGER range <>) of std_logic_vector (9
downto 0);
signal H : memory (0 to 5):= (b01, b06, b06, b06, b01, b00);
signal O : memory (0 to 5):= (b42, b05, b05, b05, b42, b00); signal L : memory (0 to 5):= (b01, b09, b09, b09, b09, b00); signal A : memory (0 to 5):= (b01, b02, b02, b02, b01, b00);