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USE IEEE.STD_LOGIC_1164.ALL;
ENTITY modul4 IS
PORT ( CLK ,d, s : IN STD_LOGIC;
M_US : OUT STD_LOGIC;
M_BT : OUT STD_LOGIC;
K_US : OUT STD_LOGIC;
K_BT : OUT STD_LOGIC;
H_US : OUT STD_LOGIC;
H_BT : OUT STD_LOGIC
);
END modul4;
PROCESS (d,CLK,s)
variable C : integer := 1;
BEGIN
IF CLK'EVENT AND CLK='1' AND d = '1' THEN
IF (C = 1) THEN
M_US <= '0';
K_US <= '1';
H_US <= '0';
M_BT <= '0';
K_BT <= '1';
H_BT <= '0';
C := C + 1;
[50] C := C + 1;
[51] ELSIF (C=4) THEN
[52] M_US <= '0';
[53] K_US <= '0';
[54] H_US <= '0';
[55] M_BT <= '0';
[56] K_BT <= '0';
[57] H_BT <= '0';
[58] C := 1;
[59]
ELSIF C>4 and d = '1' then
[60] C := 0;
[61] else
[62] currentstate <= S1;
[63]
[64] END IF;
[65]
ELSIF CLK'EVENT AND CLK='1' AND s ='1' AND d = '0' THEN
[66] CASE currentstate IS
[67]
WHEN S1 =>
[68]
IF (C<8) THEN
[69] M_US <= '1';
[70]
K_US <= '0';
[71]
H_US <= '0';
[72]
M_BT <= '0';
[73]
K_BT <= '0';
[74]
H_BT <= '1';
[75] C := C + 1;
[76] currentstate <= S1;
[77]
ELSE
[78]
currentstate <= S2;
[91] ELSE
[92] currentstate <= S3;
[93] C := 1;
[94] END IF;
[95] WHEN S3 =>
[96] IF (C<8) THEN
[97] M_US <= '0';
[98]
K_US <= '0';
[99] H_US <= '1';
[100] M_BT <= '1';
[101] K_BT <= '0';
[102] H_BT <= '0';
[103] C := C + 1;
[104] currentstate <= S3;
[105]
ELSE
[106] currentstate <= S4;
[107] C := 1;
[108]
END IF;
[109] WHEN S4 =>
[110]
IF (C<2) THEN
[111] M_US <= '0';
[112]
K_US <= '1';
[113]
H_US <= '0';
[114]
M_BT <= '1';
[115]
K_BT <= '0';
[116] H_BT <= '0';
[117] C := C + 1;
[163] ELSE
[164] currentstate <= S4;
[165] C := 1;
[166] END IF;
[167] WHEN S4 =>
[168] IF (C=1) THEN
[169] M_US <= '0';
[170] K_US <= '1';
[171] H_US <= '0';
[172] M_BT <= '1';
[173] K_BT <= '0';
[174] H_BT <= '0';
[175]
C := C + 1;
[176] currentstate <= S1;
[177] C := 1;
[178]
END IF;
[179]
[180]
END CASE;
[181]
[182]
END IF;
[183]
END PROCESS;
END behavioral;