Digital Systems Design

Digital Systems Design and Test

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 1-1

Introduction

• Traditional digital design

– Manual process of designing and capturing circuits
• Schematic entry
• System-level design
– Top-down design
• Required due to design complexity
• Rapid time-to-market requirements
– Hardware Description Language (HDL) use
• Synthesis – Use a “hardware compiler” to implement a design
• Applicable to different digital “product” types
– ASIC, CPLD, FPGA, etc.

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 1-2

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 Top-down HDL Design Methodology

• Increased productivity
– Shorter development cycle
– More product features
– Reduced time-to-market
• Reduced non-recurring engineering (NRE) costs
• Design reuse facilitated
• Flexibility in design changes
• Rapidly explore alternatives
– Architectures
– Implementation technologies

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 1-3

Other Design Methodology

Considerations
• Bottom-up design
– Design simple components
– Test desired functionality
– Integrate into larger designs
– Questions/Concerns?
• How are software versus hardware distinctions
made?
– Hardware and software designed concurrently
• Hardware/software codesign
– Hardware/software codesign can coexist with a top-down
or bottom-up design methodology

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 1-4

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 ASIC, FPGA and SoC Devices

• Standard off-the-shelf integrated circuits have fixed

functionality defined by the chip manufacturer
• ASIC and FPGA
– ASIC functionality fixed by the designer for a particular application
– FPGA is “field” programmable by the designer
• Structured ASICs
– Some lower levels of the device are prefabricated
– Upper levels are based on a given (user) design
• Mix between ASIC and FPGA
• System-On-Chip (SoC) devices are typically a combination
of some programmable fabric (FPGA) and a processor (ARM
architecture is very popular)
– Altera Cyclone V SoC is one example
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 1-5

FPGA

• The field-programmable gate array (FPGA) is

completely manufactured by the IC vendor
– The device is design independent
• Each manufacturer has their own proprietary
architecture for their devices that includes
– Programmable blocks connected to
– Programmable switch matrices
• A device is configured to implement a particular
design by programming the switch matrices to route
signals between programmable logic blocks

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 1-6

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 Basic FPGA Device Structure

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 1-7

ASIC versus FPGA

• ASIC devices have an initial NRE cost

– After the initial cost, the per unit cost can be low
• FPGA devices typically have a higher unit cost than ASIC
devices
• If production volume is low then FPGA is probably the
implementation choice
• For high volume devices, ASICs are more cost effective
• For the same design, ASICs will generally hold a
performance advantage over FPGAs
• Alternately – FPGA may be used in prototyping and ASIC
used in high volume production

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 1-8

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 Top-down Design Methodology

System

Algorithm

Increasing Increasing
behavioral Architecture detail and
abstraction complexity
RTL

Gate

Transistor

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 1-9

Example Design Flow

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 1-10

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 Design Domains

Behavioral Design Model Domain

level of
abstraction Abstract Structural Physical
Architecture synthesis
System
Architectural
Design RTL synthesis
Algorithm
Structural
Design Logic synthesis
RTL verification Logic
Design
Logic
verification Layout
Design
Gate
verification

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 1-11

Electronic Design Automation Tools

• An EDA system usually includes the following tools

– Design entry
– Synthesis and optimization
– Simulation
– Physical design

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 1-12

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 Design entry

• The process of entering into the CAD system a

description of a circuit being designed is called
design entry
• Common design entry methods
– Schematic capture
• User graphically enters a desired logic circuit
– Hardware description languages
• User enters a programming language-like description of a desired
logic circuit

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 1-13

Schematic capture

• Schematic: refers to a diagram of a circuit in which

circuit elements (logic gates) are shown as
graphical symbols and connections between them
are drawn as lines
• Tool provides a collection of symbols that represent
gates of various types with different inputs and
outputs. A library.
• Previously designed circuits can be represented
with a graphical symbol and used in larger circuits.
– Known as hierarchical design and provides a way of
dealing with complexities of large circuits
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 1-14

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 Hierarchical Design

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 1-15

Hardware description languages

• A hardware description language (HDL) is, on the

surface, similar to a computer program except that it
is used to describe hardware
• Common HDLs
– VHDL (VHSIC Hardware Description Language)
– Verilog
– Many others (vendor specific)
• VHDL and Verilog are standards
– Offer the option for portability across different CAD tools
and different types of programmable chips

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 1-16

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 Synthesis

• Synthesis CAD tools perform the process of generating a

logic circuit from some stated functional behavior
• Translating (compiling) VHDL code into a network of logic
gates is a part of synthesis
• Not only will the CAD tool produce a logic circuit, but it can
also optimize that circuit
– In terms of speed and/or size (logic optimization)
– Called logic synthesis or logic optimization
• Finally, technology mapping and layout synthesis
(physical design) complete the synthesis process

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 1-17

Simulation

• Once designed, it is necessary to verify that the design

circuit functions as expected
• In a functional simulation the user specifies valuations of
the circuits inputs and the CAD tool generates the outputs
(commonly in the form of a timing diagram)
– User verifies generated outputs against expected outputs
• Functional simulators assume the time needed for signals to
propagate through the logic gates is negligible
– Sometimes called zero-delay simulators
– For a real implementation this is not sufficient
– Use a timing simulator, or other timing analysis tool, to obtain
accurate (complete) simulation

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 1-18