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International Journal of Electronics / International Journal of Electronics Letters

Accurate Calculation of Unreliability of CMOS Logic Cells and


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Circuits

Journal: International Journal of Electronics


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Manuscript ID TETN-2019-0351

Manuscript Type: International Journal of Electronics (2501-4500 word limit)


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Date Submitted by the


04-Apr-2019
Author:
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Complete List of Authors: Beg, Azam; UAE University, College of Information Technology

Keywords: Integrated circuits, CAD, Logic, Semiconductors, Circuit synthesis


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Note: The following files were submitted by the author for peer review, but cannot be converted to PDF.
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2019_04_05_reliability_IJE_R1.tex
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April 4, 2019 International Journal of Electronics 2019˙04˙05˙reliability˙IJE˙R1
Page 1 of 20 International Journal of Electronics / International Journal of Electronics Letters

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3 To appear in the International Journal of Electronics
4 Vol. 00, No. 00, Month 20XX, 1–20
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13 Accurate Calculation of Unreliability
14 of CMOS Logic Cells and Circuits
15
16 Azam Beg∗
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18 College of Information Technology, United Arab Emirates University, Al-Ain, UAE
19 (v0.0 released Month 201x)
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Modern decananometer-sized MOS transistors tend to exhibit high rates of failure, underscoring
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the need for accurately estimating the unreliabilities of circuits built from such transistors. This
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paper presents a methodology for unreliability calculation that extends from individual transistors
24 to complete logic circuits. As a logic cell’s or logic circuit’s unreliability is highly dependent on
25 its transistors’ drain-source and gate-source voltages, SPICE simulations are used to determine
26 the voltages for the individual transistors. The voltage measurements are then utilized by the
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mathematical equations to predict the unreliabilities with high accuracy. A scalable framework
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based on the proposed methodology has been successfully implemented. The framework has been
28 validated using ISCAS85 benchmark circuits.
29
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30 Keywords: Circuit simulation, CMOS integrated circuits, CMOS technology, Design


31 optimization, Digital circuits, Digital simulation, Failure analysis, Fault tolerance, Logic gates,
32 Logic circuits, Mathematical models, MOS integrated circuits, Probability, Reliability,
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Robustness, Semiconductor device reliability, Very large scale integration


33
34
35
36 Acronyms
37
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38 BN Bayesian network
39 CAD Computer-aided design
40 CMOS Complementary metal oxide semiconductor
41 DIBL Drain-induced barrier lowering
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42 EDA Electronic design automation


43 FDSOI Fully-depleted silicon on insulator
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FinFET Fin field effect transistor
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46
MOS Metal oxide semiconductor
47 NAND Logic gate implementing inverted AND
48 nMOS N-type metal oxide semiconductor
49 NOR Logic gate implementing inverted OR
50 pMOS P-type metal oxide semiconductor
51 PDF Probability density function
52 RAM Random access memory
53 SRAM Static random access memory
54 XOR Logic gate implementing exclusive OR
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57 ∗ Corresponding author. Email: abeg@uaeu.ac.ae
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60 URL: http:/mc.manuscriptcentral.com/intjelectron Email: ijeditor@leeds.ac.uk
April 4, 2019 International Journal of Electronics 2019˙04˙05˙reliability˙IJE˙R1
International Journal of Electronics / International Journal of Electronics Letters Page 2 of 20

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5 Notations
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7 µVth Average of Vth variations
8 σVth Standard deviation of Vth variations
9 τd Time delay
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Υtr Unreliability
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CL Load capacitance
13 f Frequency
14 ID Drain current
15 L Channel length
16 Leff Effective channel length
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17 Ndep Channel doping concentration at depletion edge
18 tox Oxide thickness
19 VDD Supply voltage
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20 VGS Gate-source voltage
21 Vth Threshold voltage
22 W Channel width
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Weff Effective channel width


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27 1. Introduction
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29 The sizes of MOS transistors have continued to decrease continuously for nearly four
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30 decades now. Recently, the transistor dimensions have approached 10 nm. The scaling
31 down of a transistor’s channel length (L) is accompanied by the reductions in oxide thick-
32 ness (Tox ), doping concentrations, and the depths of source and drain junctions. The sup-
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33 ply voltage (VDD ) has also been lowered. As L dropped, the transport time for the carri-
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ers from the drain to the source also reduced while increasing the drain current (ID ) in
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the on-state (ION ). Therefore an increase in performance is witnessed, i.e., 1/τd , where
37 τd ≈ CL VDD /ION , and CL is the load capacitance. On the downside, thinner Tox has re-
sulted in increased off-current (IOFF ). The energy barrier for the carriers in the channel
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39 is now controlled not just by gate-source voltage (VGS ) but also by drain-source voltage
40 (VDS ) – an effect known as drain-induced barrier lowering (DIBL) [Rabaey, Chandrakasan,
41 and Nikolic (2004)].
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42 Multiple factors that have caused modern MOS transistors to operate unreliably, include:
43 (a) hot carrier injection, i.e., charge carriers getting trapped in a transistor’s gate [Hu et
44 al. (1985)]; (b) negative-bias temperature instability which increases threshold voltage
45 (Vth ) and decreases ID and transconductance [Schroder and Babcock (2003)]; (c) time-
46 dependent dielectric breakdown due to low electric field application for a long time-period
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[McPherson (2012)]; and (d) radiation-inflicted damage [Simoen et al. (2013)]. These phe-
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nomena manifest into temporal variations of ID , Vth , sub-Vth swing, low-frequency (1/f )
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50 noise [Kirton and Uren (1989)] and trap-assisted tunneling [Ghetti et al. (2000)]. Addition-
51 ally, performance degradation in an unreliable transistor can be observed as hysteresis in
52 the ID -VGS plots.
53 Redundancy is the most prevalent technique for reducing a system’s or a circuit’s unre-
54 liability. The common types of redundancy include space, time, and information [Moore
55 and Shannon (1956); von Neumann (1952); Winograd and Cowan (1963)]. Digital circuits
56 can utilize low or high-level redundancy, von Neumann multiplexing [Bhaduri, Shukla,
57 Graham, and Gokhale (2005)], or parallel restitution [Sadek, Nikoli, and Forshaw (2003)].
58 Obviously, circuit redundancy is costly in terms of area and power consumption. In com-
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5 parison, time-redundancy is a lower-cost option and is effective in finding and rectifying
6 most transient faults and some permanent faults. Information redundancy utilizes coding
7 and corrects the errors that occur during transmission and retrieval, albeit at the cost of
8 additional hardware [Dubrova (2013)]. Markov Random Field, an alternative solution to
9 the redundancy, offers higher reliability, better error-handling and lower area cost [Anwer,
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Shaukat, Khalid, and Hamid (2012)].
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1.1. Finding Unreliability
15 A logic gate (or a logic cell) may fail due to an external factor such as crosstalk, radiation
16 or thermal noise [Krishnaswamy, Plaza, Markov, and Hayes (2009)] or due to a factor
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17 internal to the gate [Chen and Mao (2008)]. The gate’s malfunction could also be due to
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the failure(s) of one or more of its inputs. Using a Von Neumann model for gate errors,
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a gate can independently exhibit an output flip (1 → 0 or 0 → 1) with equal probability
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21 (named Von Neumann error) [J. von Neumann (1956)].
22 It is highly desirable to accurately estimate the unreliabilities of transistors and gates in
23 order the find the unreliability of complete circuits. Monte Carlo simulations are one way of
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24 estimating the unreliability, however, the simulations carry a hefty time cost. Alternatively,
25 mathematical models, which can be several orders of magnitude faster than the simulations,
26 are used. The unreliability of a circuit Υcirc can be estimated by these equations [Nikolic,
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27 Sadek, and Forshaw (2001)]:


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29 Υgate = 1 − (1 − Υtr )n (1)
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30
γ
31 Υcirc = 1 − (1 − Υgate ) (2)
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33 where the circuit contains γ gates, each gate contains n transistors, the unreliability of the
34 transistors in the gates is denoted by Υtr , and the unreliability of the gates in the circuit
35 by Υgate . Eqs. 1 and 2 assume that all transistors have the same Υ and all gates have the
36 same number of transistors. One way of improving the equations would be to consider: (a)
37 transistor-counts ni of N different types/sizes and their respective unreliabilities Υntr,i
i
, and
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38 γj
(b) gate-counts γj of G different types and their respective unreliabilities Υgate,j . There-
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40 fore, the improved equations would be:
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N −1
42 Y
43 Υgate,i = 1 − (1 − Υtr,i )ni (3)
44 i=0
45 G−1
Y
46 Υcirc = 1 − (1 − Υgate,j )γj (4)
47 j=0
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49 Even Eqs. 3 and 4 have some drawbacks, which significantly affect the individual
50 Υgate,i ’s and hence the Υcirc . Specifically, the equations ignore the effects of input and
51 gate voltage levels, gates’ own topologies, and overall circuit’s configuration.
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54 1.2. About This Paper
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56 This paper introduces an comprehensive methodology for the accurate determination of the
57 Υgate ’s and Υcirc ’s. This improved methodology, which relies on a hybrid of mathematical
58 equations and simulations, considers:
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International Journal of Electronics / International Journal of Electronics Letters Page 4 of 20

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5 (1) Υ of every transistor, as determined by its physical dimensions, drain-source voltage
6 (VDS ), and gate-source voltage (VGS ),
7 (2) Υ of every gate, as determined by its topology (transistor count and connections)
8 and input voltages (noise margins and logic values), and
9 (3) circuit’s overall topology (gate count and connections), input voltages and input Υ’s.
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11 Section 2 presents literature review. Section 3 covers how individual transistor-Υ’s are
12 used to determine the Υ’s of combinations of transistors. Section 4 demonstrates how
13 transistor-Υ’s are utilized to calculate logic cell-Υ’s. Section 5 details the derivation of
14 logic circuit-Υ’s using logic cell-Υ’s. Section 6 discusses the algorithm and the framework
15 for the proposed methodology. Section 7 presents the results of the experiments performed
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on individual logic cells and different benchmark circuits. Lastly, Section 8 concludes the
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paper.
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2. Literature Review
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24 Over the years, many articles have covered the topics of reliability tools and methods, such
25 as Gielen et al. (2008); Jeng, Lu, and Wang (2007); Xiao and Chen (2014). Some pertinent
26 works related to MOS transistors, logic gates/cells and logic circuits are given below.
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27 An early study of the effects of variations in MOS transistor doping was conducted by
28 Keyes (1994). This was followed by the presentation of a dopant variation model by Stolk,
29 Widdershoven, and Klaassen (1998). In recent years, Asenov, Amoroso, and Gerrer (2014);
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30 Asenov et al. (2015) performed extensive simulations to look into the influence of quantum
31 mechanical effects on Vth -variations in MOS transistors.
32 An investigation into the effect of variations in transistor dimensions and Ndep in an
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33 inverter, was done by Khalid, Mastrandrea, and Olivieri (2014c). Analytical and semi-
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analytical methods were used for finding an inverter’s ‘safe areas of operation’ while being
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subjected to input voltage and Vth variations in Khalid, Mastrandrea, and Olivieri (2014b).
37 The estimation of failures due to single-event upsets by done by Khalid, Mastrandrea, Ab-
bas, and Olivieri (2015). Huard et al. (2010) proposed a reliability-driven workflow for
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39 designing SRAM cells; the workflow considered the effects of degradation and ageing.
40 Later, Esqueda and Barnaby (2013) proposed a defect-based transistor model and used it
41 to study the aging effects in SRAM cells. Modeling of statistical variations and aging of a
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42 6-T RAM cell was done by Hussin et al. (2015). The influences of aging and process varia-
43 tions on flip-flops were investigated by Khalid, Mastrandrea, and Olivieri (2014a). The use
44 of static noise margin as a representation of reliability of different logic cells was done by
45 Beg (2014). Recently, mathematical equations have been utilized for calculating the failure
46 rates of simple logic cells by Beg (2016).
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A few tools and techniques addressing the reliability of complete logic circuits include:
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Symbolic Hierarchical Automated Reliability and Performance Evaluator [Sahner and
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50 Trivedi (1987)], Probabilistic Symbolic Model Checker [Kwiatkowska, Norman, Parker,
51 and Segala (1999)], probabilistic transfer matrices [Patel, Hayes, and Markov (2003)],
52 Proxel-based method [Lazarova-Molnar (2005)], probabilistic gate models [Jie Han et al.
53 (2005)], and Bayesian networks (BNs) [Rejimon and Bhanja (2005)]. A BN-based tool
54 helped investigate the relationship of reliability and circuit-topology [Beg and Ibrahim
55 (2009); Ibrahim, Beg, and Amer (2008)]. The effect of input vectors on circuit reliability
56 was covered by Ibrahim, Shousha, and Chinneck (2015).
57 It is important to note that although the actual voltages for transistors significantly affect
58 the gate/cell and circuit reliabilities, none of the aforementioned works incorporates the
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April 4, 2019 International Journal of Electronics 2019˙04˙05˙reliability˙IJE˙R1
Page 5 of 20 International Journal of Electronics / International Journal of Electronics Letters

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5 voltages in reliability calculations. In order to address this significant shortcoming, our pa-
6 per presents a time-efficient, mathematical-cum-simulation-based approach for accurately
7 calculating the Υ’s of not just the individual transistors and gates, but also for complete
8 logic circuits (see Table 1 for feature comparison).
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3. Unreliability of Transistors
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14 A MOS transistor’s probabilistic behavior is determined by (a) the type (nMOS or pMOS),
15 (b) the dimensions (width W and channel length L), and (c) the gate voltage [Gupta,
16 Kahng, Sharma, and Sylvester (2006)]. The lack of uniformity in the doping level of a
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17 transistor causes its Vth to vary. σVth can be estimated by [Asenov, Brown, Davies, Kaya,
18 and Slavcheva (2003)]:
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20 0.4
tox Ndep
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21 σVth ≈ 3.19 × 10 p , (5)
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Leff Weff
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24 where Leff and Weff are the effective channel length and width, respectively. Ndep is the
25 channel doping concentration at depletion edge for zero body bias. (Eq. 5 was based on
26 the atomistic simulations of transistors having: Leff = 30 nm to 100 nm, Weff = 50 nm to
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27 500 nm, Ndep = 1 × 1018 cm−3 to 5 × 1018 cm−3 , and tox = 1 nm to 6 nm [Asenov et al.
28 (2003)].
29 In this work, the switching probability of failure of a MOS transistor represents Υ, and
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30 as is defined as a probability density function (PDF). The Υ/PDF depends not only on its
31 µVth and σVth but also on the level of the input voltage [Beiu, Beg, Ibrahim, Kharbash, and
32 Alioto (2013)]:
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34 exp −(VGS − Vth )2 /2σV2 th )
 
35 Υ = PDF (VGS ) = √ (6)
36 σV th 2π
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It is to be noted that Eqs. 5 and 6 address only the VGS , sizing and manufacturing-related
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39 properties of transistors (Ndep and tox ), and not the degradation or any other temporal
40 effects – hence the latter two are outside the scope of this work.
41 Consider n transistors that have their Υ’s specified by Υtr,i . If the transistors are con-
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42 nected in series, the overall Υ would be [Dubrova (2013)]:


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44 n−1
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45 Υseries = 1 − (1 − Υtr,i ), (7)
46 i=0
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48 and if the transistors are connected in parallel, their combined Υ would be [Dubrova
49 (2013)]:
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51 n−1
Y
52 Υparallel = Υtr,i . (8)
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55 Stated simply, Eq. 7 implies that the transistors when placed in series have worse over-
56 all Υ than their individual Υ’s, which in turn are driven by their respective input (gate)
57 voltages. Similarly, from Eq. 8, we see that a parallel combination of transistors exhibits
58 improved Υ depending on the individual transistors’ Υ’s. For series or parallel transistors,
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April 4, 2019

Table 1. Comparison of different un/reliability evaluation methods.

Effect of Input noise


Input vectors
Methodology Space complexity Time complexity VDD consid- margin
considered
ered considered
International Journal of Electronics

Mathematical equations (Eqs. 1 and 2) [Nikolic et al.


O(1) O(1) No No No
(2001)]
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Gate-level reliability analysis [Xiao and Chen (2014)] O(N ) O(N · 2Nin +N ) Yes Yes Yes
Monte Carlo simulations [Xiao and Chen (2014)] O(N ) O(N · NMC ) Yes Yes Yes
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Probabilistic model checking [Mohyuddin, Pakbaznia,
O(2Nin +Nout ) O(N · 2Nin +N ) No No No
and Pedram (2008)]
2019˙04˙05˙reliability˙IJE˙R1

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Probability transfer matrix [Beg (2012)] O(2Nin +Nout ) O(N ) No No Yes
Probabilistic gate model [Xiao and Chen (2014)] O(2Nin +Nout ) O(N · 2Nin +N ) No No Yes
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Stochastic computation model [Han et al. (2014)] O(N · NSCM ) O(N · NSCM ) No No No
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Bayesian networks [Ibrahim et al. (2015)] Unknown Unknown No No Yes
This work O(N ) O(N · log(N )) Yes Yes Yes
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Note that:
N is the number of gates.
Nin is the number of circuit inputs. (PTMs’ severe limitation is Nin < 50, due to space complexity).
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Nout is the number of circuit outputs.
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Required Monte Carlo simulations NMC ≈ (1/RC − 1) × 10−6 , where RC is relative error of reliability.

URL: http:/mc.manuscriptcentral.com/intjelectron Email: ijeditor@leeds.ac.uk


International Journal of Electronics / International Journal of Electronics Letters

NSCM is the same as NMC .


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(a) (b)
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Figure 1. The schematics for gates: (a) NOR2 and (b) XOR2.
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the effects of input vectors (gate voltages) are accounted for in Υ-calculation (see Eq. 6).
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As an example, a NOR2 gate with an input vector of ‘01’ would exhibit a different Υ than
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28 with an input vector of ‘11’.
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31 4. Unreliability of Logic Cells
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33 In a CMOS gate or cell, the set of pMOS transistors is commonly referred to as a P-stack
34 and the set of nMOS transistors as an N-stack. To simplify the Υ-modeling process, the
35 equations for the two stacks are found separately, and then the cells’ overall Υ is found
36 [Beg (2016)].
37 In a NOR2 gate (Figure 1a), the pMOS transistors are in series and nMOS transistors in
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38 parallel. By using eqs. 7 and 8, one can find the Υ’s for the P-stack (Υsp ) and the N-stack
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(Υsn ):
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Υsp = 1 − (1 − Υp1 ) × (1 − Υp2 )
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42 (9)
43 Υsn = Υn1 × Υn2 (10)
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45 A gate’s overall Υ is then represented by:
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Υgate = 1 − (1 − Υsp ) × (1 − Υsn ) (11)
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50 An XOR2 gate (Figure 1b) is not as ‘symmetric’ as a NOR2 (or a NAND2) gate, be-
51 cause each stack in the former has both parallel and series combinations of transistors. By
52 considering the Υ’s of sets of parallel and series transistors, one gets:
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h i h i
Υsp = 1 −(1 − Υp1 )(1 − Υp2 ) × 1 −(1 − Υp3 )(1 − Υp4 ) (12)
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h i h i
Υsn = 1 −(1 − Υn1 )(1 − Υn2 ) × 1 −(1 − Υn3 )(1 − Υn4 ) (13)
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International Journal of Electronics / International Journal of Electronics Letters Page 8 of 20

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27 Figure 2. The schematic for a full-adder cell.


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32 Lastly, the presented methodology is applied to a full adder cell (see Figure 2). The Υ’s
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33 for the two P-stacks, one for Cout and the other for Sum, are derived separately:
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35 h i
36 Υsp1 = 1 − 1 − Υp1 Υp2 ×
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h i
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1 − 1 − (1 − Υp3 )(1 − Υp4 ) Υp5 (14)
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h i
Υsp2 = 1 − 1 − Υp6 Υp7 Υp8 ×
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42 h i
43 1 − Υp9 1 − (1 − Υp10 )(1 − Υp11 )(1 − Υp12 ) (15)
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46 The Υ’s for the two N-stacks, one for Cout and the other for Sum, are derived as follows:
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49 Υsn1 = 1 − (1 − Υn1 )(1 − Υn2 Υn3 ) ×
50  
51 1 − 1 − Υn4 )(1 − Υn5 ) (16)
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53 Υsn2 = 1 − (1 − Υn6 )(1 − Υn7 Υn8 Υn9 ) ×
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55 1 − (1 − Υn10 )(1 − Υn11 )(1 − Υn12 ) (17)
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58 The stack Υ’s are combined in order to find the Υ of the carry-out (Υcout ) and the sum
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5 (Υsum ) outputs, which in turn give the full circuit’s Υ:
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8 Υcout = 1 − (1 − Υsp1 )(1 − Υsn1 ) (18)
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10 Υsum0 = 1 − (1 − Υsp2 )(1 − Υsn2 ) (19)
11 Υsum = 1 − (1 − Υcout )(1 − Υsum0 ) (20)
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16 (as given by Eq. 6), would yield different values of Υser ’s and/or Υpar ’s for different input
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17 vectors. This implies that in order to find the worst-case Υ of a logic cell, one has to
18 consider all possible input combinations.
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5. Unreliability of Logic Circuits
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25 As it was pointed out earlier, one should take into account the gates’ individual Υ’s as well
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as the overall circuit’s topology, for finding the Υ of a logic circuit. Other factors, such
27 as the supply voltage and the input noise margin (maximum allowed voltage for logic-‘0’,
28 and minimum allowed voltage for logic-‘1’) should also be taken into account.
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Here, the process of circuit-Υ calculation is elucidated using the ISCAS85 c17 bench-
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mark circuit (Figure 3). Assume input-N 1 has ΥN 1 , input-N 2 has ΥN 2 , and so on. Also
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32 assume ΥNAND2 00 is NAND2’s Υ with input ‘00’, ΥNAND2 01 is Υ with input ‘01’, and
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33 so on. For a circuit with logic inputs ‘01010’, one can find the Υ’s for the circuit gates, as
34 following:
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37 ΥG1 out =1 − (1 − ΥN 1 ) × (1 − ΥN 3 ) × (1 − ΥNAND2 00 )
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= ΥN 1 + ΥN 3 + ΥNAND2 00
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40 − ΥN 1 × ΥN 3
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− ΥN 1 × ΥNAND2 00
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43 − ΥN 3 × ΥNAND2 00
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45 + ΥN 1 × ΥN 3 × ΥNAND2 00 (21)
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50 ΥG2 out =1 − (1 − ΥN 3 ) × (1 − ΥN 4 ) × (1 − ΥNAND2 01 )
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52 = ΥN 3 + ΥN 4 + ΥNAND2 01
53 − ΥN 3 × ΥN 4
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55 − ΥN 3 × ΥNAND2 01
56 − ΥN 4 × ΥNAND2 01
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58 + ΥN 3 × ΥN 4 × ΥNAND2 01 (22)
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International Journal of Electronics / International Journal of Electronics Letters Page 10 of 20

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5 ΥG3 out =1 − (1 − ΥN 2 ) × (1 − ΥG2 out ) × (1 − ΥNAND2 11 )
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8 − ΥN 2 × ΥG2 out
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10 − ΥN 2 × ΥNAND2 11
11 − ΥG2 out × ΥNAND2 11
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13 + ΥN 2 × ΥG2 out × ΥNAND2 11 (23)
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16 ΥG4 out =1 − (1 − ΥN 5 ) × (1 − ΥG2 out ) × (1 − ΥNAND2 10 )
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17
18 = ΥN 5 + ΥG2 out + ΥNAND2 10
19 − ΥN 5 × ΥG2 out
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20
21 − ΥN 5 × ΥNAND2 10
22
− ΥG2 out × ΥNAND2 10
23
ee

24 + ΥN 5 × ΥG2 out × ΥNAND2 10 (24)


25
26
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27 ΥG5 out =1 − (1 − ΥG3 out ) × (1 − ΥG4 out ) × (1 − ΥNAND2 01 )


28
29 = ΥG3 out + ΥG4 out + ΥNAND2 01
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30
− ΥG3 out × ΥG4 out
31
32 − ΥG3 out × ΥNAND2 01
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33
34 − ΥG4 out × ΥNAND2 01
35 + ΥG3 out × ΥG4 out × ΥNAND2 01 (25)
36
37
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38
ΥG6 out =1 − (1 − ΥG1 out ) × (1 − ΥG4 out ) × (1 − ΥNAND2 11 )
39
40 = ΥG1 out + ΥG4 out + ΥNAND2 11
41
− ΥG1 out × ΥG4 out
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42
43 − ΥG1 out × ΥNAND2 11
44
45 − ΥG4 out × ΥNAND2 11
46 + ΥG1 out × ΥG4 out × ΥNAND2 11 (26)
47
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50 6. Circuit Unreliability Algorithm and Framework
51
52 Our implementation of the framework for automatically finding any logic circuit’s Υ is
53 based on the algorithm given in Listing 1. The first module of the framework reads in
54 Verilog-based circuit descriptions and creates sets of corresponding SPICE netlists. Each
55 possible set of constant/DC input-voltages gets its own customized netlist. It is noteworthy
56 that the use of constant voltages ensures speedy SPICE simulations. Relevant commands
57 for measuring all net voltages are included in the netlists. The second module executes
58 SPICE simulations and saves the results to log files. The files are then parsed in order to
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60 URL: http:/mc.manuscriptcentral.com/intjelectron Email: ijeditor@leeds.ac.uk
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5 1 mark all gateUnRel’s as ’unknown’
6 2 assign input unRels to gates fed only by inputs
7 3

8 4 while any gate has unknown gate UnRel {


5
9 6 if (all netUnRels for a gate’s inputs >= 0) {
10 7 use gate’s input voltages and VDD to find gate’s transistors’ VDSs and VGSs (
11 use SPICE)
12 8

13 9 use gate’s transistors’ VDSs and VGSs to find all transistors’ unRel’s (use Eq
. 6)
14 10
15 11 use gate’s transistors’ UnRels and all the input netUnRel’s to find gate’s
16 UnRel (use Eqs. 7-8)
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17 12
assign gate’s UnRel to gate-output’s net (netUnRel)
18 13
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19 save gate’s output voltage
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20 16
21 17 remove the gate from the list of unknown gateUnRel’s
22 18 }
else {
23 19
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20 skip to next gate in the list


24 21 }
25 22 }
26
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23

27 24 return all netUnRels and gateUnRels


28 Listing 1 The algorithm for finding a logic circuit’s unreliability
29
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30
31
extract the values of net voltages for the transistors in different gate/cells (see Listing 1 and
32
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33
2); these voltages (along with transistor dimensions) to determine the transistor Υ’s. The
34 third module uses transistor Υ’s to calculate the gate/cell-Υ’s. The last module computes
35 the circuit’s Υ while considering its overall topology. The outputs of multi-output circuits
36 result in different Υ’s, the maximum of which represents the circuit’s worst-case Υ.
37 An additional advantage of our method is that it enables the studies of effects of
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38 VDD -variations, input/static noise margin and input vectors, on the unreliability; such ad-
39 vantages are only selectively offered by other methods, as shown in Table 1.
40 Furthermore, Table 1 includes the space and time-complexities of different methods.
41 Space complexity of our method is O(N ) driven only by gate count N , which is compa-
ly

42 rable to or significantly better than other methods. Our method’s time complexity depends
43 both on N and a search algorithm (‘merge sort’), therefore the complexity is O(N ·log(N ))
44
– a considerable improvement over most other methods.
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58 Figure 3. The schematic for ISCAS85 c17 benchmark circuit.
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60 URL: http:/mc.manuscriptcentral.com/intjelectron Email: ijeditor@leeds.ac.uk
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International Journal of Electronics / International Journal of Electronics Letters Page 12 of 20

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5 7. Experiments and Discussion
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7 7.1. Setup
8
9 In this paper, our experiments rely on SPICE circuits built from the 22 nm PTM HP v2.1
10 (high-k/metal gate and stress effect) MOS transistor models [Predictive Technology Model
11 (2016)] and the BSIM4v4.7 level 54 model [Berkeley Short-channel IGFET Model (2013)].
12 The PTM model specifies the nominal Vth ’s of 0.503 V and −0.461 V, for the nMOS
13 and the pMOS transistors (µVthn0 and µVthp0 ), respectively. The nominal operating voltage
14 (VDD ) is 0.8 V [Predictive Technology Model (2016)]. Furthermore, the SPICE circuits
15 have L = Lmin = 22 nm and nMOS widths Wni = 44 nm. The pMOS widths Wpi
16
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range from 44 nm to 300 nm. With a noise margin of 30% at nominal VDD , we have
17
Vin low = 0.3 × VDD , and Vin high = 0.7 × VDD .
18
19
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21
7.2. Unreliability of Logic Gates/Cells
22 Figure 4a shows a contour plot representing log10 (Υ)’s for 225 different combinations of
23
ee

Wp and VDD for a NOR2 gate. Similarly, Figures 4b and 4c show the plots for an XOR2
24 gate and a full-adder cell, respectively.
25
From the Υ-viewpoint, for a NOR2 gate, near-Vth operation is favored. At the same
26
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27
time, large Wp ’s seem desirable. Similarly, the XOR2 yields low Υ’s at near-Vth values,
28 however, a limited range for Wp looks feasible. The full-adder cell exhibits low Υ’s at
29 nominal VDD and large Wp ’s.
ev

30 Practically speaking, a circuit designer must consider not just Υ but also the traditional
31 metrics, such as, power, delay, power-delay-product (PDP) and energy-delay-product
32 (EDP). Therefore, based on the overall design goals, the designer has to find some op-
iew

33 timum values for Wp ’s and VDD for a given gate/cell. This work is limited to the modeling
34 of Υ’s for gates and logic circuits; the ones interested in the overall optimization (including,
35 Υ, delay, power, etc.) are referred to our soon-to-be-published work (in DemSET 2019).
36
37
On

38 7.3. Unreliability of Logic Circuits


39
40 Our unreliability framework has been used to evaluate the Υ’s of a few ISCAS85 bench-
41 mark circuits. Tables 2–5 list the circuit compositions, the Υ’s using three different meth-
ly

42 ods: (1) Nikolic et al. (2001), (2) Ibrahim et al. (2008), and (3) proposed/this work. The
43 evaluation times using for the proposed method are also included.
44 Table 2 shows the Υ’s for two cones of the c17 benchmark circuit (Figure 3) constituting
45 six NAND2 gates. For five inputs, there are 32 different input vectors, from which the
46 vector ’01010’ yields the worst (highest) Υ. The Υ’s for the two output cones are: ΥN 22 =
47
1.60 × 10−4 and ΥN 23 = 1.28 × 10−4 .
48
Table 3 shows the Υ’s for all different logic cones of the c5315 benchmark circuit.
49
50 Among all the cones, the largest number of inputs is 18 and the largest gate count is 56. The
51 circuit-Υ’s take a hit when the number of gates increase. Nearly two orders of magnitude
52 difference in Υ’s is observed between the smallest and the largest cones. It would make
53 sense to fortify the cone with the worst Υ in order to optimally improve whole circuit’s Υ.
54 Table 4 lists the logic cones of the c6288 benchmark circuit and the corresponding Υ’s.
55 The maximum input count among the cones is 18 and the largest gate count is 339. The
56 dominant gate type is NOR2. The larger cones tend to have worse Υ than the smaller ones.
57 It can be observed that 10× as many gates in a cone result in 10× higher Υ.
58 In Table 5, given are gate counts and Υ’s for all cones c7552 benchmark circuit. The
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60 URL: http:/mc.manuscriptcentral.com/intjelectron Email: ijeditor@leeds.ac.uk
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Page 13 of 20 International Journal of Electronics / International Journal of Electronics Letters

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15 (a) (b)
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(c)
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28 Figure 4. Gate/cell-Υ’s (log10 -scaled) as functions of Wp and VDD : (a) NOR2, (b) XOR2,
29 and (c) 1-bit full adder.
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30
31 cones are composed of a variety of gate types. The maximum number of inputs is 20 and
32 the largest gate count is 80. The Υ’s for the cones vary widely. As observed earlier, larger
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33
gate counts result in higher Υ’s.
34
35
Generally, upsizing the gates in a circuit improves the Υ. However, across-the-board
36 gate-upsizing can significantly and adversely affect other parameters such as power and
37 energy. After identifying the high-Υ cones, a circuit designer can selectively upsize the
On

38 gates, in order to strike a balance between the performance/power/energy and Υ.


39 Going back to Tables 2–5, we see that the largest circuit cone (of 339 gates) belongs to
40 the c6288 benchmark circuit; in this case, the evaluation time was nearly 12 minutes (on a
41 Mac OSX machine). The circuits with thousands of gates are expected to run proportionally
ly

42 longer but are still expected to stay within reasonable and practical limits.
43 Once again, referring back to Tables 2–5, we make the following observations about the
44 three methods, (1) Nikolic et al. (2001), (2) Ibrahim et al. (2008), and (3) proposed/this
45 work: (a) as expected, the larger the circuit, the higher the Υ’s calculated using the three
46
methods; (b) there are significant positive correlations between the Υ’s calculated using
47
this work and method-1 and method-2, as shown in Table 6; (c) method-1 is incognizant of
48
49
input voltage levels, gate topology, and circuit topology, and predicts 2–4.6× higher Υ than
50 this work; and (d) method-2 is incognizant of input voltage levels and gate topology, and
51 predicts 1.2–2.8× higher Υ than this work; the Υ-gap is narrower as the circuit topology
52 is considered both by method-2 and this work.
53
54
55 8. Conclusions
56
57 This paper has presented a comprehensive methodology and a framework for determining
58 the unreliabilities of logic circuits. The methodology and the framework are expected to be
59
60 URL: http:/mc.manuscriptcentral.com/intjelectron Email: ijeditor@leeds.ac.uk
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April 4, 2019

Table 2. ISCAS85 c17 benchmark circuit cone configurations (input count and gate count), Υcirc ’s based on two existing methods and this work, and
the evaluation time t (seconds) for this work.
Output Input Υcirc Υcirc Υcirc t
Cone Count INVs ANDs NANDs ORs NORs [Nikolic et al. (2001)] [Ibrahim et al. (2008)] This work [s]
N22 4 0 0 4 0 0 4.02 × 10−4 1.10 × 10−4 1.60 × 10−4 2.1
International Journal of Electronics

N23 4 0 0 4 0 0 4.02 × 10−4 1.20 × 10−4 1.28 × 10−4 2.2

Table 3. ISCAS85 c5315 benchmark circuit cone configurations (input count and gate count), Υcirc ’s based on two existing methods and this work,
Fo
and the evaluation time t (seconds) for this work.
Output Input Υcirc Υcirc Υcirc t
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Cone Count INVs ANDs NANDs ORs NORs [Nikolic et al. (2001)] [Ibrahim et al. (2008)] This work [s]
N2060 2 2 1 0 0 0 1.40 × 10−4 7.01 × 10−5 7.85 × 10−5 1.3
2019˙04˙05˙reliability˙IJE˙R1

ee
N4272 5 3 4 0 1 0 4.40 × 10−4 1.09 × 10−4 2.23 × 10−4 6.2
N4275 5 3 4 0 1 0 4.40 × 10−4 1.09 × 10−4 2.23 × 10−4 6.5
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N4278 5 3 4 0 1 0 4.40 × 10−4 1.09 × 10−4 2.25 × 10−4 6.6
N4279 4 3 4 0 1 0 4.40 × 10−4 1.06 × 10−4 1.98 × 10−4 6.2
N4737 6 3 6 0 1 0 5.60 × 10−4 1.68 × 10−4 4.29 × 10−4 9.1
ev
N4738 6 3 6 0 1 0 5.60 × 10−4 1.68 × 10−4 4.25 × 10−4 9.3
N4739 6 3 6 0 1 0 5.60 × 10−4 1.68 × 10−4 4.29 × 10−4 9.1
N4740 6 3 6 0 1 0 5.60 × 10−4 1.68 × 10−4 4.16 × 10−4 8.9
iew
N6716 9 17 4 19 0 2 3.02 × 10−3 1.22 × 10−3 1.43 × 10−3 62.0
N6877 10 18 4 22 0 2 3.35 × 10−3 1.38 × 10−3 1.64 × 10−3 68.1
N7015 9 9 7 3 3 0 1.32 × 10−3 3.66 × 10−4 6.87 × 10−4 27.9
On
N7363 14 16 13 6 6 0 2.50 × 10−3 4.59 × 10−4 1.00 × 10−3 57.1
N7365 12 15 10 6 4 0 2.12 × 10−3 4.30 × 10−4 8.09 × 10−4 49.6
ly
N7466 17 16 17 12 7 0 3.41 × 10−3 4.87 × 10−4 1.50 × 10−3 77.1

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International Journal of Electronics / International Journal of Electronics Letters

N7467 17 18 17 9 7 0 3.19 × 10−3 5.02 × 10−4 1.27 × 10−3 82.3


N7472 18 19 18 12 7 0 3.59 × 10−3 5.06 × 10−4 1.39 × 10−3 85.5
N7473 15 17 14 9 6 0 2.90 × 10−3 4.76 × 10−4 1.17 × 10−3 67.5
Page 14 of 20
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April 4, 2019
Page 15 of 20

Table 4. ISCAS85 c6288 benchmark circuit cone configurations (input count and gate count), Υcirc ’s based on two existing methods and this work,
and the evaluation time t (seconds) for this work.
Output Input Υcirc Υcirc Υcirc t
Cone Count INVs ANDs NANDs ORs NORs [Nikolic et al. (2001)] [Ibrahim et al. (2008)] This work [s]
N1581 4 2 2 0 0 6 8.00 × 10−4 3.17 × 10−4 3.20 × 10−4 9.2
International Journal of Electronics

N1901 6 4 5 0 0 18 2.26 × 10−3 7.19 × 10−4 8.37 × 10−4 36.5


N2223 8 6 9 0 0 39 4.67 × 10−3 1.23 × 10−3 1.68 × 10−3 81.7
N2548 10 8 14 0 0 69 8.03 × 10−3 1.84 × 10−3 2.70 × 10−3 160.4
N2877 12 10 20 0 0 108 1.23 × 10−2 2.50 × 10−3 4.05 × 10−3 268.4
Fo
N3211 14 12 27 0 0 156 1.75 × 10−2 3.19 × 10−3 5.86 × 10−3 393.9
N3552 16 14 35 0 0 213 2.37 × 10−2 3.89 × 10−3 7.94 × 10−3 581.6
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N3895 18 16 44 0 0 279 3.07 × 10−2 4.60 × 10−3 1.08 × 10−2 772.0
2019˙04˙05˙reliability˙IJE˙R1

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Table 5. ISCAS85 c7522 benchmark circuit cone configurations (input count and gate count), Υcirc ’s based on two existing methods and this work,
and the evaluation time t (seconds) for this work.
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Output Input Υcirc Υcirc Υcirc t
ev
Cone Count INVs ANDs NANDs ORs NORs [Nikolic et al. (2001)] [Ibrahim et al. (2008)] This work [s]
N881 2 2 0 1 0 0 8.00 × 10−5 6.01 × 10−5 8.17 × 10−5 1.2
N1113 3 1 1 1 0 0 1.20 × 10−4 6.51 × 10−5 1.00 × 10−4 1.3
iew
N1489 3 2 2 0 0 0 1.60 × 10−4 8.51 × 10−5 1.18 × 10−4 2.1
N1781 2 0 1 0 0 0 6.00 × 10−5 6.01 × 10−5 8.09 × 10−5 0.1
N10025 5 9 4 6 2 0 7.80 × 10−4 5.28 × 10−4 7.15 × 10−4 25
On
N10109 17 22 20 18 7 0 2.78 × 10−3 1.00 × 10−3 1.92 × 10−3 107.9
N10110 14 18 16 15 6 0 2.28 × 10−3 9.07 × 10−4 1.58 × 10−3 85.3
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N10111 11 15 12 12 5 0 1.80 × 10−3 8.20 × 10−4 1.37 × 10−3 65.1

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International Journal of Electronics / International Journal of Electronics Letters

N10112 8 12 8 9 4 0 1.32 × 10−3 7.19 × 10−4 1.10 × 10−3 43.7


N10353 20 25 27 18 10 0 3.43 × 10−3 1.07 × 10−3 2.22 × 10−3 130.2
April 4, 2019 International Journal of Electronics 2019˙04˙05˙reliability˙IJE˙R1
International Journal of Electronics / International Journal of Electronics Letters Page 16 of 20

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5 Table 6. Correlation among predicted Υcirc ’s for three benchmark circuits, using different
6 methods: (1) Nikolic et al. (2001), (2) Ibrahim et al. (2008), and (3) this work.
7
8 Correlation between methods
9 (1) and (2) (1) and (3)
10 c5315 0.74 0.87
11 c6288 0.89 0.88
12 c7552 0.88 0.87
13
14
15 useful additions to a circuit designer’s tool set. The usefulness of the methodology has been
16 demonstrated using a few benchmark circuits. Although the methodology partly relies on
Fo
17 simulations, their time-overhead is minimized by using constant/DC input voltages. Con-
18 sequently, the methodology is scalable and applicable to circuits with thousands of gates,
19 built from not just conventional MOS transistors but also newer technologies, such as Fin-
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20
FETs, FDSOI, etc. Unlike some of the existing techniques for determining reliability that
21
22
require use of costly commercial CAD tools (for example, Synopsys-TCAD or Cadence),
23 our method can be implemented using open-source tools (for example, Octave for building
ee

24 equations, and NGSPICE for SPICE simulations). The methodology and the framework
25 are expected to be useful additions to a circuit designer’s tool set.
26 The following are a few areas of investigation for enhancing the utility of the presented
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27 methodology:
28
• For large circuits, it may not be time-feasible to simulate all possible input vectors.
29
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30 So one should look into a method for finding a minimal set of test-vectors which
31 would sufficiently evaluate the Υcirc ’s.
32 • It would be worthwhile to find whether the use of only one or two primitive gate
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33 types would produce a unreliability-optimum circuit.


34 • Knowing which gate-types are better-suited for masking the failures, can reduce the
35 Υcirc ’s.
36 • As the circuit depth affects a circuit’s performance and energy, it would be beneficial
37 to study the relationship of the depth and the Υcirc .
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38
39
40
41 9. Appendix
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43 SPICE netlist for measuring the power and delay of a NAND2 gate is given in Listing 2.
44 The ‘included’ 22 nm MOS transistor models (‘22nm hp’) can be found in [Predictive
45 Technology Model (2016)]. The simulation results of the netlist are shown in Listing 3.
46
47
48
10. Acknowledgment
49
50
51 This work is supported by the UAE University’s UPAR 2016 grant.
52
53
54 References
55
56 Anwer, J., Shaukat, S., Khalid, U., & Hamid, N. (2012, Jun). Reliable area index: A novel approach
57 to measure reliability of Markov Random Field based circuits. In 4th int. conf. intell. adv.
58 syst. (pp. 851–853). Kuala Lumpur, Malaysia.
59
60 URL: http:/mc.manuscriptcentral.com/intjelectron Email: ijeditor@leeds.ac.uk
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5 1 * -- NAND2 gate node voltage measurement --
6 2 .include ./22nm_HP.pm
7 3 .param
8 4 +wpmos0 = 88nm
5 +wpmos1 = 88nm
9 6 +wnmos0 = 44nm
10 7 +wnmos1 = 44nm
11 8 +lpmos0 = 22nm
12 9 +lnmos0 = 22nm
13 10 +wpmos = 352nm
11 +lpmos = 22nm
14 12 +wnmos = 176nm
15 13 +lnmos = 22nm
16 14
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17 15 * -- Supplies --
vdd vdd 0 0.4
18 16
17 vddLoad vddLoad 0 0.4
19 vss vss 0 0
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20 19
21 20 * -- Stimuli --
22 21 vin1 in1 0 0.4
vin2 in2 0 0.0
23 22
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24 24 * -- UUT --
25 25 MP1 out in1 vdd vdd pmos w=wpmos0 l=lpmos0
26
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26 MP2 out in2 vdd vdd pmos w=wpmos1 l=lpmos0


27 27 MN1 out in1 w1 vss nmos w=wnmos0 l=lnmos0
MN2 w1 in2 vss vss nmos w=wnmos1 l=lnmos0
28
28
29
29
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30 * -- Load --
30 31 xld2 out outLoad vddLoad vss inv; 4x-sized
31 32

32 33 * -- Sim and measurements --


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.tran 0.5e-4 0.5


33
34
35 .meas tran p1vgs find par(’v(in1)-v(vdd)’) at=0.4
34 36 .meas tran p2vgs find par(’v(in2)-v(vdd)’) at=0.4
35 37 .meas tran p1vds find par(’v(out)-v(vdd)’) at=0.4
36 38 .meas tran p2vds find par(’v(out)-v(vdd)’) at=0.4
37 39 .meas tran n1vgs find par(’v(in1)-v(w1)’) at=0.4
On

40 .meas tran n2vgs find par(’v(in2)-v(vss)’) at=0.4


38 41 .meas tran n1vds find par(’v(out)-v(w1)’) at=0.4
39 42 .meas tran n2vds find par(’v(w1)-v(vss)’) at=0.4
40 43
41 44 * -- INV subcircuit --
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42 45 .subckt inv (input output vdd vss)


46 M10 output input vdd vdd pmos w=wpmos l=lpmos
43 47 M20 output input vss vss nmos w=wnmos l=lnmos
44 48 .ends inv
45
46 Listing 2 SPICE netlist for measuring node voltages in a NAND2 gate.
47
48
49 Asenov, A., Amoroso, S. M., & Gerrer, L. (2014, Sep). Progress in the simulation of time dependent
50 statistical variability in nano CMOS transistors. In 2014 int. conf. simul. semicond. process.
51 devices (pp. 273–276). Yokohama, Japan.
52 Asenov, A., Brown, A. R., Davies, J. H., Kaya, S., & Slavcheva, G. (2003). Simulation of intrin-
53 sic parameter fluctuations in decananometer and nanometer-scale MOSFETs. IEEE Trans.
54 Electron Devices, 50(9), 1837–1852.
55 Asenov, A., Ding, J., Reid, D., Asenov, P., Amoroso, S., Adamu-Lema, F., & Gerrer, L. (2015, May).
56 Unified approach for simulation of statistical reliability in nanoscale CMOS transistors from
57 devices to circuits. In 2015 ieee int. symp. circuits syst. (pp. 2449–2452). Lisbon, Portugal.
58 Beg, A. (2012, Feb). On pedagogy of nanometric circuit reliability. J. Supercomput., 59(2),
59
60 URL: http:/mc.manuscriptcentral.com/intjelectron Email: ijeditor@leeds.ac.uk
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International Journal of Electronics / International Journal of Electronics Letters Page 18 of 20

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5 1 No. of Data Rows: 10008
6 2 Measurements for Transient Analysis
7 3

8 4 p1vgs = 0.000000e+00
5 p2vgs = -4.000000e-01
9 6 p1vds = -1.380295e-05
10 7 p2vds = -1.380295e-05
11 8 n1vgs = 1.126541e-01
12 9 n2vgs = 0.000000e+00
13 10 n1vds = 1.126403e-01
11 n2vds = 2.873459e-01
14
15 Listing 3 SPICE simulation results showing node voltages in a NAND2 gate.
16
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17
18 762–778.
19 Beg, A. (2014, Oct). Designing array-based CMOS logic gates by using a feedback control system.
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