Ratioed Logic

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Ratioed Logic
VDD VDD

Resistive PMOS
Load RL Load
VSS
F F
In1 In1
In2 PDN In2 PDN
In3 In3

VSS VSS
(a) resistive load (passive load) (b) pseudo-NMOS (active load)

Goal: to reduce the number of devices over complementary CMOS (N+1

vs. 2N for complementary CMOS) at the cost of reduced robustness and
extra power dissipation.

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Ratioed Logic
VDD

• N transistors + Load
Resistive
• VOH = VDD
Load RL

• VOL = RPN

F RPN + RL

In1 • Contention between PDN and load.

In2 PDN Reduced noise margins. Asymmetrical
In3 response

• Static power consumption

VSS

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Pseudo-NMOS
Attractive for large fan-in NOR gates (PLAs – OR & AND planes)
Since the output is ideally low, NMOS can be considered in the linear, and PMOS is saturated
VDD

F
CL
A B C D

VOH = VDD (similar to complementary CMOS)

 V2  k 2
OL p
k n ( VDD – V Tn ) V OL – -------------  = ------ ( V DD – VTp )
 2  2

kp
V = (V – V ) 1 – 1 – ------ (assuming that V = V = V )
OL DD T k T Tn Tp
n

SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!

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 Pseudo-NMOS VTC
3.0

2.5

2.0 W/Lp = 4

1.5
Vout [V]

W/Lp = 2
1.0

W/Lp = 0.5 W/Lp = 1

0.5

W/Lp = 0.25
0.0
0.0 0.5 1.0 1.5 2.0 2.5
Vin [V]

Keep PMOS small to achieve low VOL. This however comes at expense
of long tLH.
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