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Battery Cascaded DC-DC DC-AC AC Grid
Abstract—A bidirectional three-phase DC-AC converter vA
with embedded DC-DC converter for bidirectional storage vB
VL VH
interface is proposed in this paper. With the help of the vC
embedded DC-DC converter, the voltage of storage battery
can vary in a wide range. To minimize the power rating and (a)
power losses of the embedded DC-DC converter, a simple Embedded DC-DC DP-TPC
Battery
carrier-based PWM strategy with zero-sequence injection vA
AC Grid
is proposed. By adopting the proposed PWM strategy, only VH
vB
a small ratio of total power needs to be processed by the VL vC
embedded DC-DC converter while most of the power is
only processed by the three-phase DC-AC stage within
single conversion stage. As a result, quasi single-stage
(b)
power conversion is achieved to improve the conversion Fig. 1. Bidirectional three-phase converters: (a) traditional two-stage
efficiency of the overall DC-AC power system. Principles, architecture with cascaded DC-DC converter, (b) proposed quasi
characteristics and implementations of the proposed single-stage architecture with embedded DC-DC converter.
three-phase DC-AC converter and its PWM strategy are
analyzed in detail. The feasibility and effectiveness of the
converters have been the most popular solution for industrial
proposed solutions are verified with experimental results. applications due to their simple topology, high efficiency,
flexible modulation and control strategy. However, according
Index Terms—Bidirectional DC-AC conversion, to the voltage relationship between the input and output voltage
embedded DC-DC converter, quasi single-stage of the Buck-type converters, the DC input voltage must be
conversion, pulse width modulation. greater than the peak amplitude of AC line voltage. In practical
applications, e.g., battery charging/discharging for electric
vehicles and energy storage systems, the DC voltage of storage
I. INTRODUCTION battery can be either lower or greater than the peak amplitude of
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DC-DC
DP-TPC
which drops a hint that similar principles can also be applied to Converter iH
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VL + id* + iq*
- PI A. Asymmetrical Carrier Waveforms
VL*
When the conventional CB-PWM strategy is applied to a
Fig. 5. Control block diagram of the bidirectional three-phase DC-AC
converter with embedded DC-DC converter.
traditional three-level DC-AC converter, due to voltage balance
of the dividing capacitors, two carriers are displaced
where x=a, b, c, for phase A, phase B and phase C respectively. symmetrically with respect to the zero-axis, which results in the
Taking phase A in the inverter mode as an example, the same peak to peak value of the carriers. However, this is not
equivalent circuits related to each switching state are illustrated always valid for the DP-TPC because the voltage of LV port VL
in Fig. 4, and the corresponding current path is marked with the is not constant. When the CB-PWM strategy is applied to the
red line. As shown in Fig. 4(a), when SHa and SLa1 turn on, the DP-TPC, the peak to peak values of carriers should be varied
current supplied from the HV port, iH, flows into the AC grid, according to the voltages of VL and VH. As shown in Fig. 6, the
which means part of input power, PH, can be fed to the grid after amplitudes of two carriers are in proportion to the DC voltage
processed by the DC-DC converter. On the other hand, when (VH-VL) and VL, respectively, and can be normalized by
V VL 2 VH VL
SLa1 and SLa2 turn on, the current iL is directly transferred from
the LV port to the AC grid without processed by the DC-DC VPeak _ Top H (2)
converter, as shown in Fig. 4(b). When SLa2 and SZa turn on, VH 2 VH
both iH and iL would not fed to the grid through phase A, as VL 2V
shown in Fig. 4(c). The current path of other two phases is the VPeak _ Bottom L (3)
same as that of Phase A, and for the rectifier mode, it just has a
VH 2 VH
reversed current path and can be studied in a similar manner. 2 VL VH 1 0 2 VL VH 1 0
The control block diagram of the bidirectional DC-AC va vb vc va vb vc
1 1
converter with embedded DC-DC converter is illustrated in
Fig.5. The voltage VH is regulated by the embedded DC-DC
converter, while the voltage VL is regulated by the DP-TPC. It is
0 0
worth to mention that, either the battery voltage or the battery
current can be regulated by the current id, thus, the current
reference id* can be generated by the battery control loop. For
-1 -1
the DP-TPC in rectifier mode, the battery is directly connected 0 2 0 2
to the LV port and the power from the HV port is also fed to the
(a) (b)
LV port through the embedded DC-DC converter. That means Fig. 6. Three-phase modulation signals and two carrier waveforms for
the power on the LV port represents the total power of both the the DP-TPC: (a) case I: VL<VH/2, (b) case II: VL≥VH/2.
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According to (2) and (3), the value of the boundary line of vx vtop vtop
carrier waveforms shown in Fig. 6 can be derived as (2VL/VH-1). 1 1
With different locations of the boundary line, there are two 2 VL VH 1 2 VL VH 1
cases for the DP-TPC. When VL<VH/2, the boundary line lies vbottom vx vbottom
below zero-axis, and the amplitude of the top carrier waveform
is larger than that of the bottom one, as shown in Fig. 6(a). -1
When VL≥VH/2, the situation is contrary to the former one, as 1 1
shown in Fig. 6(b). It is worth to mention that, when VL=VH/2, 0 0
the boundary line locates on zero-axis, and the amplitude of two (a) (b)
carrier waveforms is equal to each other, which means that the Fig. 7. Switching state function Sx: (a) case I: vx≥2VL/VH-1, (b) case II:
carrier waveforms of the traditional three-level converter is vx<2VL/VH-1.
only a special case of the DP-TPC. Due to space constraints, three-level converter. For a three-level converter, a
only detailed analysis of case II (i.e., VL≥VH/2) will be given zero-sequence signal is always added to the sinusoidal
here and for the other case it can be studied in a similar manner. modulation signal vx to adjust the duty cycle of switches and
further achieve the voltage-balancing task. Inspired by this idea,
B. Modified Modulation Signals with Zero-Sequence to maximize the power PL for the DP-TPC, the key point is to
Injection explore the proper zero-sequence voltage, v0.
Assume that the original three-phase modulation signals are It is necessary to further analyze (6) to carry out the proper
sinusoidal, it can be written as zero-sequence injection. After adding the zero-sequence
va m cos component v0, (6) is replaced by
1 vx v0
vb m cos 2 3 (4) if vx v0 2VL VH 1
v m cos 2 3 2 2V V
c
dx L H
(8)
where m is the modulation index, θ is the phase angle. 1 vx v0 if v v 2V V 1
As mentioned above, the modulation target of the DP-TPC is
2VL VH
x 0 L H
to maximize the power PL, which is directly transferred from Noting that the physical meaning of d x is the duty cycle when
the LV port to the AC grid within single power conversion the phase leg is connected to the LV port, which, absolutely, is
stage. To analyze the power flow of the DP-TPC, the foremost nonnegative. Hence, the span of the zero-sequence component
step is to deduce the averaged current flowing out of the LV that can be injected is expressed as
port of the DP-TPC, which is defined as iL as shown in Fig. 2. 1 vmin vo 1 vmax (9)
The averaged current is determined by both the switching
pattern and the phase current. Generally, one-phase current where
contributes to the LV port if and only if this phase is connected vmin min(va , vb , vc ) vmax max(va , vb , vc ) (10)
to the LV port, as shown in Fig. 4(b). Assumed that the are defined as the minimum and maximum value of the original
frequency of the carrier waveforms is much higher than the sinusoidal-modulation signals, respectively.
frequency of modulation signals, the phase current can be In order to maximize the active power PL, which is directly
considered as a fixed value in a switching cycle. Then iL can be fed to the AC grid with only single-stage power conversion, it is
expressed as necessary to increase the average value of iL. A straightforward
iL d x ix (5) method is to block the negative phase current flowing into the
x a ,b, c LV port, that is to say, to make the duty cycle d x to be zero
where dx (x=a,b,c) is the duty cycle when the phase leg is when the phase current ix<0. The three-phase currents of the
connected to the LV port, and d x [0,1] , ix is the DP-TPC can be given by
corresponding phase current. ia I m cos
ib I m cos 2 3
In one switching period, either the top carrier waveform or (11)
the bottom one intersects with the modulation signal, as shown i I cos 2 3
in Fig. 7. The darkened regions in Fig. 7 represent the duration c m
in which the phase leg is connected to the LV port. With the where Im is amplitude of phase current, φ is power factor angle.
graphical method, the duty cycle dx can be derived as For convenience of analysis, the unity power factor case,
1 vx where the power factor angle φ=0, is firstly taken into account
2 2V V if vx 2VL VH 1 and the influence of power factor will be discussed afterwards.
dx L H
(6) According to the polarity of the phase current, the analysis is
1 vx if vx 2VL VH 1 performed in six sections (i.e., S1-S6) shown in Fig. 8.
2VL VH In section S1, where π/6≤θ≤π/2, the followed relationship is
in which vx (x=a, b, c) is the modulation signal of each phase. satisfied, i.e., ia≥0, ib≥0, ic<0. In this case, the phase current ia
Particularly, when VL=VH/2, (6) can be simplified by and ib flow out of the VL port, while the phase current ic flows
into the VL port. To block the negative current ic, the most ideal
d x 1 vx (7)
zero-sequence component is to make d c to be zero. Thus, the
Equation (7) shows the same expression as the duty cycle when injected zero-sequence component can be easily derived as
the phase current flows out of the neutral point in the traditional
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ia≤0, ib>0, ic≤0 Fig. 10. Block diagram of the proposed CB-PWM strategy with
S2/2 v0=-va-1
zero-sequence injection.
S3 ia<0, ib≥0, ic≥0 v0=-va-1 vx1
Eq. (13)
S4/1 v0=-va-1 S Hx
vx
ia≤0, ib≤0, ic>0 1
S Lx 2
0
S4/2 v0=-vb-1 vx 2
Eq. (14)
S5 ia≥0, ib<0, ic≥0 v0=-vb-1 S Lx1
1
0
S Zx
S6/1 v0=-vb-1
ia>0, ib≤0, ic≤0
S6/2 v0=-vc-1 Fig. 11. Block diagram of the proposed CB-PWM strategy with the
invariable carrier.
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three-phase sinusoidal-modulation signals, which are modified modulation signals and the phase current during each 2π/3
by adding the zero-sequence component determined by (12), interval, (15) can be replaced by
generating the proposed modulation signals. Then these signals 3 23
2 0
are compared with the asymmetrical carrier waveforms to PL VL (d aia dbib dcic )d (16)
generate the switch gating signals.
In practical implementation with digital controllers, such as During the interval of 0≤θ≤2π/3, the zero-sequence
DSP, the asymmetric carrier is not easy to be implemented with component is (-vc-1), hence, the modified modulation signals
the ePWM module. As an alternative, the carrier can be kept can be derived as
invariable while the modulation signals are equivalently va va v0 3m cos 6 1
modified to ensure the same switching signals for each switch.
vb vb v0 3m sin 1 (17)
When the modulation signal vx intersects with the top carrier, v v v 1
SHx and SLx2 operate in high frequency. To ensure the same duty
c c 0
cycle of these two switches with the carrier kept invariable Substituting (8), (11), (17) into (16), the single-stage power
from 0 to 1, the modulation signal is modified as supplied by the LV port is expressed as (18), shown at the
v 1 2VL VH bottom of this page, where l=VL/VH, 1 arccos(2l
vx1 x (13) 3m) ,
2 2VL VH
2 arcsin(2l 3m) , respectively. The span of l and the
Similarly, when the modulation signal vx intersects with the
modulation index m is 0<l≤1 and 0 m 2 3 .
bottom carrier, SLx1 and SZx operate in high frequency. To ensure
the same duty cycle of these two switches, the modulation Neglecting the power losses of the converter, the total active
signal is modified as power is given by
v 1 I
Po 3 VAC m cos (19)
vx 2 x (14) 2
2VL VH
where VAC is the RMS value of AC line voltage, equal to 380V.
The block diagram of the proposed CB-PWM strategy with
The single-stage power supplied by the LV port PL is
the invariable carrier is given in Fig. 11. It is seen that dual
normalized by the total active power Po, which is expressed as
modulation signals, vx1 and vx 2 , intersect with the invariable PLN=PL/Po. Based on (18) and (19), the curve of the normalized
carrier and then generates the gating signals for each switch. It single-stage power PLN is drawn in Fig. 12, where it is plotted
is obvious that the procedure to implement the proposed with the condition φ=0 and m=0.88 (the modulation index is
CB-PWM strategy is very simple, which implies that it is an derived with the condition VH=700V). In Fig. 12, VACPK is the
effective method suitable for practical applications. 1.01
Considering the symmetrical characteristics of the modified Fig. 12. Curve of the normalized single-stage power PLN.
2
3
PL VL
2
0
3
(d aia d bib ) d
1 + 2 3m cos( 6 ) 2
3m cos( 6 )
0 6 cos( ) d 3 cos( ) d
3I m 2 2l 2l 3m
1
6
if 0 l
2 4
2 3m sin 2
2 2 3m sin
0 cos( 3 ) d 3 cos( ) d
2
2l 3 2 2l
2
(18)
1 3m cos( 6 )
1 2 3m cos( 6 ) 2
3m cos( 6 )
0 cos( )
6
d cos( )
6
d cos( )
3
d
3I 2 2l
2l 1 1 2l 3m 3m
m
6 6
if l
2 4 2
2 2 3m sin - 2 2 2 3m sin 2
2 3 m sin
0
2 -2
3
cos( ) d cos( ) d cos( ) d
3 2l 3 2 2l 3 2l
3m
1 if <l 1
2
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peak value of AC line voltage, which is equal to 380 2 V, VH a T-type three-level converter [21], is also constructed and
is the HV port voltage and keeps as a constant value, 700V. As tested based on the schematic shown in Fig. 15. The parameters
shown in Fig. 12, it is found that PLN increases with the voltage of these two solutions are both listed in Table II, based on
VL, which means a higher VL is better for reducing the power which the voltage and current stresses (including turn on/off
processed by the embedded DC-DC converter. In particular, if current, average and RMS current at full load) in each
VL is higher than the peak value of AC line voltage, VACPK, all semiconductor are given in Table III. It is worth to mention that
the power can be directly supplied by the LV port without using the voltage stresses of SLx1 and SLx2 in the DP-TPC are VL and
the embedded DC-DC converter. (VH-VL) respectively. Therefore, the maximum value of VL is
taken as the worst case when considering the voltage stress of
B. Influence of Power Factor SLx1, while the minimum value of VL is taken as the worst case
As stated earlier, the derivation of the proposed CB-PWM when considering the voltage stress of SLx2. The current stresses
scheme is carried out under unity power factor condition.
Embedded
However, for some practical applications, the influence of the
DC - DC
power factor must be taken into consideration. In this case, the
active power transfer characteristics of the DP-TPC should be Load
re-verified, with taking account of the power factor angle φ.
When considering the influence of power factor, the apparent
power of the DP-TPC should keep as a constant value, which
stands for the power capacity of the converter. Therefore, the
total active power varies with the power factor angle φ, as
expressed in (19). Referring to (19), the power factor angle φ
cannot reach to -π/2 or π/2, because the total active power DP - TPC
would be equal to zero and there is no physical meaning for PLN. Fig. 14. The picture of the hardware prototype.
Taking the range of φ∈[-π/3, π/3] as an example, the curve of DC-DC
PLN in terms of the variable VL and φ is drawn in Fig. 13. It is Converter
T-type Three-level Converter
seen that, with any specific value of VL, when φ changes from
S Ha S Hb S Hc
-π/3 to π/3, PLN almost lies on a horizontal line, which indicates C2 S La 2 S La1 vA
S1 ia La
that the influence of the power factor is very slight. a
S Lb 2 S Lb1 vB
iL C3 ib Lb
V. EXPERIMENTAL EVALUATION AND ANALYSIS L1 VH b
o
S Lc 2 S Lc1 vC
A. Description of the Experimental Setup ic Lc
VL c
S2
An experimental platform of a 3kW bidirectional three-phase C1 S Za S Zb S Zc
DC-AC converter, which is composed of an embedded
bidirectional DC-DC converter and a DP-TPC, is built and n
tested. The experimental setup is shown in Fig. 14. For Fig. 15. The traditional two-stage DC-AC converter with cascaded
comparison, the traditional two-stage DC-AC converter, which DC-DC converter.
is composed of a cascaded bidirectional DC-DC converter and TABLE II
TEST SETUP PARAMETERS
Values
Parameters
Proposed Solution Traditional Solution
DC voltage VL 250~500V 250~500V
DC voltage VH 700V 700V
PLN
Filter capacitor C1, C2, C3 350μF, 560μF, NA 220μF, 220μF, 470μF
Inductor L1 2.5mH 2.5mH
Inductor Lx (x=a,b,c) 1.6mH 1.6mH
Switching frequency of
50kHz 50kHz
DC-DC converter fs1
Switching frequency of
DP-TPC or T-type 20kHz 20kHz
VL VH converter fs2
Switches S1, S2 CMF20120D CMF20120D
Fig. 13. The normalized single-stage power PLN versus different VL Switches SHx, SZx (x=a,b,c) HGTG18N120BND HGTG18N120BND
values and different power factor angles φ. Switches SLx1, SLx2 (x=a,b,c) HGTG18N120BND FGH20N60UFD
TABLE III
VOLTAGE AND CURRENT STRESSES IN EACH SEMICONDUCTOR
Voltage Stress (V) Turn On/Off Current (A) Average Current (A) RMS Current (A)
Devices
Proposed Traditional Proposed Traditional Proposed Traditional Proposed Traditional
S1 700 700 11.15 13.55 3.29 4.32 5.67 7.42
S2 700 700 11.15 13.55 6.4 8.37 7.91 10.33
SHx (x=a,b,c) 700 700 6.43 6.43 1.41 1.43 1.87 2.72
SLx1/SLx2 (x=a,b,c) 500/450 350 6.43 6.43 1.75 0 2.87 2.39
SZx (x=a,b,c) 700 700 6.43 6.43 1.93 1.43 3.19 2.72
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non-switching switching va (1V/ div) non-switching switching va (1V/ div) non-switching switching va (1V/ div)
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single-stage power supplied by the LV port, PLN, at various harmonic distortion (THD) analysis. The THD is measured
values of VL and φ is tested with power analyzer, with power analyzer, YOKOGAWA WT1800. The data of the
YOKOGAWA WT1800, which guarantees power accuracy of phase current was collected by a Tektronix MDO3014
0.05% of reading plus 0.05% of range. The comparison oscilloscope and then processed using the Matlab fast Fourier
between the theoretical and experimental results of PLN is transform (FFT) function for harmonics analysis. The
illustrated in Fig. 19. The theoretical curves are obtained by measured results are given in Fig. 21. Due to the asymmetrical
picking up several specific VL values from Fig. 13. It is multilevel characteristics, the THD performance of the
observed that the errors between the experimental tested results proposed DP-TPC is not as good as the traditional symmetrical
and theoretical curves, which are possibly caused by the power operated three-level converter. As shown in Fig. 21(a), the
losses of the experimental setup and the measurement errors, THD performance of the DP-TPC is almost the same with the
are relatively small. Moreover, all the tested results indicate symmetrical operated three-level converter when VL is close to
that the normalized single-stage power PLN is slightly 350V, but becomes worse as the increasing of VL voltage, which
influenced by the power factor angle φ. indicates that the THD performance of the DP-TPC is related to
the voltage of VL. The relatively significant harmonic
C. Dynamic Waveforms
components for the THD performance are shown in Fig. 21(b),
The experimental result of the transition operation for where it is seen that the low-order harmonics of the DP-TPC are
bidirectional power flow of the proposed DC-AC converter is slightly higher than the three-level converter. This is possibly
given in Fig. 20, where iLoad is the load current, VL is the LV port because the dead-time effect would be different with the
voltage, vA is the grid voltage and ia is the phase current, variation of VL for the DP-TPC. To improve the THD
respectively. It is seen that the phase current ia is in phase with performance, the dead time compensation or resonant control
the grid voltage vA in the inverter mode, whereas ia is 180°out based harmonic compensation technique could be used.
of phase with vA in the rectifier mode. Meanwhile, when the
load suddenly changes, the converter can change from the E. Efficiency Evaluation
inverter mode to the rectifier mode immediately, which The overall efficiency of both the traditional and the
indicates that fast dynamic performance can be achieved by the proposed solutions is tested and compared. The efficiency
proposed bidirectional DC-AC converter. curves are tested under different VL values with two typical
loads, i.e., half load and full load, and different load conditions
D. Line Voltage and Current THD Performance
with two typical VL values, i.e., 350V and 500V, respectively.
The quality of line voltage (vab) waveform is evaluated by 98 98
weighted total harmonic distortion (WTHDV) analysis [23]. For 97 97
Efficiency(%)
Efficiency(%)
the proposed solution, the WTHDV values at different VL values, 96 96
95 95
i.e., 250V, 350V and 500V, are 0.40%, 0.41%, 0.43%, 94 94
respectively, while for the traditional solution, the WTHDV 93 93
92 92
value is 0.45%. It is found that the WTHDV values of the 91
DC-DC+DP-TPC DC-DC+DP-TPC
DC-DC+Three-level 91 DC-DC+Three-level
proposed and traditional solutions are quite close to each other, 90 90
200 250 300 350 400 450 500 200 250 300 350 400 450 500
which indicates that the proposed CB-PWM strategy used for VL (V) VL (V)
the DP-TPC does not lead to the increasing of WTHDV values.
(a) (b)
The quality of phase current (ia) is evaluated by total Fig. 22. Efficiency comparison with different VL: (a)half load, (b)full load.
96 96
v A (400V/div) 95 95
94 94
93 93
ia (10A/ div) 92 92
DC-DC+DP-TPC DC-DC+DP-TPC
91 91
DC-DC+Three-level DC-DC+Three-level
t (1s/div) t (20ms/div) 90 90
20 30 40 50 60 70 80 90 100 20 30 40 50 60 70 80 90100
inverter mode rectifier mode inverter mode rectifier mode Load ratio(%) Load ratio(%)
Fig. 20. Dynamic waveforms of the proposed bidirectional DC-AC (a) (b)
converter changing from the inverter mode to the rectifier mode when Fig. 23. Efficiency comparison under different load conditions: (a)
the load suddenly changes. VL=350V, (b) VL=500V.
前后级总损耗
30
30
Percentage of fundamental (%)
25
25 DP-TPC(VL=350V) 2.5
2.5
DP-TPC(VL=350V) A1:Proposed A2:Traditional
DP-TPC(VL=500V) 100
THD of ia(%)
10
10 11 60
55 0.5
0.5 40
00 00 20
0.10 0.20 30
20 0.40 50
0.30 40 0.60 70
0.50 60 0.80 90
0.70 80 0.90 100
1.00 1.10 1 2
5th
3 4 5 6 7
7th 11th 13th 17th
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Load ratio(%) 1 2
Harmonic order
3 4 5 6 7 8 9 10 11 12 13
14 15 16 17 18 19 20 21 22 23 24 25 0 A1 A2 A1 A2 A1 A2
(a) (b) VL=250V VL=350V VL=500V
Fig. 21. Comparison of THD performance and harmonics of phase
Fig. 24. Comparison of the power losses of active switches between
current ia: (a) THD performance, (b) harmonics analysis.
the proposed DC-AC converter and the traditional two-stage solution.
0278-0046 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2866080, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
The tested results are shown in Fig. 22 and Fig. 23, where it is vd iLoad
VL* id* VL
obvious that much higher efficiency can be achieved by the 1 id 3vd idc 1
Gv ( s ) Gi ( s ) Gd ( s ) K PWM
sLx 2VL sC1
proposed DC-AC converter compared to the traditional
Hi
two-stage solution. Detailed power loss breakdown of active
switches of the proposed DC-AC converter and the traditional Hv
two-stage DC-AC converter is calculated [24] and shown in Fig. A1. DC voltage control diagram in d-axis.
Fig.24. It is seen that the power losses of active switches can be
reduced by the proposed solution, in which the power loss where Gi(s) is the PI current controller expressed as
reduction of S1, S2 and SHx benefits from the quasi single stage Gi (s) kip kii s , Gd(s) is the digital delay expressed as
structure, while the power loss reduction of SLx1 and SZx benefits
from the reduced average switching frequency. Taking the case Gd (s) e1.5sTs , KPWM is the PWM unit and Hi is the feedback
of VL=350V as an example, the power loss reduction of active coefficient of the inductor current. In this paper, KPWM=350 and
switches of the proposed solution is 15.9W, in which 8.3W is Hi=1. To ensure the stability and good dynamic performance,
from the reduced average switching frequency and the other is the cutoff frequency of the current loop fci is set at 1.7kHz with a
from the quasi single stage structure. phase margin of 450. This yields kip=0.057, kii=20.7. Since the
These attractive advantages, e.g., higher overall efficiency, current loop in q-axis is similar to the d-axis, the parameters of
lower power rating and cost of the DC-DC converter, suggest the current controller in q-axis are the same as that in d-axis.
that the proposed bidirectional three-phase DC-AC converter is As the current loop already designed, the open-loop transfer
a good candidate for practical applications such as energy function of the voltage loop is given by
storage systems, uninterrupted power supplies, etc. Gi _ open ( s) 3vd 1
Gv _ open ( s) Gv ( s) H v (A2)
1 Gi _ open ( s) 2VL sC1
VI. CONCLUSION
where Gv(s) is the PI voltage controller expressed as
A novel bidirectional three-phase DC-AC converter with
embedded DC-DC converter and its carrier-based PWM Gv (s) kvp kvi s , vd is the peak value of the phase voltage and
(CB-PWM) strategy is proposed in this paper. Theoretical Hv is the feedback coefficient of the DC voltage. In this paper,
analysis and experimental verification indicate that the vd= 220 2 and Hv=1. To ensure the stability of the system, the
proposed DC-AC converter with the CB-PWM strategy has the bandwidth of the voltage loop should be lower than the current
following features: loop. Hence, the cutoff frequency of the voltage loop fcv is set at
(1) With the help of the embedded DC-DC converter, the 200Hz with a phase margin of 450. This yields kvp=0.6, kvi=488.
voltage of storage battery can vary in a wide range.
(2) By employing the proposed CB-PWM scheme, most REFERENCES
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2866080, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
[10] S. Hu, Z. Liang, D. Fan and X. He, “Hybrid Ultracapacitor–Battery Hongfei Wu (S’11, M’13, SM 18) received the B.S.
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Multi-Level Inverters with Reduced Conversion Stages and Enhanced Since 2013, he has been with the Faculty of
Conversion Efficiency,” IEEE Trans. Ind. Electron., vol. 64, no. 3, pp. Electrical Engineering, NUAA, and is currently a
2081-2091, Mar. 2017. Professor with College of Automation Engineering,
[12] P. Chamarthi, P. Chhetri and V. Agarwal, “Simplified Implementation NUAA. He has authored and co-authored more than
Scheme for Space Vector Pulse Width Modulation of n-Level Inverter 140 peer-reviewed papers published in journals and
With Online Computation of Optimal Switching Pulse Durations,” IEEE conference proceedings. He is the holder of more than 30 Patents. His research
Trans. Ind. Electron., vol. 63, no. 11, pp. 6695-6704, Nov. 2016. interests are high performance power converters and distributed power
[13] J. Wang, Y. Gao and W. Jiang, “A Carrier-Based Implementation of generation system.
Virtual Space Vector Modulation for Neutral-Point-Clamped Dr. Wu was the recipient of the Outstanding Reviewer of IEEE Transactions
Three-Level Inverter,” IEEE Trans. Ind. Electron., vol. 64, no. 12, pp. on Power Electronics (2013). He was a recipient of the Changkong Scholar
9580-9586, Dec. 2017. Award and Young Scholar Innovation Award of NUAA in 2017. He serves as
[14] C. Wang and Y. Li, “Analysis and Calculation of Zero-Sequence Voltage an Associate Editor of Journal of Power Electronics and CPSS Transactions on
Considering Neutral-Point Potential Balancing in Three-Level NPC Power Electronics and Applications.
Converters,” IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 2262-2271,
Jul. 2010.
[15] J. Pou, J. Zaragoza, S. Ceballos, M. Saeedifard and D. Boroyevich, “A Tianyu Yang was born in Jiangsu Province, China, in
Carrier-Based PWM Strategy With Zero-Sequence Voltage Injection for 1994. He received the B.S. degree in electrical
a Three-Level Neutral-Point-Clamped Converter,” IEEE Trans. Power engineering from Nanjing University of Aeronautics
Electron., vol. 27, no. 2, pp. 642-651, Feb. 2012. and Astronautics (NUAA), Nanjing, China, in 2016.
[16] J. I. Leon, S. Kouro, L. G. Franquelo, J. Rodriguez and B. Wu, “The He is currently working toward the M.S. degree in
Essential Role and the Continuous Evolution of Modulation Techniques electrical engineering and power drives from NUAA,
for Voltage-Source Inverters in the Past, Present, and Future Power Nanjing, China.
Electronics,” IEEE Trans. Ind. Electron., vol. 63, no. 5, pp. 2688-2701, His research interests include modulation and
May 2016. control of AC-DC converters, power quality.
[17] Z. Wang, F. Cui, G. Zhang, T. Shi and C. Xia, “Novel Carrier-Based
PWM Strategy With Zero-Sequence Voltage Injected for Three-Level
NPC Inverter,” IEEE J. Emerg. Sel. Topics Power Electron., vol. 4, no. 4,
pp. 1442-1451, Dec. 2016. Li Zhang (S’11-M’13) received the B.E. and Ph.D.
[18] S. K. Giri, S. Chakrabarti, S. Banerjee and C. Chakraborty, “A degrees in electrical engineering from Nanjing
Carrier-Based PWM Scheme for Neutral Point Voltage Balancing in University of Aeronautics and Astronautics (NUAA),
Three-Level Inverter Extending to Full Power Factor Range,” IEEE Nanjing, China, in 2007, and 2012, respectively.
Trans. Ind. Electron., vol. 64, no. 3, pp. 1873-1883, Mar. 2017. He joined the Faculty of Electrical Engineering,
[19] J. S. Lee, S. Yoo and K. B. Lee, “Novel Discontinuous PWM Method of a Hohai University, Nanjing, China, in 2014, where he
Three-Level Inverter for Neutral-Point Voltage Ripple Reduction,” IEEE is currently a Professor. From Oct. 2012 to Sep. 2014,
Trans. Ind. Electron., vol. 63, no. 6, pp. 3344-3354, June 2016. he was a Post-Doctoral Research Fellow with the
[20] R. Maheshwari, S. Busquets-Monge and J. Nicolas-Apruzzese, “A Novel Department of Electrical Engineering, Tsinghua
Approach to Generate Effective Carrier-Based Pulsewidth Modulation University, Beijing, China. From Jul. to Aug. 2012,
Strategies for Diode-Clamped Multilevel DC–AC Converters,” IEEE he was a Visiting Scholar of Electrical Engineering at Department of Energy
Trans. Ind. Electron., vol. 63, no. 11, pp. 7243-7252, Nov. 2016. Technology, Aalborg University, Denmark. From Oct. 2016 to Oct. 2017, he
[21] M. Schweizer and J. W. Kolar, “Design and Implementation of a Highly was a Visiting Scholar of Electrical Engineering at Department of Electrical
Efficient Three-Level T-Type Converter for Low-Voltage Applications,” and Computer Engineering, Ryerson University, Canada. His current research
IEEE Trans. Power Electron., vol. 28, no. 2, pp. 899-907, Feb. 2013. interests include topology, control of dc-ac converter and distributed generation
[22] D. Somayajula and M. L. Crow, “An integrated active power filter–ultra technology.
capacitor design to provide intermittency smoothing and reactive power Dr. Zhang was a recipient of the IEEE TRANSACTIONS ON POWER
support to the distribution grid,” IEEE Trans. Sustain. Energy, vol. 5, no. ELECTRONICS Outstanding Reviewer Award in 2014.
4, pp. 1116–1125, Oct. 2014.
[23] B. Diong, H. Sepahvand and K. A. Corzine, “Harmonic distortion
optimization of cascaded H-bridge inverters considering device voltage Yan Xing (M’03) was born in Shandong Province,
drops and noninteger dc voltage ratios,” IEEE Trans. Ind. Electron., vol. China, in 1964. She received the B.S. and M.S.
60, no. 8, pp. 3106–3114, Aug. 2013. degrees in automation and electrical engineering from
[24] A. K. Sadigh, V. Dargahi and K. A. Corzine, “Investigation of Tsinghua University, Beijing, China, in 1985 and
Conduction and Switching Power Losses in Modified Stacked Multicell 1988, respectively, and the Ph.D. degree in electrical
Converters,” IEEE Trans. Ind. Electron., vol. 63, no. 12, pp. 7780-7791, engineering from Nanjing University of Aeronautics
Dec. 2016. and Astronautics (NUAA), Nanjing, China, in 2000.
Since 1988, she has been with the Faculty of
Electrical Engineering, NUAA, and is currently a
professor with College of Automation Engineering,
Jiangfeng Wang (S’15) was born in Zhejiang NUAA. She has authored more than 100 technical papers published in journals
Province, China, in 1990. He received the B.S. degree and conference proceedings and has also published three books. Her research
in electrical engineering and automation from interests include topology and control for dc-dc and dc-ac converters.
Nanjing University of Aeronautics and Astronautics, Dr. Xing is an Associate Editor of the IEEE Transactions on Power
Nanjing, China, in 2012, where he is currently Electronics and Journal of Power Electronics. She is a member of the
working toward the Ph.D. degree in electrical Committee on Renewable Energy Systems within the IEEE Industrial
engineering. Electronics Society.
His research interests include the grid-tied inverter
control, renewable energy generation system and
power quality.
0278-0046 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.