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FPGA
E E
I-Cache Pipeline
AXI Instructions C AXI Instructions AXI Data C AXI Data
C D-Cache Registers
C Ethernet Header
Nonsafe 2 Safe DMA
MicroBlaze #0
D A[31:24] = 0x3D (16MB keyhole) IP Header
A[23:8] = configurable keyholing
AXI Peripheral Data
Program Counter
M
D
A Writes to 0x3D000000 – 0x3DFFFFFF
M
A UDP Header
K
XLMB AXI Lockstep
Xilinx e
3 R E
y
REG
Delay
XLMB AXI Lockstep D CDMA h
C
(COTS) C
o
32Bit FNV-1a
AXI Peripheral Data
o
Program Counter
l
n
e
l
32Bit CRC-32-C
y UDP Payload
WR
only
E E
3 I-Cache Pipeline 3
REG
Delay
AXI Instructions C AXI Instructions AXI Data C AXI Data REG
Delay
C C Timestamp Register
D-Cache Registers
MicroBlaze #1
UART Channel
UART
CAN
CAN OCM 256K CoreSight
l2C
l2C
Central
Interconnect SRAM
HP3 HP2
SPI
SPI
Memory
Interconnect
CoreSight
Memory
Interfaces HP1
DDR2/3,3L,
Interfaces
SRAM/
Components LPDDR2
SIM
NOR
ONFI 1.0 DAP
Controller
GPIO
FPGA
GP0 GP0 SILOFFC
Sound I2S UART Lite HP3
HP0
HP0
GP0 UART Lite
BacklightC
HP0
MVB ASIC
MVB BRAM
ADC_IN
CCTVC
GP0 NANDSUB
MVB_ASIC_PINS
Controller
SPI
Safe Keyboard
EMIO ETH_RCV[0:7] GP0 Direct
MII2RMII ETH0 XPTSU
MVB
SPI/GPIO
TouchC
EMIO ETH_XMT[0:7]
MII2RMII ETH1 XPTSU
SPI
SR_ioCABC
FPGA FPGA
Nonsafe FPGA modules SIL2 FPGA modules Nonsafe FPGA modules SIL2 FPGA modules
NANDSUB NANDSUB
XVAC XLDU ccfm-XLMB SIFT Safe DMAC XVAC XLDU ccfm-XLMB SIFT Safe DMAC
Controller ccfm-XLMB Controller ccfm-XLMB Helper
Helper N2S DMA S2N DMA
N2S DMA S2N DMA DMA
DMA
Scratch Buffer
80 80 80
SIL2 visualisation
ECC
0 0 0