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DISCRETE DEVICES
1. Introduction
Again, we are astonished, how we are able to talk to our near and dear living several
thousands of kilometres away, from wherever we are, at home, office, on the road in a car, or
in a classroom –by just clicking a few n numbers on our palm sized cellular phones!
Electronics has made deep impact in several vital areas such as health care, medical
diagnosis and treatment, Air and space travels, Automobiles, etc. In short, the technological
developments of several countries of the globe are directly related to their strengths in
electronics design, manufacture, products and services. It appears as though we have to add
inevitably an “E” to the three “R”s, namely, Reading, writing, and arithmetic, to declare a
Man or Woman to be “literate”! Needless to add that the “E” here means “Electronics”! Thus
Electronics has become surely a “Basic Science”. It is no more an “applied science”. Just as
we teach physics, chemistry, biology and mathematics in our schools, it is high time we start
teaching our children at school, Electronics as a separate subject by itself.
1.1 Semiconductors:
We know the importance of using the materials like copper, aluminum etc. in
electrical applications. This is because copper, aluminum etc are good conductors. Similarly,
some materials like glass, wood, paper etc. Also, find wide applications in electrical and
electronic applications. These are called insulators. There is another category of materials
whose ability to carry current, called conductivity, lies between that of conductor and
insulators. Such materials are known as semi conductors. Germanium and silicon are two
well-known semiconductors.
A silicon crystal is different from an insulator because at any temperature above
absolute zero temperature, there is a finite probability that an electron in the lattice will be
knocked loose from its position, leaving behind an electron deficiency called a "hole”. If a
voltage is applied, then both the electron and the hole can contribute to a small current flow.
The semiconductors in the pure form are known as intrinsic semiconductor.
The addition of a small percentage of foreign atoms in the regular crystal lattice of
silicon or germanium produces dramatic changes in their electrical properties, producing n-
type and p-type semiconductors.
One of the crucial keys to solid-state electronics is the nature of the P-N junction.
When p-type and n-type materials are placed in contact with each other, the junction behaves
very differently than either type of material alone. Specifically, current will flow in one
direction (forward biased) but not in the other (reverse biased), creating the basic diode.
Figure 1.2.1: Diode
Figure 1.2.1 shows the circuit symbol of a diode and photograph of typical diode.
Since the diode is a two terminal device, the application of a voltage across its terminals
leaves three possibilities:
• No bias
• Forward bias
• Reverse bias
No Bias
In the absence of an applied bias voltage, the net flow of charge in any one direction
for a semiconductor is zero. The current, which flows under the unbiased condition, is called
diffusion. Diffusion is a process in which the charge carriers move from the region of higher
concentration to the region of lower concentration. The concentration of holes in the p region
is more compared to n region and similarly the concentrations of electrons are more in n
region than p region. There will be diffusion of charge carriers and then they undergo
recombination with the opposite charge carriers. The recombined carriers are neutral in
charge and they oppose further movements of charge carriers. The region near the junction
occupied by the recombined charges is called as depletion region. The difference of potential
across the depletion region is called barrier potential. For silicon diodes barrier potential is in
the range of 0.6 to 0.7 V and for Germanium it ranges from 0.2V-0.3V.
Forward Bias
A forward bias or ON condition is established by applying positive potential to the
p-type material and the negative potential to the n-type material as shown in figure 1.2.2
Figure 1.2.2: Forward biasing of PN Junction Diode.
On forward biasing a diode initially, no current flows due to the barrier potential. The applied
forward potential repels the charge carriers and hence pushes it towards the junction. This
results in construction of the depletion region. As the applied potential increases, it exceeds
the barrier potentials at one value (above cut-off value), and the charge carriers gain
sufficient energy to cross the potential barrier and enter the other region. The holes, which are
majority carriers in the p-region, becomes minority carrier on entering the n-region, and the
electrons, which are majority carriers in n-region, become minority carriers on entering the
p-region. This injection of the majority carriers into the opposite region results in current
called diode forward current IF.
Reverse Bias
Under reverse bias condition, the positive terminal of the DC supply is connected to the n-
type and negative terminal to the p-type semiconductor as shown in the figure 1.2.3.
- +
Variable DC
Voltagebiasing of PN- Junction diode
Figure 1.2.3: Reverse
On reverse biasing the majority charge carriers are attracted towards the terminals of the
applied potential. This results in the widening of the depletion region. That is number of
uncovered positive ions in the depletion region of the n-type material will increase due to the
large number of electrons are flown towards the applied positive potential and similarly the
number of negative ions in the p-type also will increase due to applied negative potential. The
net effect is widening of the depletion region, which will introduce a great barrier for the
majority carriers to overcome resulting in zero current flow due to majority charge carriers.
The current due to minority charge carriers still do not change, and takes part in the diode
current. So the current that exist under the reverse bias conditions is called the reverse
saturation current and is represented by I0 or IS it is in the range of few micro amperes.
The Forward diode current flowing during the forward bias is given by the following
equation.
VD
I D = I 0 (e ηVT
− 1) (1)
T
VT = (T in Kelvin), Volt equivalent of temperature.
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When the diode is forward biased, the applied voltage is positive and is large
compared to VT and exp(VD/ηVT) >>1, there for 1 can be neglected from the equation and
final equation will be
VD
I D = I 0 (e ηVT
) (2)
The ID current will increase exponentially with an increase in the forward voltage VD after the
cut in voltage is reached. When the diode is reverse biased, the applied voltage is negative
and is small compared to VT and exponential term can be neglected. Then the diode equation
becomes ID≈I0.
As we can see from the V-I characteristics when the diode is forward biased initially,
the forward current is zero and when we increase the forward voltage, the forward current
will vary in small magnitude, as the barrier potential is not reached. Once the applied voltage
is exceeds the barrier potential or cut-in voltage or Vknee, then there will be exponential rise in
the forward current. The forward current is in the range of milli amperes.
When the diode is reverse biased and when we increase the reverse applied voltage, as
we know only reverse saturation current flows, which is due to the minority charge carriers.
The reverse current is in the range of few micro amperes. Finally, when the reverse voltage is
increased beyond certain limit, the diode breaks down and reverse current shoots up to a very
large value. The breakdown of diode can be either zener breakdown or avalanche
multiplication, which will be discussed next.
m
A
(V Vkne
(V
) )
e
μ
A
Figure 1.2.4: VI characteristics of the PN
Junction diode
The Diode Breakdown
The reverse break down in diodes can occur due to two mechanisms, each of them
require critical electric field at the depletion region of the diode. They are
• Zener breakdown
• Avalanche Multiplication
Zener breakdown
When the doping is very high (≥ 1025 atoms/m 3), the depletion region is very narrow,
which results in tunnelling of electrons from p-type valance band to the n-side conduction
band constitutes a reverse current from n to p, this is called zener effect. The basic
requirement for the tunnelling current is a large number of electrons separated from a large
number of empty states by a narrow potential barrier.
The electric field resulting due to the depletion region causes field emission where by
the force on outer orbit electrons due to field is very high that they are pulled out from the
parent nucleus to become free carriers. This ionization by electro-static attraction is known as
“Zener breakdown” and causes an increase in the free carriers density and hence an increase
in the reverse current of the junction. Only for the lower level of reverse voltage the zener
effect is exhibited
Avalanche Multiplication
When the diode is reverse biased, carriers acquire sufficient energy from the thermal
energy and along with the applied reverse bias results in the high electric field in the
depletion region. An electron entering from the p-side may be accelerated to high kinetic
energy to cause ionizing collision. This ionizing collision results in the breakage of covalent
bonds of the bound charges, this result in the generation of new electron-hole pair. The
original electron and generated electron are both swept to the n-side of the junction and
generated hole is swept to the p-side. The generation of electron-hole pair results in the
generation of enormous energy by the process called fission. The liberated fission energy
along with the applied potential and thermal energy colloid with other non-ionized bonds.
This collision and generation of new electron-hole pairs are continuous and multiplicative,
which results in a large amount of charge carriers and thus an increase in the reverse current.
Effect of Temperature on the Reverse current
Since the reverse saturation current is temperature dependent parameter, the reverse
saturation current approximately doubles for every 10o C rise in temperature. Let I01 is the
reverse saturation current at temperature T1 and I02 is the reverse saturation current at
temperature T2, where T2 > T1. The rise in reverse saturation current is given by the relation.
The dynamic resistance (r) of a diode is defined as the ratio of change in voltage to
the change in current. The dynamic resistance is not as constant as static resistance; it
depends upon the operating voltage.
∆V η VT η VT
r= = =
∆I D VD
I D + I0
I 0 eηVT
T
VT = (T in 0Kelvin) Volt equivalent of temperature.
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Solved Problems
1. A Silicon diode has a saturation current of 1pA at 20 oC. Find Diode bias voltage when
diode current is 3mA. Diode bias current when the temperature is 100OC assuming the
diode voltage to be constant.
Solution:
Given
VD
T 293
V = = = 25 .25 mV
I D = I0 (e ηVT
− 1) and T 11600 11600
ID
V D = ηVT ln(1 + ) = 1.103
Io
T 373
VT = = = 32 .15 mV
11600 11600
The temperature is raised to 100OC (So the reverse saturation current I0 changes) use
the relation.
I 02 = I 01 2 (T2 −T1 )/10 = 1x10 −12 (2100−20) / 10 ) = 1x10 −12 (28 ) = 256 pA
1.103
I D = 256x10 -12
(e 2x32.15x10 -3
− 1) = 7.21mA
2. Find the static and dynamic resistance of a p-n junction germanium diode if the
temperature is 27OC and IO=1μA for an applied forward bias of 0.2V.
Solution
Given
T 300
VT = = = 25 .86 mV
11600 11600
0.2
I D = 1x10 (e
-6
− 1) = 2.28 mA
-3
1x25.86x10
V
Static resistance = =
I
Exercise Problems:
1. A Silicon diode has a saturation current of 0.1pA at 20OC. Find its forward voltage
when the current is 0.3mA.
2. A Germanium diode has IO=10μA. Determine its forward voltage when it is carrying
50mA of current. Compute the dynamic resistance at this operating point.
3. A Silicon diode at room temperature conducts 5mA at 0.7V. If the voltage increases
to 0.8V. Find reverse saturation current.
4. Calculate the factor by which reverse saturation current IO of Germanium diode is
multiplied when the temperature increases from 25 to 100OC.
5. Determine the voltage for which the reverse current in a germanium diode reaches
70% of its reverse saturation value at room temperature.
Advantages:
Transistor structure
Two types:
• Thin layer of n-type material sandwiched between two p-type materials (called PNP
transistor)
• Thin layer of p-type material sandwiched between two n-type materials (called NPN
transistor)
Base is lightly doped – allows most of the charge carriers to pass through it
Transistor operation
Current relationship:
I E = IC + I B - (1.1)
When emitter circuit is opened, there is no supply of free electrons from emitter to
collector. Even then, there will be small collector current called reverse saturation collector
current I CBO . This is due to thermally generated electron-hole pairs.
Even during normal operation, I CBO is present. So, total collector current is:
where, αdc is fraction of emitter current, which flows to collector. From (1.2),
I C − I CBO
α dc = - (1.3)
IE
IC
α dc ≈ - (1.4a)
IE
Also,
IC
β dc = - (1.4b)
IB
Transistor symbols
Transistor configurations
Transistor is 3-terminal device. For amplifier circuit, four terminals are required –
two for input and two for output. So, one of three terminals of transistor is made common for
both input and output. Accordingly, there are 3 configurations:
• Common base (CB) configuration
• Common emitter (CE) configuration
• Common collector (CC) configuration
Common base configuration
Base is common, emitter is input terminal, and collector is output terminal. We get two
characteristics: input characteristics and output characteristics
Input characteristics
It is the plot of input current IE, versus input voltage VEB, for various values of output
voltage VCB. As VEB is increased, IE increases similar to diode characteristics. If VCB is
increased, then IE increases slightly. This is due to the increase in electric field aiding the
flow of electrons from emitter.
Output characteristics
Plot of output current IC versus output voltage VCB for various values of input current IE.
Here IE is less than zero (E-B diode is reverse biased) and VCB is positive (C-B diode
is reverse biased).Transistor is said to be in OFF state since IC is zero.
Here IE is positive nonzero (E-B diode forward biased) and VCB is negative (C-B
diode is forward biased) IC decreases exponentially in this region.
Input characteristics
It is the plot of input current IB versus input voltage VBE for various values of output
voltage VCE. As VBE is increased, IB increases similar to diode characteristics. If increased,
then IB decreases slightly. This is due to Early effect.
Output characteristics
Plot of output current IC versus output voltage VCE for various values of input current IB.
Active region: Region to the right of VCE Sat, above IB=0 curve, where the curves are linear.
Note that VCE = VCB + VBE - (1.5)
If VCE > VCE Sat, then VCB becomes positive (i.e., C-B diode is reverse biased)
VCE Sat is around 0.3V for silicon transistor. If IB > 0, then it means E-B diode is forward
biased. When VCE is increased, IC increases slightly due to Early effect. Note that slope of
curve is more than that of CB o/p characteristics. If IB is increased, IC also increases
When IB=0, IC=ICEO (Collector current in common Emitter with base Open) ICEO is much more
than ICBO of CB configuration.
Cutoff region: Region below IB=0 curve Here E-B diode and C-B diode are both reverse
biased Transistor is said to be in OFF state since IC is almost zero.
Saturation region: Region to the left of VCE Sat and right of y-axis Here E-B diode and C-B
diode are both forward biased
Note: Common collector characteristic is similar to that of common emitter, hence not
discussed here.
IE I
Dividing throughout by IC we get: =1+ B
IC IC
1 1
From equations (1.4a) and (1.4b) we get: =1+
α dc β dc
β dc
Rearranging, we get: α dc = - (1.6)
β dc + 1
α dc
Rearranging again, we get: β dc = - (1.7)
1 − α dc
In the above two equations, we can replace αdc and βdc by αac and βac respectively without
causing any harm.
α dc I
Hence, we get: I C = I B + CBO
1 − α dc (1 − α dc )
I CBO
Substituting IB = 0, we get: I CEO = - (1.8)
(1 − α dc )
Practical transistor circuits
In the circuit diagrams shown earlier, there were no resistors. Without resistors,
currents may be high enough to burn the transistor!
Figure shows practical transistor circuit used to determine input and output characteristics in
CE configuration
V BB − V BE
Rearranging, we get: I B = - (1.9)
RB
VBE is often taken as +0.7 V for Silicon and +0.2 V for Germanium, for simplicity.
There are limits on voltage, current and power dissipation in transistor. If these limits
are exceeded, then transistor will not function properly, or may even burn.
i.e., VCE should not cross VCEMAX, IC should not cross ICMAX, and PC should not cross PCMAX.
All three conditions should be satisfied at the same time.
For the transistor to operate in active region, within the maximum ratings, we require:
Problems
1. In pnp transistor circuit, the ammeter reads the base current as 16 µA. If the
emitter current is 1.618 mA, determine the collector current.
2. A BJT has α = 0.99, IB = 25 µA and ICBO = 200 nA. Find the collector current.
3. For problem 2, find the emitter current. Also find the emitter current by
neglecting ICBO and then find the percentage of error.
4. For a certain BJT, β = 50, ICEO = 3 µA and IC = 1.2 mA. Find IB and IE.
5. A Ge transistor with β = 100 has base-to-collector leakage current of 5 µA. If the
transistor is connected in common-emitter operation, find the collector current for
base current (a) 0 and (b) 40 µA.
6. A Ge Transistor has collector current of 51 mA when the base current is 0.4 mA.
If β = 125, then what is its collector cutoff current ICEO?
7. In a transistor circuit, when the base current is increased from 0.32 mA to 0.48
mA, the emitter current increases from 15 mA to 20 mA. Find αac and βac values.
8. A transistor with α = 0.98 and ICBO = 5 µA has IB = 100 µA. Find IC and IE.
1.5 Light Emitting Diode:
The increasing use of digital displays in calculators, watches and all forms of
instrumentation has contributed to an extensive inherent in structures that emit light when
properly biased. The two types of displays commonly used are light emitting diode (LED)
and liquid crystal display(LCD).
Light emitting diode is a diode that gives of visible or invisible (infrared) light when
energized. In any p-n junction there is a recombination of holes and electrons. During this
process energy possessed by the free electron is transferred to another state, some of this
energy is transferred into heat and some in the form of photons. In silicon and germanium
greater percentage is converted into heat and the emitted light is insignificant.
Diodes constructed of GaAs emit light in the infrared zone during the process of
recombination. Even though the light is not visible, they have numerous applications like,
security systems, industrial processing, optical coupling etc. where visible light is not a
desirable effect visible light can be generated.
By using elements like gallium, arsenic and phosphorous LEDs producing red,
green, yellow, blue, orange or infrared (visible). LED’s have replaced incandescent lamps in
many applications because of their low voltage, long life, and fast on-off switching.\
Figure shows seven segment display. It contains seven LEDs. It can be used to display
any alphanumeric character. Fig is schematic diagram of seven segment display, where all
the anodes connected together.
External series resistance is used to limit the current. By grounding one or more
resistors we can display a character.
Application of LED:
When a p-n junction diode is reverse biased the current flow is only due to the
minority charge carriers. These carriers exists because of thermal energy, which dislocates
valance electrons from their orbits, producing electron hole-pairs.
When light energy bombards a p-n junction, it can dislodge valance electrons. The
more light striking the junction, reverse current increases. In photo diode light is made to fall
on p-n junction by providing a window to allow the light fall.
Fig1.6.1: Photo diode
• As light detectors
• As demodulators
• Encoders
• Optical Communications
• High speed counting
• Switching circuits
The photo transistor is like a normal transistor, but the base is kept open. The
incident light is made to fall on the base terminal so that base current is generated and the
output current is multiplied by the β of the transistor. The symbol and typical application
circuit is as shown in fig.1.7.1.
(a) (b)
Applications:
1.8 Opto Coupler: Opto coupler or opto isolator combines an LED and a photo diode in a
single package as shown below in Fig. no.1.8.1.
When input voltage is applied to LED emits light and this light is detected by photo
diode. The reverse current flowing in the photo diode circuit produces a voltage drop across
series resistor, which is proportional to reverse current, which in turn proportional to input
voltage. This device can couple an input signal to the output circuit.
Advantage of opto coupler is the isolation between input and output circuits.
(a) (b)
The depletion layer formed in a p-n junction is like a parallel plate capacitor. The
capacitance of this depends on the width of the depletion layer. Width of the depletion layer
is directly -proportional applied reverse voltage. Thus capacitance can be controlled by
reverse voltage. Diodes used for this purpose are called varactor or voltage variable capacitor
or varicaps.
Symbol and variation in capacitance are as shown:
Applications
DIODE CIRCUITS
2.1 Clipper: Clipping circuits are used to select that part of the input wave which lies above
or below some reference level. A clipper is a device designed to prevent the output of a
circuit from exceeding a predetermined voltage level without distorting the remaining part of
the applied waveform.
A clipping circuit consists of linear elements like resistors and non-linear elements like
diodes or transistors. Clipping circuits are used to select for purposes of transmission, that
part of a signal wave form which lies above or below a certain reference voltage level.
The action of the circuit is explained below. When the input signal voltage is negative, the
diode D is reverse-biased and behaves as an open-switch, the entire negative half cycle
appears across the load( output). When the input signal voltage is positive but does not
exceed battery voltage VR, the diode D remains reverse-biased and most of the input voltage
appears across the output. When during the positive half cycle of input signal, the signal
voltage exceeds the battery voltage VR, the diode D is forward biased i.e conducts heavily.
The output voltage is equal to VR and stays at VR as long as the input signal voltage is greater
than battery voltage VR in magnitude. Thus a biased positive clipper removes input voltage
when the input signal voltage exceeds the battery voltage. Clipping can be changed by
reversing the battery and diode connections.
That is Vo = Vi if Vi<VR
Vo = VR if Vi>VR
Negative biased clipper: the clipping circuit which removes part of the negative input is as
shown in Fig. below
When the input signal voltage is positive, the diode D is reverse-biased and behaves as an
open-switch, the entire positive half cycle appears across the load. When the input signal
voltage is negative but does not exceed battery voltage V, the diode D remains reverse-biased
and most of the input voltage appears across the output. When during the negative half cycle
of input signal, the signal voltage exceeds the battery voltage V, the diode D is forward
biased i.e conducts heavily. The output voltage is equal to – V and stays at – V as long as the
input signal voltage is greater than battery voltage V in magnitude. Thus a biased negative
clipper removes input voltage when the input signal voltage exceeds the battery voltage
In this circuit,
Vo = Vi if Vi>VR
Vo = VR if Vi<VR
It is a circuit which removes signal voltage above or below a reference level. It is useful in
signal shaping and protecting circuits. Circuit shown in fig 2.1.1 removes all positive half
cycles. During positive half cycle diode turns on. So ideally zero voltage across Rl
During negative half cycle diode is off. So input voltage appears across Rl But practically
diode voltage 0.7V will appear at output. If we reverse the polarity of diode we get negative
clipper and connecting battery serially with diode we get biased clipper.
Positive unbiased
In the negative cycle of the input AC signal, the diode is forward biased and conducts, charging the
capacitor to the peak positive value of VIN. During the positive cycle, the diode is reverse biased and
thus does not conduct. The output voltage is therefore equal to the voltage stored in the capacitor plus
the input voltage again, so VOUT = 2VIN
Negative unbiased
A negative unbiased clamp is the opposite of the equivalent positive clamp. In the positive cycle of
the input AC signal, the diode is forward biased and conducts, charging the capacitor to the peak
value of VIN. During the negative cycle, the diode is reverse biased and thus does not conduct. The
output voltage is therefore equal to the voltage stored in the capacitor plus the input voltage again, so
VOUT = -2VIN
2.3 Diode Rectifiers:
The nature of the p-n junction is that it will conduct current in the forward direction
but not in the reverse direction. It is therefore a basic tool for rectification in the building of
DC power supplies.
The figure 2.3.3 shows the circuit diagram of half wave rectifier the voltage at point A
does the opposite of that at point B. When A is increasing in a positive direction, B is
increasing in a negative direction. It is rather like the two ends of a seesaw. During the first
half cycle of the waveform shown on the left, A is positive and B is negative. The diode is
forward biased and current flows around the circuit formed by the diode, the transformer
winding and the load. Since the current through the load and the voltage across the load are in
the same proportions, then the voltage across the load is as shown in the right hand diagram,
during the first half cycle. During the second half cycle, A and the anode is negative, B
and the cathode are positive. The diode is reverse biased and no current flows. This is
indicated by the horizontal line in the right hand diagram. The diode only conducts on every
other half cycle. The diode only conducts during half the cycle. Hence, HALF-WAVE
RECTIFICATION. The rectified voltage is DC (it is always positive in value). However, it is
not a steady DC but PULSATING DC. It needs to be smoothed before it becomes useful.
Ripple Factor
Ripple factor r is defined as the ratio of rms value of ac component to the dc
component in the output.
Vav the average or the dc content of the voltage across the load is given by
Ripple Factor
Efficiency
Efficiency, η is the ratio of the dc output power to ac input power. Thus
Low cost High Ripple factor
Low TUF
A practical full-wave rectifier circuit is shown in figure 2.3.4 It uses two diodes (D1
and D2) and a center-tapped transformer (T1). When the center tap is grounded, the voltages
at the opposite ends of the secondary windings are 180 degrees out of phase with each other.
Thus, when the voltage at point A is positive with respect to ground, the voltage at point B is
negative with respect to ground. Let's examine the operation of the circuit during one
complete cycle.
During the first half cycle (indicated by the solid arrows), the anode of D1 is positive
with respect to ground and the anode of D2 is negative. The current flows from the ground up
through the load resistor (RL), through diode D1 to point A. In the transformer, current flows
from point A, through the upper winding, and back to ground (center tap). When D1
conducts, it acts like a closed switch so that the positive half cycle is felt across the load (RL).
During the second half cycle (indicated by the dotted lines), the polarity of the applied
voltage has reversed. Now the anode of D2 is positive with respect to ground and the anode
of D1 is negative. Now only D2 can conduct. Current now flows, as shown, from ground
(center tap), up through the load resistor (RL), through diode D2 to point B of T1. In the
transformer, current flows from point B up through the lower windings and back to ground
(center tap). Notice that the current flows across the load resistor (RL) in the same direction
for both halves of the input cycle.
Ripple Factor
The ripple factor for a Full Wave Rectifier is given by
The average voltage or the dc voltage available across the load resistance is
Full Wave Rectifier is 2Vm because the entire secondary voltage appears across the
non-conducting diode.
Advantages Disadvantages
Low ripple factor Output voltage is only the half the secondary voltage
High efficiency High PIV rating is needed
High TUF Transformer is bulky, expensive and difficult to
adjust the center tap accurately.
Full-wave bridge rectifier:
The voltages at points A and B on the transformer are changing in opposite directions.
When A is increasing in a positive direction, B is increasing negatively. It is like the opposite
ends of a seesaw. During the first half cycle, A is positive and B is negative. D1 has positive
on its anode, D2 has negative on its cathode. Both are forward biased. Current flows around
the circuit formed by these diodes, the load and the transformer winding, as shown in the
second diagram.
Figure 2.3.5: The full wave bridge wave rectifier and its
waveforms
The current flowing up through the load produces a pulse of voltage across the load as
shown in the right hand waveform. During the next half cycle, A is negative and B is
positive. D4 has positive on its anode, D3 has negative on its cathode. Both are forward
biased. Current flows around the circuit as shown in the bottom diagram, again flowing in the
same direction through the load and producing another pulse of voltage. Since the full cycle
is used, this circuit is called a FULL-WAVE rectifier. The following parameters are same as
the full wave rectifier they are Idc, Vdc, Irms, Vrms, Ripple factor, Efficiency Form factor, peak
factor. Its Peak Inverse Voltage (PIV) is Vm.
Advantages Disadvantages
Low ripple Uses four diodes, which reduces voltage by
two diode drops for every half cycle.
High efficiency
TUF is higher than centre tapped FWR
Less bulky and expensive
PIV is only Vm
As TUF is high, it can be used for high
power applications.
Rectifiers with Capacitor Filters:
A capacitor filter connected directly across the load is shown above. The property of a
capacitor is that it allows ac component and blocks dc component. The operation of the
capacitor filter is to short the ripple to ground but leave the dc to appear at output when it is
connected across the pulsating dc voltage.
During the positive half cycle, the capacitor charges up to the peak vale of the
transformer secondary voltage, Vm and will try to maintain this value as the full wave input
drops to zero. Capacitor will discharge through RL slowly until the transformer secondary
voltage again increases to a value greater than the capacitor voltage. The diode conducts for a
period, which depends on the capacitor voltage. The diode will conduct when the transformer
secondary voltage becomes more than the diode voltage. This is called the cut in voltage. The
diode stops conducting when the transformer voltage becomes less than the diode voltage.
This is called cut out voltage.
Referring to the figure below, with slight approximation the ripple voltage can be
assumed as triangular. From the cut-in point to the cut-out point, whatever charge the
capacitor acquires is equal to the charge the capacitor has lost during the period of non-
conduction, i.e., from cut-out point to the next cut-in point.
Figure 2.3.8
If the value of the capacitor is fairly large, or the value of the load resistance is very large,
then it can be assumed that the time T2 is equal to half the periodic time of the waveform.
From the above assumptions, the ripple waveform will be triangular and its rms value is
given by
A Zener diode exhibits almost the same properties, except the device is especially
designed so as to have a greatly reduced breakdown voltage, the so-called Zener voltage. A
Zener diode contains a heavily doped p-n junction allowing electrons to tunnel from the
valence band of the p-type material to the conduction band of the n-type material. A reverse-
biased Zener diode will exhibit a controlled breakdown and let the current flow to keep the
voltage across the Zener diode at the Zener voltage. For example, a 3.2-volt Zener diode will
exhibit a voltage drop of 3.2 volts if reverse biased. However, the current is not unlimited, so
the Zener diode is typically used to generate a reference voltage for an amplifier stage, or as a
voltage stabilizer for low-current applications.
The breakdown voltage can be controlled quite accurately in the doping process.
Tolerances to within 0.05% are available though the most widely used tolerances are 5% and
10%.The effect was discovered by the American physicist Clarence Melvin Zener.
Another mechanism that produces a similar effect is the avalanche effect as in the
avalanche diode. The two types of diode are in fact constructed the same way and both
effects are present in diodes of this type. In silicon diodes up to about 5.6 volts, the zener
effect is the predominant effect and shows a marked negative temperature coefficient. Above
5.6 volts, the avalanche effect becomes predominant and exhibits a positive temperature
coefficient.
Zener diodes are widely used to regulate the voltage across a circuit. When connected
in parallel with a variable voltage source so that it is reverse biased, a zener diode conducts
when the voltage reaches the diode's reverse breakdown voltage. From that point it keeps the
voltage at that value.
In the circuit shown, resistor R provides the voltage drop between input and output.
The value of R must satisfy two conditions:
• R must be small enough that the current through D keeps D in reverse breakdown.
The value of this current is given in the data sheet for D. For example, the common
BZX79C5V6 device, a 5.6 volt 0.5 watt zener diode, has a recommended reverse
current of 5 mA. If insufficient current flows through D, then output will be
unregulated, and could rise as high as . When calculating R, allowance must be made
for any current flowing through the external load, not shown in this diagram,
connected across the output.
• R must be large enough that the current through D does not destroy the device. If the
current through D is ID, its breakdown voltage VB and its maximum power dissipation
PMAX, then IDVB < PMAX.
A zener diode used in this way is known as a shunt voltage regulator (shunt meaning
connected in parallel), and voltage regulator being a class of circuit that produces a stable
voltage across any load.
The circuit has to mainatin constant voltage across a load resisitor R L. The circuit
holds the voltage across the load RL almost equal to the voltage across zener VZ even after th
input Vin andload resistor RL undergo changes. If the unrgulated dc voltage Vin rises, the
current through R increases. This extra current is directed to the zener diode instesd of
flowing through the load. The zener diode voltage is virtually unaffected by the increase in
this current and load voltage which is same as the diode voltage Vz remains constant. If the
load requires more current when RL is decreased, the zener didoe can supply the extra current
without affecting the load voltage.
I = Iz + IL
Vin − Vz
I =
R
Vin − Vz
Rs =
I
After substituting the value if I we get,
Vin − Vz
Rs =
IZ + IL
VZ
For Line regulation RL is constant. And I L = is also constant
RL
For Load Regulation, Vin is constant and RL varies between RLmin and RLmax and load current is
VZ VZ
given by I Lmin = and I Lmax =
R Lmax R Lmin
Vin(min) − Vz
I min = ,
R
I min = I z(min) + I L
Vin(max) − Vz
Similarly when Vin=Vin(max) we have I max = ,
R
I max = I z(max) + I L
The selected R must be small enough to permit minimum zener current to ensure that
the diode is in its breakdown region. That is R must be small enough to ensure that minimum
current IZ(min ) flows under worst condition. This is when Vin falls to its smallest possible value
Vinmin and IL is its largest possible value ILmax (Load Regulation). At the same time R must be
selected large enough to ensure that the current through the zener diode should not exceed the
maximum zener current Izmax so that power desipation in the diode will not will not exceed P z.
That is the condition when Vin rises to the value of Vinmax and load current IL to its minimum
ILmin
SO we can write
Vin(min) − VZ Vin(max) − VZ
R≤ and R≥
I zmin + I Lmax I zmax + I Lmin
Applications:
• As Voltage regulators
• As Voltage Limiters
• Wave shaping
• Protection diode
• Fixed reference voltage
Solved Problems
In a zener voltage regulator if Vz=10V, Rs=1KΩ, RL-2KΩ. If the input voltage Vin
varies from 22 to 40 V, find the maximum and minimum values of zener current.
Solution:
VZ 10
IL = = = 5mA
R L 2x10 3
Vin(min) − Vz 22 − 10
I min = = = 12mA
R 1x10 3
−3
I min = I z(min) + I L and I z(min) = I min + I L = 12x10 − 5x10 −3 = 7mA
Vin(max) − Vz
Similarly I max = and I max = I z(max) + I L
R
40 - 10
I max = = 30mA ans
1x10 3
Although voltage regulators can be designed using OP AMPS and other discrete
components, it is easier and quicker to use IC voltage regulators. Furthermore IC voltage
regulators are versatile, relatively inexpensive and are available with features such as
programmable output, current / voltage boosting is possible.
IC voltage regulators are available as
78XX series are three terminal positive voltage regulators. In 78XX, XX indicates the
output voltage. They are available as 7805, 7806, 7808, 7815, 7818, and 7819. 79Xx series
are negative fixed voltage regulators which are complements to the 78Xx series devices.
The input capacitor is used to cancel the inductive effects due to long distributive leads and
the output capacitor to improve the transient response.
Adjustable Voltage Regulators:
IC regulator like LM117, LM317, LM338 are adjustable voltage regulators. The
LM117 series of adjustable 3-terminal positive voltage regulators is capable of supplying in
excess of 1.5A over a 1.2V to 37V output range. They are exceptionally easy to use and
require only two external resistors to set the output voltage. Further, both line and load
regulation are better than standard fixed regulators. Normally, no capacitors are needed
unless the device is situated more than 6 inches from the input filter capacitors in which case
an input bypass is needed. An optional output capacitor can be added to improve transient
response.
Lm 317 is a three terminal positive voltage regulator that can supply 1.5A of load current
over an adjustable output range of 1.25V to 37V. Output voltage is given by the equation
Typical value of I adj = 50 µA and Vref = 1.25V, Vref is the voltage between output terminal and
center terminal, I adj is the current in center terminal.
SMPS
The main advantage of this method is greater efficiency because the switching
transistor dissipates little power when it is outside of its active region (i.e., when the transistor
acts like a switch and either has a negligible voltage drop across it or a negligible current
through it). Other advantages include smaller size and lighter weight (from the elimination of
low frequency transformers which have a high weight) and lower heat generation due to
higher efficiency. Disadvantages include greater complexity, the generation of high-
amplitude, high-frequency energy that the low-pass filter must block to avoid electromagnetic
interference (EMI), and a ripple voltage at the switching frequency and the harmonic
frequencies thereof.
Very low cost SMPS may couple electrical switching noise back onto the mains
power line, causing interference with A/V equipment connected to the same phase. Non-
power-factor-corrected SMPSs also cause harmonic distortion.
Switching regulators are used as replacements for the linear regulators when higher
efficiency, smaller size or lighter weight is required. They are, however, more complicated,
their switching currents can cause electrical noise problems if not carefully suppressed, and
simple designs may have a poor power factor
CHAPTER 3
TRANSISTOR BIASING
3.1 Introduction
3.2Operating point
When no input signal is applied to transistor circuit, and only dc voltages are supplied,
currents IC, IB and voltage VCE will have certain values.
If these values are plotted over the transistor output characteristics, the point we get is called
‘Operating point’. It is also called ‘Quiescent point’ or just Q-point.
In above figure, currents IBQ, ICQ and voltage VCEQ are plotted as point Q. In practice, we have
to choose Q-point according to our requirement. If we want to operate in the middle of active
region,
we may choose Q as Q-point. For Class A amplifier (discussed later) we want Q-point to be
in the middle of active region. If we want to operate near saturation, we may choose Q’ as Q-
point. If we want to operate near cutoff, we may choose C as Q’’-point. Note that if no
biasing is used, Q-point will be in the origin of graph. So, biasing is used to fix the Q-point
according to our need.
Types of bias
• Fixed bias
• Voltage divider bias
Vcc − I B R B −V BE = 0
Rearranging, we get
VCC − V BE
IB = (3.21)
RB
Vcc is constant, VBE is almost constant (0.7V for silicon). So by selecting proper RB, we can
fix IB as required Applying KVL to output side we get:
IC is related to IB by β
This is an equation of straight line with VCE and IC as two variables. This straight line is called
load line Now, output characteristic is also a function of same two variables.
Intersection of load line and output characteristic for particular IB gives the common solution.
This is nothing but Q-point. Figure 3.2.3 shows load line superimposed on output
characteristics, with Q-point marked. Now if we vary RB, Q-point moves along the load line.
If RB is held constant, and RC is varied, then slope of load line varies.
If RB and RC are held constant and VCC is varied, then load line shifts, maintaining same
slope. From these graphs we infer that, with everything else held constant, if RB is increased,
transistor goes towards cutoff, if RB is decreased, transistor goes towards saturation. With
everything else held constant, if RC is increased, transistor goes towards saturation, if RC is
decreased, transistor goes towards active region. With everything else held constant, if VCC is
increased, transistor goes towards active region, if VCC is decreased, transistor goes towards
saturation.
• Q-point is not stable. i.e., if temperature varies, βwill vary, hence IC will vary.
• If transistor is replaced by another transistor having different βthen Q-point will
shift
Uses two resistors R1 and R2 instead of RB. RE is connected between emitter and
ground
Figure 3.2.4: Fig (a) should be replaced by Thevenin’s equivalent circuit shown in fig (b)
VTH is the open circuit voltage between points A & B in fig (a) given by:
VCC R2
VTH = - (3.23)
R1 + R2
RTH is the resistance seen between A & B with VCC replaced by short circuit. See fig 3.13(c).
R1 R2
RTH = R1 || R2 = - (3.24)
R1 + R2
Self bias circuit with its input loop replaced by Thevenin’s equivalent circuit is shown in fig
3.14.
VTH − I B RTH − V BE − I E R E = 0
VTH − V BE
IB = - (3.25)
RTH + ( β + 1) R E
VCC − I C RC −VCE − I E RE = 0
Rearranging, we get
Also,
VC = VCC − I C RC - (3.27)
And, VE = I E RE - (3.28)
Since β>> 1, we have (β+1) ≈ β. If βRE >> RTH, then equation (12) reduces to:
VTH − V BE
IB ≈ - (3.29)
β RE
VTH − V BE
Now, IC = β I B = - (3.30)
RE
Since equation for IC does not contain β, we say that IC is independent of temperature
variation and transistor replacement.
After a transistor has been biased with the Q point near the middle of the load line, we
can couple a small AC voltage in to the base. This produces AC collector voltage which is
proportional to AC input voltage. For applying this voltage a coupling capacitors are used.
Coupling Capacitor:
Consider the RC circuit shown below. Here R represents the input resistance or the load
resistance of the amplifier.
Here a capacitor is used to connect the AC signal source to load R. Since capacitive
reactance is inversely proportional to frequency for DC voltages. This capacitor acts as a
open and at very high frequency it acts as a short circuit. When capacitor is used in this way it
is called Coupling capacitor. For this to work properly its reactance must be very small even
at the lowest frequency of the source.
Where R is the input resistance of amplifier. For example if the frequency variation is 20 Hz
Ex: If R = 2 KΩ, and frequency range is 20 Hz to 20 KHz, the value of the capacitor needed
is
Xc < 0.1 R
<R C= 39.8 µF
Fig shows an AC voltage connected to RC circuit. For high frequency capacitive reactance is
too small and acts like a short circuit. In other words point E is effectively connected to
ground. Similarly by connecting a capacitor in parallel it passes all AC components and
effectively grounding emitter, without disturbing DC conditions.
For bypass capacitor to work effectively, even at the lowest frequency capacitive reactance
must be too small. As a rule Xc < 0.1 RE.
C= , C = 4.2 µF
Small Signal Operation:
When a sinusoidal voltage (ac) is applied it appears across the emitter diode and produces
the sinusoidal variations in VBE . When input voltage increases to positive peak Q point moves
to QA, and when the input voltage reaches negative peak point moves to QB. Thus Q point is
moving along the curve. The size of the AC voltage determines how far the instantaneous
point moves away from the Q point. Large AC voltage produces large variations and small ac
voltage produces smaller variations.
If the movement of the instantaneous Q point is large it will produce distortions because of
the curvature of the graph. To reduce the distortion smaller swing in input voltage is desired.
AC Beta : When AC signal is applied ib and ic also changes and we define AC current gain β
h-parameter model:
∆I C
hfe = forward current gain = h fe = with VCE = const
∆I B
∆VCE
hoe = output conductance = hoe = with I B = const
∆I C
∆V BE
hre = reverse transfer ratio = hre = with I B = const
∆VCE
Transistor Amplifier
If base current is considered as input current, then collector current which is output current is
beta times the input current. This is known as transistor action
By suitably designing transistor circuit, we can get voltage amplification and power
amplification to work as amplifier, transistor should be in active region throughout the input
waveform cycle. i.e., base-emitter junction forward biased, collector-base junction reverse
biased. This is achieved by proper use of biasing circuit Consider the working of the circuit
shown below:
Batteries VBB and VCC ensure that transistor is operating in the active region. It causes
direct currents IB, IC and IE to flow Vin is a weak signal to be amplified. This causes an
alternating current ib to flow through input circuit Total base current iB is sum of IB and ib,
which is alternating current During positive quarter cycle of input waveform, as input voltage
increases, ib and hence iB increases. Due to transistor action, iC also increases.
During negative half cycle of input waveform, E-B junction still remains forward biased
because, VBB is so chosen that it is greater than peak value of Vin. So, during negative half
cycle when iB decreases, iC also decreases, and hence Vout decreases Thus output voltage Vout
will be exact replica of input voltage Vin, but magnified many times However, since current
direction through RL is from bottom to top, the output voltage is 180o out of phase with input.
Resistors R1, R2, RC and RE, and voltage source VCC fix operating point in active region. This
is voltage divider bias, which is already discussed. CC is called coupling capacitor. At input
side, it blocks dc component of input voltage (or output of previous stage) from reaching the
base of transistor. If dc is not blocked, then it will shift the operating point. At output side,
CC blocks dc component from entering into the load (or next stage).
Figure3.3.1: RC coupled amplifier
CE is called emitter by-pass capacitor. It offers low reactance path for ac component, thus
preventing ac component from passing through RE. If ac is allowed to pass through RE, then
it will decrease VBE, bringing down output voltage. RL is the equivalent resistance of the load
connected at output of amplifier.
As explained earlier, when input voltage varies, iB varies and hence iC varies. Thus output
voltage is proportional to input voltage, but amplified.
• Class A amplifier (collector current flows throughout the input signal cycle)
• Class B amplifier (collector current flows only during positive or negative half cycle
of input signal cycle)
• Class C amplifier (collector current flows for less than half cycle of input signal)
• Class AB amplifier (collector current flows for more than half, but less than full cycle
of input signal)
3.5 Gain of amplifier
Vout
AV = - (3.32)
Vin
V
( AV ) dB = 20 log out - (3.33)
Vin
Note that unit less gain AV is negative since Vout is 180o out of phase with Vin. However,
while expressing in terms of dB, negative sign is obviously not taken.
Usually gain of around 100 (approximately) (i.e., 40 dB) can be easily obtained using one
stage amplifier. Sometimes, this may not be sufficient. Especially when input is in micro
volts, we may require gain more than 1000 or 10000.
In such cases, we have to cascade amplifier stages. i.e., connect amplifiers in series, with
output of one stage given to input of next stage.
If high gain is required, then amplifier stages are cascaded as shown in figure 3.18.
However, practically the gain will be less than calculated AV due to loading effects
Fig 3.6.1: Multistage amplifier
Plot of amplifier gain versus frequency of input signal is called frequency response.
Frequency of input signal is increased in steps. At each frequency, voltage gain is
determined and then plotted. It is found that gain is very small at lower frequencies and at
higher frequencies. Gain remains constant at mid frequencies. For audio amplifier, it is
required that gain should be constant over the audio frequency range from 20 Hz to 20
kHz.Bandwidth of amplifier is defined as range of frequencies over which gain is either equal
or greater than 0.707 (or 1/ 2)times the maximum gain Since 20 log (0.707) = – 3,
bandwidth is also defined as range of frequencies over which gain is within 3 dB of
maximum gain (in dB) Fig shows frequency responses of RC coupled amplifier
Here, f1 is called lower cutoff frequency; f2 is called upper cutoff frequency. These are also
called 3 dB frequencies
Note that this is only a qualitative analysis; exact analysis of RC coupled amplifier is
not required at this stage.
Problems
1. An amplifier is known to have a power gain of 40 dB. If the output power is 4
watts, determine the input power.
2. What output power is obtained from an amplifier whose power gain is 55 dB,
when the input power is 1 mW?
3. In a three-stage amplifier, the gain of first stage is 40 dB, gain of second stage is
200 (not in dB) and that of third stage is 0 dB. Find the overall gain of the
amplifier.
CHAPTER 4
OPERATIONAL AMPLIFIERS
4.1 Introduction: “An opamp is a very high gain directly coupled amplifier which can
amplify signals having wide range of frequencies.”
The circuit model of an amplifier is shown in Figure (centre dashed box, with an input
port and an output port). The input port plays a passive role, producing no voltage of its own,
and is modelled by a resistive element Ri called the input resistance. The output port is
modelled by a dependent voltage source AVi in series with the output resistance Ro, where
Vi is the potential difference between the input port terminals. Figure 1 shows a complete
amplifier circuit, which consists of an input voltage source Vs in series with the source
resistance Rs, and an output “load” resistance RL. From this figure, it can be seen that we
have voltage-divider circuits at both the input port and the output port of the amplifier. This
requires us to re-calculate Vi and Vo whenever a different source and/or load is used:
Ri RL
Vi = Vs Vo = AVi
Rs + Ri Ro + R L
R S
+ R o +
INPUT PORT
OUTPUT PORT
V i V o
R i A i V R
V S _ _ L
S O U R C E A M P L I F I E R L O A D
Figure 4.2: Circuit model of an amplifier circuit.
The amplifier model shown in Figure 1 is redrawn in Figure 2 showing the standard
op-amp notation. An op-amp is a “differential-to-single-ended” amplifier, i.e., it amplifies the
voltage difference Vp – Vn = Vi at the input port and produces a voltage Vo at the output
port that is referenced to the ground node of the circuit in which the op-amp is used.
ip
+ +
+ +
V_p Ri V_p
V
i
Ro
Vi
_
+ +
AVi AVi
in Vo _ Vo
_
_
+ +
V_n V_n
The ideal op-amp model was derived to simplify circuit analysis and it is commonly
used by engineers for first-order approximate calculations. The ideal model makes three
simplifying assumptions:
Gain is infinite: A = ∞
Applying these assumptions to the standard op-amp model results in the ideal op-amp
model shown in Figure 3. Because Ri = ∞ and the voltage difference Vp – Vn = Vi at the input
port is finite, the input currents are zero for an ideal op-amp:
in = ip = 0
Vi =Vs
(7)
In addition, because Ro = 0, there is no loading effect at the output port of an ideal op-amp:
Vo = A * Vi (8)
4.4 The Ideal Op-amp: An Ideal Op-Amp has the following characteristics .
Recall that the op-amp amplifies the difference between the two input signals V+ and
V-, i.e. Vo = Aol(V+ - V-). So by this equation, if both input signals are the same then the
output will be zero. However, this is not the case in real op-amps. Any signal common to
both inputs will also be amplified by a common mode gain.
The common mode gain, Acm, is the ratio of the output voltage, Vo, to the common
mode input signal, Vcm, i.e. Vo = AcmVcm. For two independent input signals, the common
mode signal is often taken to be the average of the two input signal voltages, i.e. V o = Acm((V+
+ V-) / 2) So the final gain equation is: Vo = Aol(V+ - V-) + Acm((V+ + V-) / 2) To limit the
effects of common mode gain on the output signal, the open loop gain, Aol, needs to be much
larger than the common mode gain, Acm. The common mode rejection ratio (CMRR) is a
measure of the 'quality' of the op-amp to reject common mode signals (the higher the better)
and is defined as:
Vo = ViÃol(1 + 1/CMRR)
where Ãcl is the 'ideal' closed loop gain, i.e. Ãcl = 1 + R2/R1
Use the tool below to see the effect of common mode gain on the non-inverting amplifier.
Practical considerations: common-mode gain
As stated before, an ideal differential amplifier only amplifies the voltage difference
between its two inputs. If the two inputs of a differential amplifier were to be shorted together
(thus ensuring zero potential difference between them), there should be no change in output
voltage for any amount of voltage applied between those two shorted inputs and ground:
Voltage that is common between either of the inputs and ground, as "Vcommon-
mode" is in this case, is called common-mode voltage. As we vary this common voltage, the
perfect differential amplifier's output voltage should hold absolutely steady (no change in
output for any arbitrary change in common-mode input). This translates to a common-mode
voltage gain of zero.
The operational amplifier, being a differential amplifier with high differential gain,
would ideally have zero common-mode gain as well. In real life, however, this is not easily
attained. Thus, common-mode voltages will invariably have some effect on the op-amp's
output voltage.
The performance of a real op-amp in this regard is most commonly measured in terms
of its differential voltage gain (how much it amplifies the difference between two input
voltages) versus its common-mode voltage gain (how much it amplifies a common-mode
voltage). The ratio of the former to the latter is called the common-mode rejection ratio,
abbreviated as CMRR:
An ideal op-amp, with zero common-mode gain would have an infinite CMRR. Real
op-amps have high CMRRs, the ubiquitous 741 having something around 70 dB, which
works out to a little over 3,000 in terms of a ratio. Because the common mode rejection ratio
in a typical op-amp is so high, common-mode gain is usually not a great concern in circuits
where the op-amp is being used with negative feedback. If the common-mode input voltage
of an amplifier circuit were to suddenly change, thus producing a corresponding change in
the output due to common-mode gain, that change in output would be quickly corrected as
negative feedback and differential gain (being much greater than common-mode gain)
worked to bring the system back to equilibrium. Sure enough, a change might be seen at the
output, but it would be a lot smaller than what you might expect.
The common-mode rejection ratio (CMRR) of an amplifier (or other device) measures
the tendency of the device to reject input signals common to both input leads. A high CMRR
is important in applications where the signal of interest is represented by a small voltage
fluctuation superimposed on a (possibly large) voltage offset, or when relevant information is
contained in the voltage difference between two signals. (An example is audio transmission
over balanced lines.)
where Ad is the differential gain and As is the common-mode gain. This is a very important
specification, as it indicates how much of the common-mode signal will appear in your
measurement. The value of the CMRR often depends on signal frequency as well, and must
be specified as a function thereof.
CMRR is often important in reducing noise on transmission lines. For example, when
measuring a thermocouple in a noisy environment, the noise from the environment appears as
an offset on both input leads, making it a common-mode voltage signal. The CMRR of the
measurement instrument determines the attenuation applied to the offset or noise.
Applications of OPAMP:
Inverting amplifier:
Assuming that the input difference is small, we can write KCL at the inverting node:
(Notice the little red dot at the inverting node in the circuit diagram.) (Note also, that we
have defined two voltages, V1 and Vout that are both measured with respect to the ground.)
Here's the KCL equation using the assumption that the voltage at the amplifier input - at
the input node - is zero.
I 1 + I0 = 0
Technically, we can write KCL in terms of all the voltages involved (taking V+ and V- as
the voltages - with respect to ground - at the "+" and "-" terminals respectively). Doing
that we obtain:
However, since we assume that there is no voltage difference between V+ and V-, we
can replace V- with V+ and we have the inverting input terminal connected to ground, so
V- = 0. That means we get:
V1/R1 + Vout / R0 = 0
Note that the situation where V+ 0 happens so often that it has a common name. The non-
inverting terminal in a connection like this - where the inverting input terminal is connected
to ground - is called a virtual ground.
Vout = - V1 R0 / R1
There are two things to note about this expression for the output voltage.
The input voltage is multiplied by a constant that depends only upon the two resistors, R 0 and
R1. Properties of the amplifier that are used in the argument for this expression are:
Very large gain (approaching infinity) Very large input resistance between the two input
terminals
Non-inverting amplifier:
Rin
Expression for gain Vini = Vout and
R f + Rin
Vout Rf
= 1 +
Vin Rin
From these calculations, we can see that the effective voltage gain of the noninverting
amplifier is still set by the resistance ratio Rf/Rin, but is one greater than this ratio. Thus, if
the two resistors are of equal value, the non-inverting gain will be 2, rather than 1. To get a
non-inverting gain of 1, we can simply eliminate both Rf and Rin, and connect the output
directly to the (-) input. We would eliminate Rs at the same time, or else use equal resistances
in series with the two inputs.
Voltage follower:
When
Output is inverted, Input impedance Zn = Rn, for each input (V − is a virtual ground)
Subtractor:
The subtractor provides an output which is equal to the difference of the two input
signals or proportional to their difference . For minimum offset error R1 || R2 = R3 || R4
Integrator:
(where Vin and Vout are functions of time, V initial is the output voltage of the integrator at
time t = 0.) Note that this can also be viewed as a type of electronic filter
Differentiators:
Comparator :
Compares two voltages and outputs one of two states depending on which is greater
Problems:
1. Determine the gain of the amplifier shown in fig below given R0=100Ώ R1=4.7k Ώ
2. For the circuit of non inverting amplifier with R1=10 k Ώ and R0=100k Ώ determine
3.In this circuit, you have it set up for a gain of -10. The input voltage is 0.24V. What is the
output voltage?
4.For the same conditions as in Problem 2, the input is changed to -0.35 volts. What is the
output voltage now?
An operational amplifier (op-amp) has a well balanced difference input and a very
high gain. The parallels in the characteristics allows the op-amps to serve as comparators in
some functions.[1]
A comparator is designed to produce well limited output voltages that easily interface
with digital logic. Compatibility with digital logic must be verified while using an op-amp as
a comparator.
Schmitt trigger:
Schmitt trigger is a comparator circuit that incorporates positive feedback.In the non-
inverting configuration, when the input is higher than a certain chosen threshold, the output is
high; when the input is below a different (lower) chosen threshold, the output is low; when
the input is between the two, the output retains its value. The trigger is so named because the
output retains its value until the input changes sufficiently to trigger a change. This dual
threshold action is called hysteresis, and implies that the Schmitt trigger has some memory.
In fact, the Schmitt trigger is a bistable multivibrator.
The symbol for Schmitt triggers in circuit diagrams is a triangle with an inverting or non-
inverting hysteresis symbol. The symbol depicts the corresponding ideal hysteresis curve.
Schmitt triggers are commonly implemented using a comparator] connected to have positive
feedback (i.e., instead of the usual negative feedback used in operational amplifier circuits).
For this circuit, the switching occurs near ground, with the amount of hysteresis controlled by
the resistances of R1 and R2:
The comparator extracts the sign of the difference between its two inputs. When the non-
inverting (+) input is at a higher voltage than the inverting (−) input, the comparator output
switches to +VS, which is its high supply voltage. When the non-inverting (+) input is at a
lower voltage than the inverting (−) input, the comparator output switches to -VS, which is its
low supply voltage. In this case, the inverting (−) input is grounded, and so the comparator
implements the sign function – its 2-state output (i.e., either high or low) always has the same
sign as the continuous input at its non-inverting (+) terminal.
Because of the resistor network connecting the Schmitt trigger input, the non-inverting (+)
terminal of the comparator, and the comparator output, the Schmitt trigger acts like a
comparator that switches at a different point depending on whether the output of the
comparator is high or low. For very negative inputs, the output will be low, and for very
positive inputs, the output will be high, and so this is an implementation of a "non-inverting"
Schmitt trigger. However, for intermediate inputs, the state of the output depends on both the
input and the output. For instance, if the Schmitt trigger is currently in the high state, the
output will be at the positive power supply rail (+VS). V+ is then a voltage divider between
Vin and +VS. The comparator will switch when V+=0 (ground). Current conservation shows
that this requires
and so Vin must drop below to get the output to switch. Once the comparator output
and the maximum value of the output M is the power supply rail.
The output characteristic has exactly the same shape of the previous basic configuration, and
the threshold values are the same as well. On the other hand, in the previous case, the output
voltage was depending on the power supply, while now it is defined by the Zener diodes. In
this configuration, the output levels can be modified by appropriate choice of Zener diode,
and these levels are resistant to power supply fluctuations (i.e., they increase the PSRR of the
comparator). The resistor R3 is there to limit the current through the diodes, and the resistor
R4 minimizes the input voltage offset caused by the comparator's input leakage currents.
Feedback concepts
Introduction:
Feedback plays an important role in electronic circuits and the basic parameters
such as input resistance, output resistance, current gain or voltage gain and bandwidth
Feedback The process of combining a fraction of the output back to its input is called
feedback. The network coupling employed for the process of feedback is called feedback
network.
Basic
Input Vi amplifier Output
Vs A
Feedback
network
βVo β
It consist of an amplifier with a gain A and a feedback network with feedback
fraction β and drives an error signal β Vo. Depending upon whether the feedback energy
aids or opposes the input signal, there are two basic types of feed backs in amplifiers. They
are positive feedback and negative feedback.
Positive feedback:
When the feedback is in phase to the input the input signal increases this type of
feedback is called positive feedback.
V s, is source signals
Positive feedback increases the gain of amplifier and also increases noise, distortion and
reduces stability of an amplifier. Because of these disadvantages, +ve feedback is seldom
used in amplifiers. But +ve feedback is used in oscillators.
Negative feedback:
When the feedback is in opposition to the input, the input signal reduces this type of
feedback is called Negative feedback or degenerative feedback.
Here Vi = Vs – Vf or Ii = Is - If
Negative feedback reduces gain of the amplifier. It also reduces noise, distortion and
instability and increases the bandwidth. Due to these advantages negative feedback is used in
amplifiers.
Basic Amp
I/P Is O/P
Mixer A Sampler
Feedback
N/W
The output quantity (current or voltage) is sampled by a suitable sampler which is of two
types current or voltage, and fed to the feedback network. The output of the feedback
network is combined with source signal through a mixer and fed to the basic amplifier. Mixer
also known as comparator is of two types, namely series mixer and shunt mixer.
If ------->feedback signal (V or I)
Af = Io/Is = Io/Ii – If [ Ii = Is + If ]
= = = A/1 – Aβ
| Af | > |A|
When |Aβ| =1 , Af = ∞
Af = Io/Is = Io/Ii + If [ Ic = Is - If ]
= = = A/(1 + Aβ)
Difference between +ve and -ve feedback
Input and output resistance changes Input and output resistance changes
Oscillations whose amplitude keeps decreasing with time are called damped
oscillations and oscillators whose amplitude remains constant are called undamped or
sustained oscillations. Oscillators use positive feedback for producing sustained oscillations.
Tank / oscillatory circuit consist of an inductor (or resistor) in parallel with a capacitor.
The frequency of oscillations in the circuit depends upon the values of L, C or R, C
[f=1/2π√LC or f = 1 / 2πRC].
Amplifier receives DC power from the battery and converts it into AC power for
supplying it to the tank circuit. Oscillations of that tank circuit are fed to the amplifiers which
are amplified due to the active devices amplifying action.
Feedback circuit supplies a part of the output energy to the tank circuit in correct phase
to meet the losses in order to produce undamped oscillations.
Types of oscillators:
555 Timer
The 8-pin 555 timer must be one of the most useful ICs ever made and it is used in many
projects. With just a few external components it can be used to build many circuits, not all of
them involve timing.
The 555 can be used with a supply voltage (Vs) in the range 4.5 to 15V (18V absolute
maximum).
Square wave generator:
Square wave outputs are generated when the op-amp is forced to operate in saturation region.
That is the output of the op-amp repeatedly swings between positive (+Vsat ≈ +VCC) and
negative saturation (-Vsat ≈ -VEE), resulting in a square wave output. This square wave
generator is also known as free-running or astable multivibrator. The output of the op-amp
will be either positive or negative depending on whether the differential voltage vid is
negative or positive respectively.
Fig : (a)Square Wave generator (b) waveform across output and capacitor
An electric filter is often a frequency selective circuit that passes a particular band of
frequencies and blocks or attenuates the signals of frequencies outside this band.
A passive filter uses only passive elements such as resistors, capacitors and inductors. Active
filters on the other hand use transistors and op-amps in addition to the passive elements. The
elements used dictate the operating frequency range of the filters. In audio frequencies,
inductors are not often used as they are large, costly and may dissipate more power. Also
inductors emit magnetic field.
1. Gain and frequency adjustment flexibility: Since the op-amp is providing some gain
the input signal is not attenuated as in case of the passive filters. Aslo they are easier
to tune and adjust.
2. No loading problem: Because of high input resistance and low output resistance the
active filter does not cause loading of the input source and the output load.
3. Cost: Typically, they are cheaper due to availability of cheap op-amps and the
absence of inductors in the circuit.
Although active filters are most extensively used in the field of communications and signal
processing, they are employed in one form or another in almost all sophisticated electronic
systems. Radio, television, telephone, radar, space satellites, and biomedical equipment are
but a few systems that employ active filters. The most commonly used filters are these:
Low-pass filter - allows low frequencies to pass and attenuates high frequencies
High pass filter - allows high frequencies to pass and attenuates low frequencies
Band pass filter - allows a range of frequencies to pass
Band stop filter - attenuates a range of frequencies and allows all frequencies not within the
range to pass
A low-pass filter has constant gain for low frequency signals but attenuates signals with
frequencies higher than the cutoff frequency fH. At fH the gain is down 3dB and decreases
further as frequency increases. The frequencies between 0 Hz and fH are known as passband
frequencies while the range of frequencies beyond fH are attenuated and are therefore called
the stop-band frequencies.
A high-pass filter with a stopband 0 < f < fL and a passband f > fL is shown in figure.b. Here
fL is the lower cut-off frequency and f is the operating frequency.
A band-pass filter has a passband between two cut-off frequencies fH and fL where fH > fL
and two stopbands at 0 < f < fL and f > fH. The bandwidth of the band-pass filter is,
therefore, equal to fH – fL.
Band-stop filter is exactly opposite to the band-pass filter in performance i.e., it has a
bandstop between two cut-off frequencies fH and fL and two passbands, 0 < f < fL and f > fH..
This filter passes all frequencies equally well (i.e. the output and input voltages are equal in
magnitude for all frequencies) but with the phase shift between the two; phase shift being a
function of the input frequency. The highest frequency up to which the magnitudes of the
input and output remain equal depends on the unity gain BW of the op-amp. At this
frequency, however, the phase shift between the input and output is maximum.
First-order low-pass Butterworth filter:
Fig shows first-order low-pass Butterworth filter that uses an RC network for filtering. Note
that the op-amp is used in non-inverting configuration and hence it does not load down the
RC network. Resistirs R1 and RF determine the gain of the filter.
f = frequency of the input signal fH is the high (or upper) cutoff frequency of the filter.
fH =
The gain magnitude and phase angle equations for the filter can be obtained as
The operation of the low-pass filter can be verified from the gain magnitude equation:
Fig shows a first-order high-pass filter that uses an RC network for filtering. The circuit is
formed by interchanging the positions of R and C from the low-pass filter circuit.
f = frequency of the input signal and fL is the lower cutoff frequency of the filter.
fL =
Band-pass filter:
A band pass filter has a passband frequency between two cutoff frequencies fH and fL such
that fH > fL. Any input frequency outside the passband frequencies is attenuated. Basically
there are two types of band-pass filters: 1. Narrow band-pass and 2.wide band-pass filters.
Unfortunately, there is no set dividing line between the two.
However, a band-pass filter is defined as a wide band-pass if its figure of merit or quality
factor Q is less than 10 while the band-pass filters with Q > 10 are called the narrow band-
pass filters. Thus Q is a measure of selectivity, meaning the higher the value of Q the more
selective is the filter, or the narrower is the bandwidth (BW). The relationship between Q, 3-
db bandwidth, and the centre frequency fC is given by
For a wide band-pass filter the centre frequency can be defined as.
In a narrow band-pass filter, the output voltage peaks at the centre frequency fc.
A wide band-pass filter can be formed by simply cascading high-pass and low-pass sections
and is generally the choice for simplicity of design and performance though such a circuit can
be realized by a number of possible circuits. To form a ± 20 db/ decade band-pass filter, a
first-order high-pass and a first-order low-pass sections are cascaded; for a ± 40 db/decade
band-pass filter, second-order high- pass filter and a second-order low-pass filter are
connected in series, and so on. It means that, the order of the band-pass filter is governed by
the order of the high-pass and low-pass filters
.
Narrow band-pass filter
A narrow band-pass filter employing multiple feedbacks is depicted in figure. This filter
employs only one op-amp, as shown in the figure. In comparison to all the filters discussed so
far, this filter has some unique features that are given below.
1. It has two feedback paths, and this is the reason that it is called a multiple-
feedback filter.
Generally, the narrow band-pass filter is designed for specific values of centre frequency fc
and Q or fc and BW. The circuit components are determined from the following relationships.
For simplification of design calculations each of C1 and C2 may be taken equal to C.
R1 = Q/2π fc CAf
R2 =Q/2π fc C(2Q2-Af)
and R3 = Q / π fc C
Af = R3 / 2R1
R’2 = R2 [fc/f’c]2
Notch filters are most commonly used in communications and biomedical instruments for
eliminating the undesired frequencies.
A mathematical analysis of this circuit shows that it acts as a lead-lag circuit with a phase
angle, shown in fig. (b). Again, there is a frequency fc at which the phase shift is equal to 0°.
In fig. (c), the voltage gain is equal to 1 at low and high frequencies. In between, there is a
frequency fc at which voltage gain drops to zero. Thus such a filter notches out, or blocks
frequencies near fc. The frequency at which maximum attenuation occurs is called the notch-
out frequency given by
fn = Fc = 2πRC
Notice that two upper capacitors are C while the capacitor in the centre of the network is 2 C.
Similarly, the two lower resistors are R but the resistor in the centre of the network is 1/2 R.
This relationship must always be maintained.
All-pass filter is that which passes all frequency components of the input signal without
attenuation but provides predictable phase shifts for different frequencies of the input signals.
The all-pass filters are also called delay equalizers or phase correctors. An all-pass filter with
the output lagging behind the input is illustrated in figure.
The output voltage Vout, of the filter circuit shown in fig, can be obtained by using the
superposition theorem
From equations given above it is obvious that the amplitude of v out / vin is unity, that is |vout | =
|vin| throughout the useful frequency range and the phase shift between the input and output
voltages is a function of frequency.
By interchanging the positions of R and C in the circuit, the output can be made leading the
input. These filters are most commonly used in communications. For instance, when signals
are transmitted over transmission lines (such as telephone wires) from one point to another
point, they undergo change in phase. To compensate for such phase changes, all-pass filters
are employed.
Chapter 4
DIGITAL ELECTRONICS
In analog system, the output can be continuously controlled by the input & the output is
linearly proportional to the input. In digital system, the digital logic used only two values,
either HIGH or LOW. i.e. they have only two discrete values and are called BINARY. The
binary may be either logic 0 or logic ‘1’. A logic value of ‘0’ or ‘1’ is often called as
BINARY DIGIT or BIT.
Number System: Many number systems are used in digital technology. Most common are
binary, decimal, octal & hexadecimal system.
Binary Number system: A number system that uses only two digits ‘0’&’1’ is called binary
number system. The binary umber system is also called as Base 2 system or Radix 2 system.
Examples: (100010)2
(0.1011)2
1. (100010)2=0×20+1×21+0×22+0×23+0×24+1×25
=0+2+0+0+0+32
=(34)10
2. (0.1011)2=1×2-1+0×2-2+1×2-3+1×2-4
=0.5+0+0.125+0.0625
=(0.6875)10
3. (10101.011)2
Integer part: (10101)2=1×20+0×21+1×22+0×23+1×24
=1+0+4+0+16 = (21)10
= (0.375)10
= (21.375)10
Octal Number System: A number system that uses 8 digit (0-7) is called an octal number
system. It has base 8. Example: (723)8, (676)8
Hexadecimal Number System: The hexadecimal number system has base 16. It has 16
distinct digit symbols. It uses the digits 0-9 & letters A,B,C,D,E,F as 16 digit symbols.
8 4 2 1 (weights)
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
10 1010=A
11 1011=B
12 1100=C
13 1101=D
14 1110=E
15 1111=F
Octal Numbers Binary Equivalent number
4 2 1 (weights)
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111
Convert the following octal number into decimal number system
1. (2376)8 = (?)10
= 2×83+3×82+7×81+6×80
= 1024+192+56+6
= (1278)10
2. (1234.567)8=1×83+2×82+3×81+4×80 +5×8-1+6×8-2+7×8-3
=512+128+24+4+0.625+0.09375+0.01367
= (668.7324219)10
1. (269)16=2×162+6×161+9×160
= 2×256+96+9
= (617)10
2. 2B8D.E2)16=2×163+11×162+8×161+13×160 +14×16-1+2×16-2
= 8192+2816+128+13+0.875+0.0078125
= (11149.88281)10
The given decimal number is repeatedly divided by 2, which is the base number of
binary system till quotient becomes ‘0’ and collect the remainder from bottom to top.
To convert the fractional part into binary, multiply fraction by 2 repeatedly, record
any carry in integer place. The string of integer obtained from top to bottom gives the
equivalent fraction in binary number system.
2∠734
2∠367 −−0
1. (734)10=(X)2 2∠183 −−1
2∠91 −−1
2∠45 −−1
2∠22 −−1
2∠11 −−0
2∠5 −−−1
2∠2 −−−1
1 −−−−−0 ↑
(734)10 = ( 1011011110)2
2. (0.705)10
0.705×2=1.410 ---1
0.410×2=0.820 ---0
0.82×2= 1.64------1
0.64×2= 1.28------1
0.28×2= 0.56------0
0.56×2=1.12-------1
0.12×2=0.24-------0
0.24×2=0.48-------0
0.48×2=0.96-------0
0.96×2=1.92-------1
(41)10 = (101001)2
0.915×2=1.830---1
0.830×2=1.660---1
0.660×2=1.320---1
0.32×2=0.64------0
0.64×2= 1.28-----1
(0.915)10 = (11101)2
(41.915)10= (101001.11101)2
For traction part repeatedly multiplied by 8, record carry in integer place & take the
string of integer from top to bottom.
1.(2003)10=(X)8
8∠2003
8∠250 − −3
8∠31 − − − 2
3 −−− −−7 ↑
2.(0.12)10 = (X)8
0.12×8=0.96---0
0.96×8=7.68---7
0.68×8=5.44---5
0.44×8=3.52---3
0.52×8=4.16---4
(0.12)10=(0.07534)8
3. (632.97) 10=(?)8
8∠632
8∠79 − − −0
8∠9 − − −−7
1 − −− − −−1 ↑
(632) 10=(1170)8
0.97×8=7.76---7
0.76×8=6.08---6
0.08×8=0.64---0
0.64×8=5.12---5
0.12×8=0.96---0
(0.97)10 =(0.76050) 8
(632.97)10= (1170.76050)8
For traction part repeatedly multiplied by 16, record carry in integer place & take the string of
integer from top to bottom.
1. (0.368)10
0.368×16=5.888---5
0.888×16=14.208-14-E
0.208×16=3.328---3
0.328×16=5.248---5
0.248×16=3.968---3
(0.368)10=(0.5E353)16
2. (22.64)10= (?)8
16 ∠22
1 − − − − − −6 ↑
(22)10= (16)16
0.64×16=10.24---10-A
0.24×16=3.84-----3
0.84×16=13.44—13-D
0.44×16=7.04---7
0.04×16=0.64---0
(22.64)10=(16.A3D70)16
Conversion from Octal number system into Binary number system:
When an octal number is to be converted to its equivalent binary number, each of its digits is
replaced by equivalent group of three binary digits.
1. (632)8
6 3 2
110 011 010
So, (632)8=(110011010)2
2. (7423.245)8
7 4 2 3 . 2 4 5
111 100 010 011 . 010 100 101
(7423.245)8= (111100010011.010100101)2
To convert, Starting from the binary point, the binary digits are arranged in groups of
three on both sides. Each in group of binary digit is replaced by its octal equivalent.
Note: 0’s can be added on either side, if needed to complete a group of three.
1. (011101.110)2=(?)8
(011101.110)2= (35.6)8
2. (11101101110.11111)2
011 101 101 110 . 111 110
3 5 5 6 . 7 6
(11101101110.11111)2 =(3556.72)8
1.(347.28)16
3 4 7 . 2 8
0011 0100 0111 . 0010 1000
(347.28)16= (001101000111.00101000)2
2. (8BE6.7A)16
8 B E 6 . 7 A
1000 1011 1110 0110 . 0111 1010
(8BE6.7A) 16 = (1000101111100110.01111010)2
To convert, Starting from the binary point, the binary digits are arranged in groups of
four on both sides. Each in group of binary digit is replaced by its hexadecimal equivalent.
Note: 0’s can be added on either side, if needed to complete a group of four.
1.(1011011110111110.11100011)2= (?)16
(1011011110111110.11100011)2= (B7BE.E3)16
2. (110111101.01)2=(?)16
(110111101.01)2=(1BD.4)16
Write down the three bit binary equivalent of octal digit and then rearranging into
group of four bits with ‘0’s added on either side of decimal point, if needed to complete the
group of four.
1.(46) 8 = (?)16
Octal equivalent 4 6
100 110
2 6
(46) 8 = (26)16
2. (764.352) 8 = (?)16
Octal equivalent 7 6 4 . 3 5 2
111 110 100.011 101 010
(764.352) 8 = (1F4.750)16
First write down the 4 bit binary equivalent of hexadecimal digit and then rearranging
into group of three bit each.
1.(2AB.9) 16 = (?)8
Hexadecimal 2 A B . 9
equivalent
0010 1010 1011 . 1001
1 2 5 3 . 4 4
(2AB.9) 16 = (1253.44)8
2. (3FC.82) 16 = (?)8
Hexadecimal 3 F C . 8 2
equivalent
0011 1111 1100 . 1000 0010
1 7 7 4 . 4 0 4
(3FC.82) 16 = (1774.404)8
BCD Numbers:
The Binary Coded Decimal (BCD) is a combination of four binary digits that
represent decimal numbers. It is also called 8421 code. It has four bits and represents the
decimal digits 0 to 9. Below table gives the BCD codes for the decimal number 0 to 15.
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
10 0001 0000
11 0001 0001
12 0001 0010
13 0001 0011
14 0001 0100
15 0001 0101
11011100001001
0 0 1 1
+0 +1 +0 +1
The sum of two 1’s gives binary ‘10’ i.e.2, there is a carry. The carry is taken to the next
higher column.
1.(1010)2+(0111)2
1010 =10
+0111 =7
10001 =17
(1010)2+(0111)2=(10001)2
2. (101)2+(011)2
101=5
+011=3
1000=8
(101)2+(011)2=(1000)2
Addition in Octal number System: Add the digit in each column in decimal and convert
this sum into octal. Write the sum in that column and carry the carry term to the next higher
significant column.
3 3 4 . 6 5
6 7 1 . 1 4
10 10 6 . 8 9
C=1 S=2 C=1 S=2 C=0 S=6 . C=1 S=0 C=1 S=1
Add the digit in each column in decimal and convert this sum into hexadecimal
number. Write the sum in that column and carry term to the next higher significant column.
7 A B . 6 7
1 5 C . 7 1
9 16 23 . 13 8
C=0 S=9 C=1 S=0 C=1 S=7 . C=0 S=D C=0 S=8
Problems:
(11.111) 2
(65.45) 10
(106) 10
(4673) 8
(34.125) 8
(103.45) 8
(890) 10
(453.023) 10
(111110001) 2
(01110.1100) 2
(34) 8
(482) 8
(17333.66) 8
7. Convert from hexadecimal to decimal number system
(ABC.DE) 16
(B6A) 16
(3A1.4) 16
(ABC) 16
(00110111) 2
(11001110) 2
(11010.01101) 2
(B4D) 16
(7AF4) 16
(156.8F) 16
(1C00)16
(222) 8+(333) 8
(25.36) 8+(37.11) 8
(12) 8+(20) 8
(9349) 16+(AACE) 16
(AA.BB) 16+(BB.CC) 16
(A0FC) 16+(B75F) 16
Complements:
The subtraction operation and logical manipulations become easy in digital computers
by using the concept of complements.
For a given number ‘N’ in base-‘r’, we can define two types of complements
r’s complement
(r-1)’s complement
1’s complement:
1’s form of any binary number can be obtained by replacing 0’s by 1’s and 1’s by 0’s.
Example:
10101 01010
11100 00011
1111 0000
1101—minuend
1000— subtrahend
1 1 0 1
+ 0 1 1 1
1 0 1 0 0
End carry Add to LSB +1
0 1 0 1
1111—minuend
0101— subtrahend
1 1 1 1
+ 1 0 1 0
1 1 0 0 1
End carry Add to LSB +1
1 0 1 0
6=0110—minuend
14=1110— subtrahend
0 1 1 0
+ 0 0 0 1
No End
0 1 1 1
carry
Take 1’s complement of the 0111 & place negative sign in front of it =-1000
2’s complement:
To find the 2’s form of any binary number, obtain the 1’s complement of the given
number and then add ‘1’ to the LSB.
(100100)2
+1
011100
Step3: (a) If an end carry occurs, discard it. (b) If an end carry doesn’t occur, take 2’s
complement of the number obtained in step2 and place a negative sign in front of it.
1.(1111)2-(1100)2
1111—minuend
1100— subtrahend
1 1 1 1
+ 0 1 0 0
Neglect 0 0 1 1
end carry
(1111)2-(1100)2=(0011)2
2.(15)10-(31)10
(1111)2-(11111)2
1111—minuend
11111— subtrahend
0 1 1 1 1
+ 0 0 0 0 1
No end
1 0 0 0 0
carry
So, take the 2’s complement of the answer and place negative sign in front of it,
i.e.= -(10000)2
(1111)2-(11111)2= -(10000)2
9’s complement:
The 9’s complement of a decimal number is formed by subtracting each digit form 9.
9 9 9 9
8 1 4 7
1 8 5 2
Step2: Inspect the result obtained in step1 for an end carry. (a) If an end carry occurs, add 1
to the least significant bit. (end round carry) (b) If an end carry doesn’t occur, take 1’s
complement of the number obtained in step1 and place a negative sign in front of it.
1. ( 487)10 - (354)10
487—minuend
354— subtrahend
4 8 7
+ 6 4 5
1 1 3 2
End carry Add to LSB +1
1 3 3
213—minuend
546— subtrahend
2 1 3
+ 4 5 3
No 6 6 6
End carry
Take the 9’s complement of the answer (666)10 and place the negative sign in front of it.
i.e.= -(333)10
10’s complements:
The 10’s complement of the decimal number is equal to 9’s complement of number plus 1.
999
-731
268 9’s complement
+1
Step3: (a) If an end carry occurs, discard it. (b) If an end carry doesn’t occur, take 10’s
complement of the number obtained in step2 and place a negative sign in front of it.
1. (347)10-(265)10
347—minuend
265— subtrahend
3 4 7
+ 7 3 5
1
0 8 2
Neglect end carry
(347)10-(265)10=(082)10
2. (23)10-(64)10
23—minuend
64— subtrahend
2 3
+ 3 6
No end carry 5 9
So, take the10’s complement of the answer and place negative sign in front of it, i.e.= -(41)10
Problems:
1. Laws of complementation: The term complement means invert. i.e. to change 0’s to
1’s and 1’ to 0’s. The following are the laws of complement. 0 =1; 1 = 0; A =A.
2. “ OR” laws
0+0=0; 0+1=1; 1+0=1;1+1=1
3. “ AND’ laws
0.0=0; 0.1=0;1.0=0; 1.1=1; A. A =0; A.A=A
Commutative Law:
Property 1: This states that the ord3r in which the variables OR’ed makes no difference in
output. i.e. A+B=B+A
A B A+B B A B+A
0 0 0 0 0 0
0 1 1 = 1 0 1
1 0 1 0 1 1
1 1 1 1 1 1
Property 2: This property of multiplication states that the order in which the variables are
AND’ed makes no difference in the output. i.e. A.B=B.A
A B A.B B A B.A
0 0 0 0 0 0
0 1 0 = 1 0 0
1 0 0 0 1 0
1 1 1 1 1 1
Associative property:
Property1: This property states that in the OR’ing of the several variables, the result is same
regardless of grouping of variables. For three variables i.e.(A OR’ed with B)or’ed with C is
same as A OR’ed with (B OR’ed with C)
0 0 0 0 0 0 0
0 0 1 0 1 1 1
0 1 0 1 1 1 1
0 1 1 1 1 1 = 1
1 0 0 1 0 1 1
1 0 1 1 1 1 1
1 1 0 1 1 1 1
1 1 1 1 1 1 1
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 = 0
1 0 0 0 0 0 0
1 0 1 0 0 0 0
1 1 0 1 0 0 0
1 1 1 1 1 1 1
Distributive property:
1 2 3 4 5 6 7 8
0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 1 0 0 0 0
0 1 1 1 0 0 0 0
1 0 0 0 0 0 0 0
1 0 1 1 1 0 1 1
1 1 0 1 1 1 0 1
1 1 1 1 1 1 1 1
Property 2: A+ A B = A+B
A B A AB A+ A B A+B
0 0 1 0 0 0
0 1 1 1 1 = 1
1 0 0 0 1 1
1 1 0 0 1 1
Duality:
The important property to Boolean algebra is called Duality principle. The Dual of
any expression can be obtained easily by the following rules.
Examples:
0 =1≡ 1 =0
X +0=X ≡ X .1=X
X+Y=Y+X ≡ X.Y=Y.X
X+1=0 ≡ X.0=1
De Morgon’s Theorems:
It states that “ the complements of product of two variables equal to sum of the
complements of individual variable”.
i.e. AB = A + B
A B A B A.B AB A+B
0 0 1 1 0 1 1
0 1 1 0 0 1 ≡ 1
1 0 0 1 0 1 1
1 1 0 0 1 0 0
De Morgon’s Second Theorem:
i.e. A + B = A . B
A B A B A+B A +B A.B
0 0 1 1 0 1 1
0 1 1 0 1 0 ≡ 0
1 0 0 1 1 0 0
1 1 0 0 1 0 0
1. X Y Z+ X YZ
= X Z[ Y +Y]
= X Z[1]= X Z
2. f=X( X +Y)
=X X +XY = 0+XY= XY
3. f = B(A+C)+C
=BA+BC+C
=BA+C(1+B)
=BA+C
4.XY+XYZ+XY Z + X YZ
=XY(Z+ Z )+XYZ+XY Z + X YZ
XYZ+XY Z +XY Z + X YZ+XYZ
XYZ(1+1)+XY Z (1+1)+ X YZ
XYZ+XY Z + X YZ
XY(Z+ Z )+ X YZ
XY+ X YZ
Y(X+ X Z)
Y(X+Z)
5.XYZ+ X Y + XY Z
=Y( X + X Z )+ XY Z
= Y( X + Z )+ XY Z
= Y X +Y Z + XY Z
=Y X +Y(Z+ X Z )
=Y X +Y(Z+ X)
=Y(Z+ X +X)
=Y(Z+1)
=Y
6. Y(W Z +WZ)+XY
=YW Z +YWZ+XY
=YW( Z +Z)+XY
=YW+XY
=Y(W+X)
=BC+A B C+AB C
=C[B+ B A]+AB C
=C[B+A]+AB C
BC+AC=AB C
=BC+A[C+ C B]
=BC+A[C+B]
= AB+BC+CA = RHS
8. (A+B)(A+C)=A+BC
(A+B)(A+C)= A.A+A.C+B.A+B.C
=A+AC+A.B+B.C
=A(1+C)+BA+BC
= A.1+BA+BC
=A(1+B)+BC
= A+BC
Logic Gates:
It is an electronic circuit, which makes logic decisions. A logic gate is a digital circuit
with one or more input signal and only one output signal. All input or output signals either
low voltage or high voltage. A digital circuit is referred to as logic gate for simple reason i.e.
it can be analyzed based on Boolean algebra.
To make logical decisions, three gates are used. They are OR, AND and NOT gate.
These logic gates are building blocks, which are available in the form of IC.
The input and output of the binary variables for each gate can be represented in a
tabular column or truth table.
OR Gate:
If A & B are the input variables of an OR gate and c is its output, then A+B. similarly
for more than two variables, the OR function can be expressed as Y=A+B+C.
Input Output
A B Y= A+B
0 0 0
0 1 1
1 0 1
1 1 1
Realization of OR gate using diodes:
Two input OR gate using "diode-resistor" logic is shown in figure below. Where X, Y
are the inputs and F is the output.
D 1
X
F
Y
R L
D 2
• If X = 0 and Y = 0, the both the diodes D1 and D2 are reverse biased and thus both
the diodes are in cut-off and thus F is low.
• If X = 0 and Y = 1, D1 is reverse biased, thus does not conduct. But D2 is forward
biased, thus conducts and thus pulling F to HIGH
• If X = 1 and Y = 0, D2 is reverse biased, thus does not conduct. But D1 is forward
biased, thus conducts and thus pulling F to HIGH.
• If X = 1 and Y = 1, the both the diodes D1 and D2 are forward biased and thus both
the diodes conduct and thus F is HIGH
AND Gate:
The AND gate performs logical multiplication, commonly known as AND function.
The AND gate has two or more inputs and a single output. The output of an AND gate is
HIGH only when all the inputs are HIGH. Even if any one of the input is LOW, the output
will be LOW. If a & b are input variables of an AND gate and c is its output, then Y=A.B
0 0 0
0 1 0
1 0 0
1 1 1
Two input AND gate using "diode-resistor" logic is shown in figure below. Where X,
Y are inputs and F is the output.
+V c c
R L
D 1
X F
Y
D 2
• If X = 0 and Y = 0, the both the diodes D1 and D2 are forward biased and thus both
the diodes conduct and pulling F to LOW.
• If X = 0 and Y = 1, D1 is reverse biased, thus does not conduct. But D2 is forward
biased, thus conducts and thus pulling F to LOW.
• If X = 1 and Y = 0, D2 is reverse biased, thus does not conduct. But D1 is forward
biased, thus conducts and thus pulling F to LOW.
• If X = 1 and Y = 1, the both the diodes D1 and D2 are reverse biased and thus both
the diodes are in cut-off and thus there is no drop in voltage at F. Thus F is HIGH.
The NOT gate performs the basic logical function called inversion or
complementation. The purpose of his gate is to convert one logic level into the opposite logic
level. It has one input and one output. When a HIGH level is applied to an inverter, a LOW
level appears at the output and vice-versa.
Logical Symbol:
A Y
Truth Table:
Input output
A Y= A
0 1
1 0
A NOT gate using a transistor is shown in below figure. ‘A’ represents the input and
‘F’ represents the output. When the input is HIGH, the transistor is in the ON state and the
output is LOW. If the input is LOW, the transistor is in the OFF state and the output F is
HIGH.
+ V c c
R L
F
A
NAND Gate:
The output of a NAND gate is LOW only when all inputs are HIGH and output of the
NAND is HIGH if one or more inputs are LOW.
A
Y
B
Truth Table:
Input Output
A B Y = AB
0 0 1
0 1 1
1 0 1
1 1 0
NOR Gate:
The output of the NOR gate is HIGH only when all the inputs are LOW.
A
Y
B
Truth Table:
Input Output
A B Y = A +B
0 0 1
0 1 0
1 0 0
1 1 0
In this gate output is HIGH only when any one of the input is HIGH. The circuit is
also called as inequality comparator, because it produces output when two inputs are
different.
Logical Symbol: Two input XOR Gate
A
Y
B
Truth Table:
Input Output
A B Y = A ⊕B
0 0 0
0 1 1
1 0 1
1 1 0
Y= A ⊕ B =A B + A B
An XNOR gate is a gate with two or more inputs and one output. XNOR operation is
complementary of XOR operation. i.e. The output of XNOR gate is High, when all the inputs
are identical; otherwise it is low.
A
Y
B
Truth Table:
Input Output
A B Y=A B
+AB
0 0 1
0 1 0
1 0 0
1 1 1
NAND and NOR gates are called Universal gates or Universal building blocks,
because both can be used to implement any gate like AND,OR an NOT gates or any
combination of these basic gates.
1. NOT operation:
A A
A
A
2. AND operation:
A AB Y=A . B
B
3. OR operation:
A
A AA
A A + B
B
B
B BB
4. NOR operation:
A
A + B A+ B
B
1. NOT operation:
A A
A
A
2. AND operation:
A
A A . B
A
B
B
B
3. OR operation:
A A+ B A + B
B
4. NAND operation:
A A
A B AB
B
B
Examples:
Draw the logic circuit for the Boolean expression.Y= A BC+A B C+ABC.
The logic circuits whose output at any instant of time depend not only on the present
input but also on the past outputs are called Sequential Circuits.
In sequential circuits, the output signals are feedback to the input side. Thus, an
output signal is a function of present input signals and a sequences of the past input signal.
i.e. the output signals.
The logic circuits whose output at any instant of time are entirely dependent upon the
input signals present at that time are known as combinational digital circuits. In particular, the
output of the combinational circuit doesn’t depend upon any past input or output So that the
circuit doesn’t possess any memory. The output signals of combinational circuits are not
feedback to any other part of the circuit. Combinational circuit are faster, since the operation
don’t have to be performed in sequences.
Combinational circuits can be constructed using sum of products (SOP) or product of sums
(POS). Sum is logically OR operation of different literals or signals. Product is logically
AND operation of different literals or signals.
SOP: It is sum of many products. That is literals are ORed first then those outputs are
ANDed.
Eg: F1 = YZ +Z +XY
F2 = XYZ + W
POS: It is the product of many sums. That is literals are ANDed first then those outputs are
ORed.
F2 = (X+Y+Z)W
Half Adder:
0 0 0 0
0 1 1 0
1 0 1 0
Logical Symbol
1 1 0 1
Sum= A B+A B =A ⊕B
Carry= A.B
A B
A B
Sum= AB+AB =A ⊕ B
C a r Ar y . B =
Sum= AB+AB =A ⊕ B
C a r Ar y . B =
Full Adder:
The full adder is a combinational circuit that performs the arithmetic sum of three
input bits.It consists of three inputs and two outputs. Two of the inputs are variables, denoted
by A and B, represent the two significant bit to be added The third input Cin represents carry
form the previous lower significant position.
Logical Symbol:
A S u m
B F u l l A d d e r
C a r r y
C in
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
= A [B ⊕Cin]+A[ B ⊕Cin ]
= A ⊕B ⊕Cin
= A BCin+A B Cin+AB
= A BCin+A( B Cin+B)
= A BCin+AB+ACin
= B( A Cin+A)+ACin
=B(A+Cin)+ACin
= AB+BCin+ACin
Implementation of Full Adder:
A B C i n
A B Cin A ⊕B
A ⊕B ⊕C i n
A B
B C i n A BB +C + A i n C i n
A C i n
Problems
1. Realize NOR and NAND gate using discrete components
2. Realize NOR and NAND gate using Basic gates
3. Implement Full Adder using Basic gates
4. Simplify and realize using only NAND gates
XYZ+XYZ+YZ+ Z
Karnaugh maps generally become more cluttered and hard to interpret when adding
more variables. A general rule is that Karnaugh maps work well for up to four variables, and
shouldn't be used at all for more than six variables. For expressions with larger numbers of
variables, the Quine–McCluskey algorithm can be used. Nowadays in general the
minimization process is carried out by computer, for which the Espresso heuristic logic
minimizer has become the standard minimization program.
Procedures
The K-Map method may theoretically be applied for the simplification of any boolean
expression regardless of its number of variables, but is most often used when there are fewer
than six variables because K-Maps of expressions with more than six variables are complex
and tedious to simplify. Each variable contributes two possibilities: the initial value, and its
inverse; it therefore organizes all possibilities of the system. The variables are arranged in
Gray code in which only one variable changes between two adjacent grid boxes.
Once the variables have been defined, the output possibilities are transcribed
according to the grid location provided by the variables. Thus for every possibility of a
boolean input or variable the output possibility is defined.
When the Karnaugh map has been completed, to derive a minimized function the "1s"
or desired outputs are grouped into the largest possible rectangular groups in which the
number of grid boxes (output possibilities) in the groups must be equal to a power of 2. For
example, the groups may be 4 boxes in a line, 2 boxes high by 4 boxes long, 2 boxes by 2
boxes, and so on. "Don't care(s)" possibilities (generally represented by a "X") are grouped
only if the group created is larger than the group with "Don't care" is excluded. The boxes can
be used more than once only if it generates the least number of groups. Each "1" or desired
output possibilities must be contained within at least one grouping.
The groups generated are then converted to a boolean expression by: locating and
transcribing the variable possibility attributed to the box, and by the axiom laws of boolean
algebra—in which if the (initial) variable possibility and its inverse are contained within the
same group the variable term is removed. Each group provides a "product" to create a "sum-
of-products" in the boolean expression.To determine the inverse of the Karnaugh map, the
"0s" are grouped instead of the "1s". The two expressions are non-complementary
Size of map
The size of the Karnaugh map with n Boolean variables is determined by 2n. The size
of the group within a Karnaugh map with n Boolean variables and k number of terms in the
resulting Boolean expression is determined by 2nk. Common sized maps are of 2 variables
which is a 2×2 map, 3 variables which is a 2×4 map, and 4 variables which is a 4×4 map.
A flip-flop circuit can be constructed from two NAND gates or two NOR gates. These flip-
flops are shown in Figure 2 and Figure 3. Each flip-flop has two outputs, Q and Q', and two
inputs, set and reset. This type of flip-flop is referred to as an SR flip-flop or SR latch. The
flip-flop in Figure 2 has two useful states. When Q=1 and Q'=0, it is in the set state (or 1-
state). When Q=0 and Q'=1, it is in the clear state (or 0-state). The outputs Q and Q' are
complements of each other and are referred to as the normal and complement outputs,
respectively. The binary state of the flip-flop is taken to be the value of the normal output.
When a 1 is applied to both the set and reset inputs of the flip-flop in Figure 2, both Q and Q'
outputs go to 0. This condition violates the fact that both outputs are complements of each
other. In normal operation this condition must be avoided by making sure that 1's are not
applied to both inputs simultaneously.
The NAND basic flip-flop circuit in Figure 3(a) operates with inputs normally at 1 unless the
state of the flip-flop has to be changed. A 0 applied momentarily to the set input causes Q to
go to 1 and Q' to go to 0, putting the flip-flop in the set state. When both inputs go to 0, both
outputs go to 1. This condition should be avoided in normal operation.
Clocked SR Flip-Flop: The clocked SR flip-flop shown in Figure 4 consists of a basic NOR
flip-flop and two AND gates. The outputs of the two AND gates remain at 0 as long as the
clock pulse (or CP) is 0, regardless of the S and R input values. When the clock pulse goes to
1, information from the S and R inputs passes through to the basic flip-flop. With both S=1
and R=1, the occurrence of a clock pulse causes both outputs to momentarily go to 0. When
the pulse is removed, the state of the flip-flop is indeterminate, ie., either state may result,
depending on whether the set or reset input of the flip-flop remains a 1 longer than the
transition to 0 at the end of the pulse.
D Flip-Flop
The D flip-flop shown in Figure 5 is a modification of the clocked SR flip-flop. The D input
goes directly into the S input and the complement of the D input goes to the R input. The D
input is sampled during the occurrence of a clock pulse. If it is 1, the flip-flop is switched to
the set state (unless it was already set). If it is 0, the flip-flop switches to the clear state.
JK Flip-Flop
A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type
is defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-
flop (note that in a JK flip-flop, the letter J is for set and the letter K is for clear). When logic
1 inputs are applied to both J and K simultaneously, the flip-flop switches to its complement
state, ie., if Q=1, it switches to Q=0 and vice versa.
Note that because of the feedback connection in the JK flip-flop, a CP signal which remains a
1 (while J=K=1) after the outputs have been complemented once will cause repeated and
continuous transitions of the outputs. To avoid this, the clock pulses must have a time
duration less than the propagation delay through the flip-flop. The restriction on the pulse
width can be eliminated with a master-slave or edge-triggered construction. The same
reasoning also applies to the T flip-flop presented next.
In this Binary Counter, outputs A to D represent a 4-bit Binary Number, in which A is the
LSB and D is the MSB.The 4-bit Binary Number is increased by one on each CLOCK cycle.
The count goes from (0)10 to (15)10 and then cycles back to (0)10, Table 3.
Binary
Decimal
D C B A
0 0 0 0 0
Table 3: Truth-Table of a 4-bit Binary
1 0 0 0 1 Counter
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
Ripple counter
The basic idea behind this is when J and K inputs are high in a JK filpflops the output
value gets toggled.
Assume that A, B, C, and D are lamps and that all the FFs are reset. The lamps will all
be out, and the count indicated will be 00002. The negative-going pulse of clock pulse 1
causes FF1 to set. This lights lamp A, and we have a count of 0001 2. The negative-going
pulse of clock pulse 2 toggles FF1, causing it to reset. This negative-going input to FF2
causes it to set and causes B to light. The count after two clock pulses is 0010 2, or 210. Clock
pulse 3 causes FF1 to set and lights lamp A. The setting of FF1 does not affect FF2, and lamp
B stays lit. After three clock pulses, the indicated count is 0011 2. Clock pulse 4 causes FF1 to
reset, which causes FF2 to reset, which causes FF3 to set, giving us a count of 01002. This
step shows the ripple effect. This setting and resetting of the FFs will continue until all the
FFs are set and all the lamps are lit. At that time the count will be 1111 2 or 1510. Clock pulse
16 will cause FF1 to reset and lamp A to go out. This will cause FF2 through FF4 to reset, in
order, and will extinguish lamps B, C, and D. The counter would then start at 00012 on clock
pulse 17. To display a count of 1610 or 100002, we would need to add another FF. The ripple
counter is also called an ASYNCHRONOUS counter. Asynchronous means that the events
(setting and resetting of FFs) occur one after the other rather than all at once. Because the
ripple count is asynchronous, it can produce erroneous indications when the clock speed is
high. A high-speed clock can cause the lower stage FFs to change state before the upper
stages have reacted to the previous clock pulse. The errors are produced by the FFs’ inability
to keep up with the clock.
Here And-Or logic is used to implement Up down counter. When Up/down signal is
high all upper and gates enabled. So all Q values are considered and it upcounts. When When
Up/down signal is low all lower And gates enabled. So all Q bar values are considered and it
downcounts.
SHIFT REGISTER
The term register can be used in a variety of specific applications, but in all cases it
refers to a group of flip-flops operating as a coherent unit to hold data. This is different
from a counter, which is a group of flip-flops operating to generate new data by
tabulating it.
In this context, a counter can be viewed as a specialized kind of register, which counts
events and thereby generates data, rather than just holding the data or changing the way
it is handled. More commonly, however, counters are treated separately from registers.
The two are then handled as separate concepts which work together in many
applications, and which have some features in common.
The demonstration circuit below is known as a shift register because data is shifted
through it, from flip-flop to flip-flop. If you apply one byte (8 bits) of data to the initial
data input one bit at a time, and apply one clock pulse to the circuit after setting each bit
of data, you will find the entire byte present at the flip-flop outputs in parallel format.
Therefore, this circuit is known as a serial-in, parallel-out shift register. It is also known
sometimes as a shift-in register, or as a serial-to-parallel shift register.
By standardized convention, the least significant bit (LSB) of the byte is shifted
in first.
The 555 timer consists of two voltage comparators, a bistable flip-flop, a discharge
transistor, and a resistor divider network. To understand the basic concept of the timer let’s
first examine the timer in block form as in Figure. The resistive divider network is used to set
the comparator levels. Since all three resistors are of equal value, the threshold comparator is
referenced internally at 2/3 of supply voltage level and the trigger comparator is referenced at
1/3 of supply voltage. The outputs of the comparators are tied to the bistable flip-flop. When
the trigger voltage is moved below 1/3 of the supply, the comparator changes state and sets
the flip-flop driving the output to a high state. The threshold pin normally monitors the
capacitor voltage of the RC timing network. When the capacitor voltage exceeds 2/3 of the
supply, the threshold comparator resets the flip flop which in turn drives the output to a low
state. When the output is in a low state, the discharge transistor is “on”, thereby discharging
the external timing capacitor. Once the capacitor is discharged, the timer will await another
trigger pulse, the timing cycle having been completed.
Astable multivibrator
Fig. Astable multivibrator
With the output high (+Vs) the capacitor C1 is charged by current flowing through R1
and R2. The threshold and trigger inputs monitor the capacitor voltage and when it reaches
2
/3Vs (threshold voltage) the output becomes low and the discharge pin is connected to 0V.
The capacitor now discharges with current flowing through R2 into the discharge pin.
When the voltage falls to 1/3Vs (trigger voltage) the output becomes high again and the
discharge pin is disconnected, allowing the capacitor to start charging again.
This cycle repeats continuously unless the reset input is connected to 0V which forces
the output low while reset is 0V.
An astable can be used to provide the clock signal for circuits such as counters.
A low frequency astable (< 10Hz) can be used to flash an LED on and off, higher
frequency flashes are too fast to be seen clearly. Driving a loudspeaker or piezo transducer
with a low frequency of less than 20Hz will produce a series of 'clicks' (one for each low/high
transition) and this can be used to make a simple metronome.
An audio frequency astable (20Hz to 20kHz) can be used to produce a sound from a
loudspeaker or piezo transducer. The sound is suitable for buzzes and beeps. The natural
(resonant) frequency of most piezo transducers is about 3kHz and this will make them
produce a particularly loud sound.
Monostable Multivibrator
A typical DAC converts the abstract numbers into a concrete sequence of impulses that are
then processed by a reconstruction filter using some form of interpolation to fill in data
between the impulses. Other DAC methods (e.g., methods based on Delta-sigma modulation)
produce a pulse-density modulated signal that can then be filtered in a similar way to produce
a smoothly varying signal.
An ADC inputs an analog electrical signal such as voltage or current and outputs a binary
number. In block diagram form, it can be represented as such:
A DAC, on the other hand, inputs a binary number and outputs an analog voltage or current
signal. In block diagram form, it looks like this:
Together, they are often used in digital systems to provide complete interface with analog
sensors and output devices for control systems such as those used in automotive engine
controls:
It is much easier to convert a digital signal into an analog signal than it is to do the reverse.
Therefore, we will begin with DAC circuitry and then move to ADC circuitry.
This DAC circuit, otherwise known as the binary-weighted-input DAC, is a variation on the
inverting summer op-amp circuit. If you recall, the classic inverting summer circuit is an
operational amplifier using negative feedback for controlled gain, with several voltage inputs
and one voltage output. The output voltage is the inverted (opposite polarity) sum of all input
voltages:
For a simple inverting summer circuit, all resistors must be of equal value. If any of the input
resistors were different, the input voltages would have different degrees of effect on the
output, and the output voltage would not be a true sum. Let's consider, however, intentionally
setting the input resistors at different values. Suppose we were to set the input resistor values
at multiple powers of two: R, 2R, and 4R, instead of all the same value R:
Starting from V1 and going through V3, this would give each input voltage exactly half the
effect on the output as the voltage before it. In other words, input voltage V1 has a 1:1 effect
on the output voltage (gain of 1), while input voltage V2 has half that much effect on the
output (a gain of 1/2), and V3 half of that (a gain of 1/4). These ratios are were not arbitrarily
chosen: they are the same ratios corresponding to place weights in the binary numeration
system. If we drive the inputs of this circuit with digital gates so that each input is either 0
volts or full supply voltage, the output voltage will be an analog representation of the binary
value of these three bits.
If we chart the output voltages for all eight combinations of binary bits (000 through 111)
input to this circuit, we will get the following progression of voltages:
Note that with each step in the binary count sequence, there results a 1.25 volt change in the
output.
An alternative to the binary-weighted-input DAC is the so-called R/2R DAC, which uses
fewer unique resistor values. A disadvantage of the former DAC design was its requirement
of several different precise input resistor values: one unique value per binary input bit.
Manufacture may be simplified if there are fewer different resistor values to purchase, stock,
and sort prior to assembly.
Of course, we could take our last DAC circuit and modify it to use a single input resistance
value, by connecting multiple resistors together in series:
Unfortunately, this approach merely substitutes one type of complexity for another: volume
of components over diversity of component values. There is, however, a more efficient
design methodology.
By constructing a different kind of resistor network on the input of our summing circuit, we
can achieve the same kind of binary weighting with only two kinds of resistor values, and
with only a modest increase in resistor count. This "ladder" network looks like this:
Mathematically analyzing this ladder network is a bit more complex than for the previous
circuit, where each input resistor provided an easily-calculated gain for that bit. For those
who are interested in pursuing the intricacies of this circuit further, you may opt to use
Thevenin's theorem for each binary input. you should obtain the following table of figures:
Binary Output voltage
000 0.00V
001 -1.25V
010 -2.50V
011 -3.75V
100 -5.00V
101 -6.25V
110 -7.50V
111 -8.75V
As was the case with the binary-weighted DAC design, we can modify the value of the
feedback resistor to obtain any "span" desired. For example, if we're using +5 volts for a
"high" voltage level and 0 volts for a "low" voltage level, we can obtain an analog output
directly corresponding to the binary input (011 = -3 volts, 101 = -5 volts, 111 = -7 volts, etc.)
by using a feedback resistance with a value of 1.6R instead of 2R.
Flash ADC
Also called the parallel A/D converter, this circuit is the simplest to understand. It is
formed of a series of comparators, each one comparing the input signal to a unique reference
voltage. The comparator outputs connect to the inputs of a priority encoder circuit, which
then produces a binary output. The following illustration shows a 3-bit flash ADC circuit:
Vref is a stable reference voltage provided by a precision voltage regulator as part of the
converter circuit, not shown in the schematic. As the analog input voltage exceeds the
reference voltage at each comparator, the comparator outputs will sequentially saturate to a
high state. The priority encoder generates a binary number based on the highest-order active
input, ignoring all other active inputs.
When operated, the flash ADC produces an output that looks something like this:
For this particular application, a regular priority encoder with all its inherent complexity isn't
necessary. Due to the nature of the sequential comparator output states (each comparator
saturating "high" in sequence from lowest to highest), the same "highest-order-input
selection" effect may be realized through a set of Exclusive-OR gates, allowing the use of a
simpler, non-priority encoder:
And, of course, the encoder circuit itself can be made from a matrix of diodes, demonstrating
just how simply this converter design may be constructed:
Not only is the flash converter the simplest in terms of operational theory, but it is the most
efficient of the ADC technologies in terms of speed, being limited only in comparator and
gate propagation delays. Unfortunately, it is the most component-intensive for any given
number of output bits. This three-bit flash ADC requires seven comparators. A four-bit
version would require 15 comparators. With each additional output bit, the number of
required comparators doubles. Considering that eight bits is generally considered the
minimum necessary for any practical ADC (255 comparators needed!), the flash
methodology quickly shows its weakness. An additional advantage of the flash converter,
often overlooked, is the ability for it to produce a non-linear output. With equal-value
resistors in the reference voltage divider network, each successive binary count represents the
same amount of analog signal increase, providing a proportional response. For special
applications, however, the resistor values in the divider network may be made non-equal.
This gives the ADC a custom, nonlinear response to the analog input signal. No other ADC
design is able to grant this signal-conditioning behavior with just a few component value
changes.
Chapter 8
COMMUNICATION SYSTEMS
8.1 Introduction:
In a broad sense the term communication refers to the sending, receiving and
processing of information by electronic means. It can also be defined as a process of
transmitting information or signal from one point known as source to another point known as
destination. Information can be continuous such as speech music, picture etc. or discrete
signals like data from computer etc.
Output
Input Input
Transmitte Received Output Messag
Messag Signa
d signal signal signal e
e l
Input
Transmitt Transmission Output
Receiver
er transducer
Transduc
er channel
Noise
As shown in the figure 8.1, the first block at the source is an input transducer which is
used to convert physical quantity (non electrical) to electrical quantity. For example voice is
converted to electrical quantity using microphone. Similarly at the destination output
transducer is used to convert electrical back to physical quantity. For example a loudspeaker
is used to convert voice signal in the form of electrical back to physical quantity. Likewise
picture signal can be converted to electrical signal by using image sensor. The image sensors
used mostly in digital Camera. If the signal to be transmitted is picture input transducer can
be the digital camera. The output transducer can be any picture display unit such as CRT or
LCD.
• Transmitter
• Transmission Channel
• Receiver
8.1.1 Transmitter:
The output signal of the transducer is a complex signal. It is restricted to desired range of
frequencies. On this signal modulation is performed. Modulation is a process of altering the
characteristics of carrier signal in accordance with the information. There are basically three
types of modulation technique
• Amplitude modulation.
• Frequency modulation.
• Phase modulation.
The modulated signal is then transmitted over a transmission channel.
It is a medium over which the electronic signal is transmitted from one point to
another. This medium can be either wired or wireless.
8.1.3 Noise:
It is a random, undesirable electrical energy that interferes with the transmitted signal. It
can be either natural noise such as noise caused by lightning during rainy season or man
made noise produced by ignition system of cars etc. Noise is a serious problem which cannot
be eliminated but one can reduce the effect caused by it on the signal.
8.1.4 Receiver:
The radio-frequency spectrum is divided arbitrarily into a number of bands from very low
frequencies. Sections of the spectrum have been allocated to the various users, such as
telegraph, telephonic speech, telemetry, and radio and television broadcasting.
Each frequency range has a band designator and each range of frequencies behaves
differently and performs different functions. The frequency spectrum is shared by civil,
government, and military users of all nations according to International Telecommunications
Union (ITU) radio regulations. For communications purposes, the usable frequency spectrum
now extends from about 30Hz to about 300GHz. Frequency band standard is described in
International Telecommunications Union radio regulations. And it looks as follows.
Noise can be divided into two types: Internal Noise, which originates within the
communication equipment, and External Noise, which is a property of the channel.
Noise is generated in all electronic equipment. Several types of internal noise are as follows:
Thermal Noise: Produced by the random motion of electrons in a conductor due to heat.
Shot Noise: produced by random variations in current flow in active devices such as tubes,
transistors, and semiconductor diodes.
Partition Noise: It occurs only in devices where a single current separates into two or more
paths.
Transit-Time Noise: Occurs when the time taken by the charge carriers to cross a junction is
comparable to the period of the signal.
If the channel is a radio link, there are following possible sources of noise:
Equipment Noise: Noise is generated by equipment that produces sparks. Examples include
automobile engines and electric motors with brushes.
Space Noise: occurs due to radiation from Sun and other stars.
Examples of wire media include Twisted-pair, Co-axial cable and Optical fiber.
Twisted-pair:
A basic twisted-pair cable consists of two strands of copper wire twisted together as shown
in the figure 8.2.
This twisting reduces the sensitivity of the cable to electromagnetic interference and also
reduces the tendency of the cable to radiate radio frequency noise that interferes with nearby
cables and electronic components. This is because the radiated signals from the twisted wires
tend to cancel each other out.
These are divided into two major categories: Unshielded Twisted Pair (UTP), and Shielded
Twisted Pair (STP).
Applications:
Most common transmission media for both digital and analog signals
Less expensive compared to coaxial cable or optical fiber
Limited in terms of data rate and distance
Telephone network
• Individual units (residence lines) to local exchange (end office)
• Subscriber loops
• Supports voice traffic using analog signaling
• May handle digital data at modest rates using modems
Communications within buildings
• Connection to digital data switch or digital pbx within a building
• Allows data rate of 64 kbps.
Coaxial Cable:
• Consists of two conductors with construction that allows it to operate over a wider
range of frequencies compared to twisted pair
• Hollow outer cylindrical conductor surrounding a single inner wire conductor
• Inner conductor held in place by regularly spaced insulating rings or solid dielectric
material
• Outer conductor covered with a jacket or shield
• Diameter from 1 to 2.5 cm
• Shielded concentric construction reduces interference and crosstalk
• Can be used over longer distances and support more stations on a shared line than
twisted pair.
Applications:
Optical Fiber:
Applications
_ Long haul trunks
_ Increasingly common in telephone networks
_ About 1500km in length with high capacity (20000 to 60000 voice channels)
_ Metropolitan trunks
_ Average length of about 12 km with a capacity of 100,000 voice channels
_ Mostly repeaterless to join phone exchanges in metro areas
_ Rural exchange trunks
_ Circuit lengths from 40 to 160 km
_ Fewer than 5000 voice channels
_ Connect exchanges of different phone companies
_ Subscriber loops
_ Central exchange to subscriber
_ May be able to handle image and video in addition to voice and data
_ Local area networks
_ 100Mbps to 1Gbps capacity
_ Can support hundreds of stations on a campus
Chapter 9
Analog Modulation:
9.1 Introduction:
The communication system can be of an analog or digital type. The design of analog
communication system is relatively simple. The transmitter consists of a modulator and the
receiver consists of a demodulator. The different modulation and demodulation techniques
used are Amplitude, Frequency and Phase modulation.
1. The height of the antenna required to transmit and receive radio waves is a
function of wavelength of the frequency used. i.e.λ = c/f. At low frequency, λ is
high and hence the height of the antenna should be more to transmit the signal
(since ‘λ’ is proportional to ‘h’). Therefore high frequencies are used to transmit
the information which requires antenna of lesser height.
2. At low frequency radiation is poor and signal gets highly attenuated. Therefore
signal cannot be transmitted over longer distance. Modulation effectively
increases the frequency of the signal to be radiated and thus increases the distance
over which signal can be transmitted faithfully.
3. The modulation permits multiplexing to be used. Multiplexing is method of
transmitting two or more information simultaneously over a single channel. In this
method each message signal is modulated using different carrier signal
frequencies and then transmitted over a single channel. At the receiver the
message signals are extracted individually by tuning to their respective carrier
frequencies.
9.3 Amplitude Modulation:
It is defined as a process of varying the amplitude of the carrier wave proportional to the
instantaneous amplitude of modulating signal. Figure 9.1 shows the diagram for AM
generation.
Fig. 9.1 Diagram for Amplitude Modulation.
Let the equation of carrier signal be c(t) = Accos(2пfct) where Ac is the peak amplitude
of carrier signal and fc is the frequency of the carrier signal.
Let the equation of modulating signal be m(t) = Amcos(2пfmt) where Am is the peak
amplitude of modulating signal and fm is the frequency of the modulating signal.
Am
= AC cos(2пfct) + {cos[2п(fc + fm)t] + cos[2п(fc - fm)t] }
2
mA C
VAM(t) = AC cos(2пfct) + {cos[2п(fc + fm)t] + cos[2п(fc -
2
fm)t] } (9.2)
Where ‘m’ is the modulation index of AM signal which is defined as ratio of amplitude of
Am
modulating signal to that of carrier signal i.e. . The significance of modulation index is,
AC
it decides the depth of modulation. If it is less than one, then AM signal is known as under
modulated signal. If it is more than one, then AM signal is known as over modulated signal.
If it is equal to one, then AM signal is known as perfect modulated signal. To obtain the
original information, modulation index should always be less than or equal to one.
f
fc - fc +
fc Hzs
fm m
f
Fig. 9.2 Frequency Spectrum of AM signal
As shown in the figure 9.2, the spectrum consisted of three frequency components,
one at fc and other two at fc + fm , fc- fm. The frequencies fc + fm and fc- fm are known as
sideband frequencies i.e.fc + fm is known as upper sideband frequency and f c- fm is known as
lower sideband frequency . The separation between these two frequencies is defined as
bandwidth of AM signal. Therefore the bandwidth of AM signal is 2fm.
= PC + PLSB + PUSB
AC2 m2
= {1+ }
2R 2
(9.5) m2
PT = PC { 1 + }
2
(9.6)
The above equation gives the total power required to transmit AM signal in terms of
carrier power and modulation index.
1
For 100% modulation : m = 1, Therefore PT = PC { 1 + }
2
3
= PC
2
2
Or PC = PT = 0.6666 PT
3
Or PC = 66.66%PT
Current calculation:
m2
PT = PC { 1 + }
2
I T2 I2 m2
= C {1+ }
R R 2
m2
I T2 = I C2 { 1 + }
2
(9.7)
where I T is the current with modulation , I C is the current without modulation and R is the
resistance of the antenna.
In modulation by several sine waves, modulating signal consists of several sine waves
(9.8)
2
mt
PT = PC { 1 + }
2
(9.11)
Similarly current with modulation will be
mt2
IT = IC { (1 + }
2
(9.12)
Problems:
Am 10
i) Modulation index: m = = = 0.25.
AC 40
AC2 m2
PT = (1+ )
2R 2
1600 0.25
= (1+ )
2000 2
AC 40
v) Amplitude of each sideband = m =0.25 * = 5V.
2 2
Solution:
i) Given : IT = 8.93A.
IC = 8A.
m2
IT = IC { (1 + }
2
I T2
m = 2 2 −1 = 0.701 =70.1%.
IC
m2
IT = IC { (1 + } = 9.19A.
2
3. A certain transmitter radiates 9KW with carrier unmodulated and 10.125KW when
carrier is sinusoidally modulated. Calculate modulation index. If another sine wave
corresponding to 40% modulation is transmitted simultaneously, determine the total
power radiated.
Solution:
i) Given: P T = 9KW.
PC = 10.125KW.
2
m
PT = PC { 1 + }
2
P
m = 2 T −1 = 0.5.
PC
2
mt
PT = PC { 1 + } = 10.84KW.
2
Problems:
VMAX −VMIN
1. Show that modulation index = , where VMAX and VMIN are maximum
VMAX +VMIN
9.4 AM Demodulation:
Amplitude modulation, AM, is one of the most straightforward ways of modulating a radio
signal or carrier. The process of demodulation, where the audio signal is removed from the
radio carrier in the receiver is very simple. The easiest method of achieving amplitude
demodulation is to use a simple diode detector. This consists of just a handful of
components:- a diode, resistor and a capacitor. The circuit diagram of AM demodulator or
detector is as shown below.
Fig9.3 AM detector
In this circuit, the diode rectifies the signal, allowing only half of the alternating waveform
through. The capacitor is used to store the charge and provide a smoothed output from the
detector, and also to remove any unwanted radio frequency components. The resistor is used
to enable the capacitor to discharge.
The two sidebands of an AM signal are mirror images of each other. Thus one sideband is
redundant, and it is not necessary to transmit both sidebands. Removing one sideband reduces
the bandwidth by at least a factor of two. Thus resulting signal will require less transmitted
power, and perfectly acceptable communication will be possible.
Applications:
SSB modulation offers a far more effective solution for two way radio communication for the
transmission of voice because it provides a significant improvement in efficiency.
= fC + Kf Amcos(2Πfmt)
= fC + Δf cos(2Πfmt) (9.14)
where Δf is known as frequency deviation. Its signifies, by how much amount carrier
frequency gets deviated.
∆W
WFMt = WCt +
Wm ∫cos( 2Πf m t ) dt
(9.16)
∆W
θ(t ) = WCt + sin(2Πfmt) (9.17)
Wm
∆W
= AC cos[ WCt + sin(2Πfmt) ]
Wm
2Π∆f
= AC cos[ WCt + sin(2Πfmt) ]
2Πf m
∆f
= AC cos[ WCt + sin(2Πfmt) ]
fm
∆f
where β = is defined as modulation index of FM. Unlike AM modulation index is not
fm
Problems:
Solution:
ii) If Am = 7.5V , Δf = ?
∆f 5 ×10 3
Kf = = = 2KHz/V.
fm 2 .5
Δf = Kf × Am = 2 × 7.5 = 15KHz.
∆f 15 ×10 3
Modulation index: β = = = 300.
fm 50
iii) Δf = Kf × Am = 2 × 10 = 20KHz.
∆f 20 ×10 3
Modulation index: β = = = 800.
fm 250
Problems:
1. A carrier of amplitude 5V and frequency 90MHz is frequency modulated by
asinusoidal voltage of amplitude 5V and frequency 15KHz. The frequency sensitivity
is 1Hz/V. Calculate the frequency deviation and modulation index.
2. Compare and contrast AM and FM.
9.9 The Super-heterodyne Receiver:
There are a great variety of receivers in communication systems based on the requirements
such as the modulation scheme, the operating frequency and its range and the type of display
required. One of them AM-super-heterodyne type, whose block diagram is as shown in
fig.9.5.
When heterodyning the incoming signal and the local oscillator signal in the mixer stage, four
frequencies are produced. They are the two basic input frequencies and the sum and the
difference of those two frequencies. The amplifier that follows (IF amplifier) will be tuned to
the difference frequency. This difference frequency is known as the intermediate frequency
(IF). A typical value of IF for an AM communications receiver is 455 kilohertz. The
difference frequency is a lower frequency than either the rf input or oscillator frequencies.
This lower frequency gives slightly better gain but does increase the chances of image
frequency interference.
Once the IF stages have amplified the intermediate frequency to a sufficient level, it is fed to
the detector. The detector extracts the modulating audio signal. The detector stage consists of
a rectifying device and filter, which respond only to the amplitude variations of the IF signal.
This develops an output voltage varying at an audio-frequency rate. The output from the
detector is further amplified in the audio amplifier and is used to drive a speaker or
earphones.
The FM superheterodyne receiver block diagram has many similarities to that of the AM
superheterodyne receiver studied earlier.
As the figure 9.6 shows, the FM receiver is quite similar to AM receiver, and the only
apparent differences are the use of limiter-discriminator circuit in place of detector section
and the addition of a de-emphasis network. The other sections perform almost identical
functions as in AM receiver.
The universally standard IF frequency for FM is 10.7MHz , as compared to 455kHz for AM.
The additional components inside the FM superheterodyne receiver and their functions are:
Limiter: Its function is to remove any unwanted amplitude modulation and the amplitude
variations due to noise, where they would carry an undesirable effect if carried through to
the speaker.
Discriminator: Its function is to extract the information that has been modulated onto the
carrier via frequency variations.
Pre- and de-emphasis network: Its function is to improve the signal-to-noise ratio where at
the transmitter there will be the pre-emphasis circuit. The pre-emphasis will amplify the high
frequency component. And the de-emphasis will provide a normal frequency response. The
combined effect of pre-emphasis and de-emphasis is to increase the high-frequency
components during the transmission so that they will be stronger and not masked by noise.
Chapter 10
Digital Modulation
10.1 Introduction:
Harry Nyquist proved the sampling theorem which states that it is possible to reconstruct a
band-limited analog signal from periodic samples, as long as the sampling rate is at least
twice the highest frequency component of the signal.
Consider for example a signal composed of a single sine wave at a frequency of 1 Hz:
Fig.10.1 Sinusoidal signal of frequency 1 Hz
If we sample this waveform at 2 Hz (as dictated by the Nyquist theorem), that is sufficient to
capture each peak and trough of the signal:
If however we sample at a frequency lower than 2 Hz, for example at 1.5 Hz, then there are
now not enough samples to capture all the peaks and troughs in the signal:
Fig.10.4 Sinusoidal signal of 1 Hz sampled at 1.5Hzs
Note here that we are not only losing information, but we are getting the wrong information
about the signal. The person receiving these samples, without any previous knowledge of the
original signal, may well be mislead into thinking that the signal has quite a different form:
Thus, when a signal contains not just one but many different frequencies added together, the
minimal sampling rate needed to avoid aliasing is just twice whatever the highest frequency
is, irrespective of how many other frequency components there are.
Frequency Division Multiplexing (FDM) is a technique, the carrier bandwidth is divided into
sub-channels of different frequency widths, each signal is modulated to a different carrier
frequency. Carrier frequencies separated so that signals do not overlap (guard bands).
E.g. broadcast radio.
FDM is used in analog transmission such as twisted pair telephone line, cable access, cellular,
radio and TV communications.
10.6 Introduction to Mobile Communication:
A cellular radio system provides a wireless connection to the public telephone network for
any user location within the radio range of the system. The term mobile has traditionally been
used to classify a radio terminal that can be moved during communication. Cellular systems
accommodate a large number of mobile units over a large area within a limited frequency
spectrum. There are several types of radio transmission systems. We consider only full
duplex systems. These are communication systems that allow simultaneous two-way
communication. Transmission and reception for a full duplex system are typically on two
different channels, so the user may constantly transmit while receiving signals from another
user. Figure 10.12 shows a basic cellular system that consists of mobiles, base stations, and a
switching center.
Each mobile contains a transceiver (transmitter and receiver), an antenna, and control
circuitry. The base stations consist of several transmitters and receivers, which
simultaneously handle full duplex communications and generally have towers that support
several transmitting and receiving antennas. The base station connects the simultaneous
mobile calls via telephone lines, microwave links, or fiber-optic cables to the switching
center. The switching center coordinates the activity of all of the base stations and connects
the entire cellular system to the public telephone network.
The channels used for transmission from the base station to the mobiles are called forward or
downlink channels, and the channels used for transmission from the mobiles to the base
station are called reverse or uplink channels. The two channels responsible for call initiation
and service request are the forward control channel and reverse control channel.
Once a call is in progress, the switching center adjusts the transmitted power of the mobile
(this process is called power control) and changes the channel of the mobile and base station
(handoff) to maintain call quality as the mobile moves in and out of range of a given base
station. A call from a user can be transferred from one base station to another during the call.
The process of transferring is called handoff.