disclaimer: use this sheet at your own risk; i.e.

there may be errors on this, make sure you know when to use the formulas, don’t use
this as substitute for studying, blah blah blah…)

pn junction
Semiconductor Physics in thermal equilibrium
mass-action law* *under T.E. (or quasi-equilibrium) charge neutrality Æ N a x po = N d xno
2 2
n o p o = ni where ni = 1020 cm-3 at 300K
built-in potential φ B = φn − φ p
2
n depletion regions
n-type: no ≅ N d & po ≅ i
Nd ⎛ 2ε φ ⎞⎛ N d ⎞ ⎛ 2ε φ ⎞⎛ N a ⎞
x po = ⎜⎜ s B ⎟⎟⎜⎜ ⎟⎟ xno = ⎜⎜ s B ⎟⎟⎜⎜ ⎟⎟
ni
2
⎝ qN a ⎠⎝ N d + N a ⎠ ⎝ qN d ⎠⎝ N d + N a ⎠
p-type: po ≅ N a & no ≅
Na
⎛ 2ε φ ⎞⎛ 1 1 ⎞
X do = x po + x no = ⎜⎜ s B ⎟⎟⎜⎜ + ⎟⎟
drift velocity* *for v < vsat only (vsat = 10 cm/s) 7 ⎝ q ⎠⎝ N a N d ⎠
vdn = − µ n E (electron) vdp = µ p E (hole)
n+p junction p+n junction

current density (drift + diffusion) ⎛ 2ε φ ⎞ ⎛ 2ε φ ⎞

x po = ⎜⎜ s B ⎟⎟ = X do x no = ⎜⎜ s B ⎟⎟ = X do
dn (electron) ⎝ qN a ⎠ ⎝ qN d ⎠
= qnµ n E + qDn
dr diff
Jn = Jn + Jn
dx
dp (hole) depletion capacitance (at T.E.)
= qpµ p E − qD p
dr diff
Jp = Jp + Jp C jo =
εs
=
εs
dx X do ⎛ 2ε sφ B ⎞⎛ 1 1 ⎞
⎜⎜ ⎟⎟⎜⎜ + ⎟⎟
Einstein Relation ⎝ q ⎠⎝ N a N d ⎠
Dp kT Dn kT
= and = under reverse bias
µp q µn q φ j = φB − VD (VD is negative)
kT
“thermal voltage” : Vth = = 26mV x p (V D ) = x po 1 −
VD
x n (V D ) = x no 1 −
VD
q φB φB
Electrostatics VD
X d (V D ) = X do 1 −
Gauss’ Law / Electrostatic Potential φB
dE ρ dφ Depletion capacitance (under bias)
= E ( x) = −
dx ε dx C j (VD ) =
εs C jo
=
X d (VD ) VD
1−
d φ
2
dE ( x) ρ ( x) φB
Poisson Equation: =− =− MOS capacitor (p-substrate)
dx 2
dx ε Built-in voltage
φ B = φ g − φ p = φn + − φ p
Permittivity in vacuum: ε o = 8.85 × 10 −14 F / cm
in silicon: ε s = 11.7ε o in SiO2: ε ox = 3.9ε o Flatband voltage
VFB = −φB
Boltzmann relations* (requires Jno = Jpo = 0) Threshold voltage
no ( x) = ni e qφo ( x ) / kT po ( x) = ni e − qφo ( x ) / kT VT = VFB − 2φ p + γ − 2φ p

reference point: φo ( x ) = 0 when no = ni

Body factor [units = V1/2]
1
60mV Rule* (requires Jno = Jpo = 0) γ= 2ε s qN a
Cox
⎛ no ( x) ⎞ ⎛ p ( x) ⎞
φo ( x) = 60mV log⎜ 10 ⎟
= −60mV log⎜ o 10 ⎟ Small-signal capacitance
⎝ 10 ⎠ ⎝ 10 ⎠ ε ox εs
For electrons: For holes: Cox = C dep =
tox X d (VGB )
kT ⎛ no ⎞ kT ⎛ p ⎞
φn = ln⎜ ⎟ φ p = − ln⎜⎜ o ⎟⎟ In depletion regime:
q ⎜⎝ ni ⎟⎠ q ⎝ ni ⎠ 1
C=
1 1
+
n+ Si: φn+ = 550mV p+ Si: φ p+ = −550mV Cox Cdep
disclaimer: use this sheet at your own risk; i.e. there may be errors on this, make sure you know when to use the
formulas, don’t use this as substitute for studying, blah blah blah…)

Summary for MOS Capacitor (n+ gate, p-type Si substrate)

VGB ≤ VFB VGB = VFB VFB ≤ VGB ≤ VT VGB = VT VGB ≥ VT
regime Accumulation Flatband Depletion Threshold Inversion
QG Cox (VGB − VFB ) 0 − QB = qN a X d (VGB ) − QB max = qN a X d max Cox (VGB − VT ) − QB max
QS − Cox (VGB − VFB ) 0 QB = −qN a X d (VGB ) QB max = −qN a X d max − Cox (VGB − VT ) + QB max
ε s ⎛⎜ 4(φ B + VGB ) ⎞ 2ε s (−2φ p ) 2ε s (−2φ p )
Xd N/A N/A 1+ − 1⎟ X d max = X d max =
Cox ⎜⎝ γ2 ⎟
⎠ qN a qN a
φs ≈ φp φp qN a X d
2
− φp ≈ −φ p
φp +
2ε s
C Cox Cox 1 1 Cox
C= C=
1 X 1 X
+ d + d max
Cox ε s Cox εs

*Note: in accumulation, gate charge is actually negative, charge in semiconductor is positive (because VGB<VFB).