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1. The ESD system should comply with which IEC standard for software to execute logic.
Ans: IEC61131
Explanation: IEC 61131-3 standard identified following language for software logic execution:
Ladder Diagram (LD),
Instruction List (IL),
Function Block Diagram (FBD),
Structured Text (ST) and
Sequential Function Chart (SFC).
2. ESD system dangerous Failures can be revealed
i> During system diagnostic test ii> By Sequence of Event Operation (SOE) of failures iii> During system complete
testing iv> During system detail designing.
Explanation: In case of ESD system the diagnostic test is the part of the ESD system design & engineering and
dangerous failures known through the diagnostic test is already known during the system test, hence it is revealed one
and part of supplied ESD system PFD. Hence dangerous failures can be revealed only through complete test. If all
dangerous failure can be revealed
However in case of On/OFF valve PST will revealed some dangerous failure which are not known during valve
engineering and test and not the part of its original PFD.
i> 50 millisecond ii> Half of the process safety time iii> 20 millisecond iv> Half of the process logic scan time
Ans: 20 millisecond
Explanation: If the inverter output is synchronized with the mains input (synchronous mode) then in the event of a
failure in inverter the transfer time is less than 5mS because the Static Switch output and Inverter output are in phase
and frequency locked with static Bypass.
In case, the inverter is not synchronized with the input mains then the unit is in Asynchronous mode and the transfer
time will be larger and around 20ms.
4. As per RIL specification supplied ESD system shall be guaranteed to min availability of
Ans: 99.99990%
Ans: 2oo2
Explanation: HFT= Hardware fault tolerance; for MooN configuration HFT = N-M
configuration HFT
1oo4 3
2oo3 1
2oo2 0
1oo2 1
i> Reduce avg PFD ii> Increase avg PFD iii> Increase Valve proof test interval(PTI) iv> Reduce RRF
Explanation: Partial stroke testing will increase the diagnostic coverage where some dangerous failure will be
revealed, hence Probability of Failure Dangerously will reduce. The coverage of partial stroke testing range from 50-
90%.
i> it bypass initiator ii> it neglect initiator iii> it put imitator in trip condition iv> it bypass output
Explanation: Negative MOS will force selected initiator in trip condition. It generally used for 2oo3 group for SIL3
application in J3.
Explanation: On/off valves, logic solver and automated fire water sprinkler are part of SIF. Automated fire sprinkler are
generally part of SIF if water sprinkler is used for prevention of fire.
9. To carry out Process Hazard Analysis (PHA), such as a HAZOP, the participants carrying out the study should
have all of the following safety information, except: (easy)
Ans: B
Explanation: SIS data sheet and specification will not be required for HAZOP. In fact SIS data sheet and specification
will not be available during HAZOP as safety requirement specification and detail engineering yet to start.
10. To carry out SIL classification, the participants carrying out the study should have all of the following safety
information, except:
B. Hazop report
Ans: D
Explanation: PFD values of SIS will not be required for SIL classification or assignment. In fact after SIL classification
min PFD values required for SIS will be known.
11. Rank the following redundancy scheme from highest probability of failure to lowest probability of failure
on demand.
Highest----------------- lowest
Explantion: If λdu is the PFD of one component and will be always less than 1. The overall configuration PFD will be
Configuration PFD
2oo2 λdu - Highest
2oo3 λdu²
1oo2 λdu²/3 - lowest