cu_a.

vhd Thu Sep 20 12:17:48 2018

1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3 use IEEE.NUMERIC_STD.ALL;
4
5 entity cu_a is
6 Port ( go : in STD_LOGIC;
7 z : in STD_LOGIC;
8 a0 : in STD_LOGIC;
9 clk : in STD_LOGIC;
10 rst : in STD_LOGIC;
11 LA : out STD_LOGIC;
12 EA : out STD_LOGIC;
13 LB : out STD_LOGIC;
14 EB : out STD_LOGIC;
15 done : out STD_LOGIC);
16 end cu_a;
17
18 architecture Behavioral of cu_a is
19
20 type state_type is (s0,s1,s2,s3,s4,s5,s6);
21 signal y:state_type;
22
23 begin
24
25 --===================== transitions =============================================
26 transitions:process(clk,rst)
27 begin
28 if rst='1' then
29 y<=s0;
30 elsif rising_edge(clk) then
31 case y is
32 when s0 =>
33 if go='1' then
34 y <= s1;
35 else
36 y <= s0;
37 end if;
38 when s1 =>
39 y <= s2;
40 when s2 =>
41 if z = '0' then
42 y <= s3;
43 else
44 y <= s6;
45 end if;
46 when s3 =>
47 if a0 = '1' then
48 y <= s4;
49 else
50 y <= s5;
51 end if;
52 when s4 =>
53 y <= s5;
54 when s5 =>
55 y <= s2;
56 when s6 =>
57 y <= s6;
58 when others => NULL;
59 end case;
60 end if;
61 end process;

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cu_a.vhd Thu Sep 20 12:17:49 2018
62 --===============================================================================
63
64 --============== outputs ========================================================
65 outputs:process(y)
66 begin
67 --default values:
68 LA <= '0'; EA <= '0'; LB <= '0'; EB <= '0'; done <= '0';
69
70 case y is
71 when s0 =>
72 LA <='1';
73 when s1 =>
74 LB <='1';
75 when s4 =>
76 EB <='1';
77 when s5 =>
78 EA <='1';
79 when s6 =>
80 done <='1';
81 when others => NULL;
82 end case;
83 end process;
84 --===============================================================================
85 end Behavioral;
86
87

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