Mechanical Engineering Department

Student Name: ...................................................................................................................

Student ID: .........................................................................................................................

RCSS 5202.01 - Embedded Real Time Systems

Midterm 1 Exam

Fall 2018

Sunday Nov. 4th, 2018

Instructions: Please Read Carefully Before Proceeding.

1. The allowed time for this exam is 2:00 hours (120 minutes).
2. Non-programmable calculators are allowed.
3. No books or other aids are permitted for this test.
4. This exam booklet contains 8 pages, including this one, 1-page Appendix, and an extra sheet of
scratch paper, attached and have to be kept attached. Note that if one or more pages are
missing, you will lose their points. Thus, you must check that your exam booklet is complete.
5. Please write your solutions in the space provided. If you need more space, please use the back
of the sheet containing the problem or the extra sheet and make an arrow indicating that.

All the best.

Please, do not write anything on this page.

Question 1 2 3 4 5 6 7 8 Total

Maximum Marks 8 6 9 9 10 9 9 10 70

Earned Marks
 Mechanical Engineering Department
RCSS 5202.01 - Embedded Real Time Systems
Fall 2018
Dr. M. Watheq El-Kharashi

Question 1........................................................................................................... [8 Marks]

In the table below, differentiate between RISC and CISC with respect to the shown aspects.

No. Aspect RISC CISC

a) Data types

b) Addressing modes

c) Required compiler design

d) Static program size

Question 2........................................................................................................... [6 Marks]

State the term that is best described by each of the following definitions.

No. Definition Term

A single computing component with two or more
a)
independent actual processors
A register to hold the address of the next
b)
instruction to be fetched by the processor
A property of RAM that describes the fact that
c) when power is removed and subsequently
restored, the contents of the memory is not lost
An architecture in which there is no separation
d)
between a program and data memory
The convention used to interpret the bytes making
e) up a data word when those bytes are stored in
computer memory
The number of bits describing the microcontroller
f)
data path

Midterm Exam 1 Page 2 of 8

 Mechanical Engineering Department
RCSS 5202.01 - Embedded Real Time Systems
Fall 2018
Dr. M. Watheq El-Kharashi

Question 3........................................................................................................... [9 Marks]

a) Briefly state what the following ARM code fragment overall does. Do not describe what
each statement does. ............................................................................................[3 Marks]

MOV R0, #0
MOV R0, R0, RRX
MOV R0, R0, ROR #31

b) Write an ARM code fragment that stores the 2’s complement of R1 into R0. .....[3 Marks]

c) What is the main difference between the following ARM assembly code segments?
(Assume that LSL exists in the ARM 7 instruction set.) .........................................[3 Marks]

Code segment A Code segment B

LSL R1, R1, #3 MOVS R2, R1, LSL #3
MOVS R2, R1

Difference:

Midterm Exam 1 Page 3 of 8

 Mechanical Engineering Department
RCSS 5202.01 - Embedded Real Time Systems
Fall 2018
Dr. M. Watheq El-Kharashi

Question 4........................................................................................................... [9 Marks]

An ARM instruction sets the status bits to: N = 1, Z = 0, C = 1 and V = 0. Indicate (Yes or No)
which of the following condition codes will allow the next instruction to execute.

EQ NE CS HS CC LO MI PL VS

VC HI LS GE LT GT LE AL NV

Question 5......................................................................................................... [10 Marks]

You know that the single ARM instruction ADD R0, R0, R0, LSL #2 will multiply the
contents of R0 by 5 in-place without using the multiply (MUL) instruction. By using other
shift amounts, or by using different op-codes (such as MOV, MVN, SUB, or RSB), you can
multiply in-place by a wide variety of constants.

Determine, yes or no, if each of the numbers listed below can be used as a multiplier in the
fashion described above. If yes, write down the single ARM instruction that will multiply R0
in-place by the specified constant. If no, explain why not.

1. 7

2. 17

3. 21

4. -7

5. 6

Midterm Exam 1 Page 4 of 8

 Mechanical Engineering Department
RCSS 5202.01 - Embedded Real Time Systems
Fall 2018
Dr. M. Watheq El-Kharashi

Question 6........................................................................................................... [9 Marks]

For each of the following 8-bits binary addition problems, show the sum in binary (8-bits)
and the new values, 0 or 1, of the N (negative), Z (zero), V (overflow), and C (carry) status
bits as a result of the sum. The sign bit is the left-most of the 8-bits.

01110100 01110100 10001101

+10000111 +00111111 +11100101
Sum = Sum = Sum =
N = N = N =
Z = Z = Z =
C = C = C =
V = V = V =

Question 7........................................................................................................... [9 Marks]

Assume the following initial conditions for each of the instructions below. State if each
instruction, if fetched individually, is executed or not and the value of R2 as well as the flags
after the instruction completes. The results of all registers should be represented in
hexadecimal. All numbers are signed unless otherwise stated.

R0 R1 R2 R3 N Z C V
0x6A300ADC 0x3F2005B9 0x4C800DEF 0x95FFE523 1 0 0 1

Executed
No. Instruction R2 N Z C V
(Yes/No)

1 BICMIS R2, R1, R1

2 MOVVSS R2, R1, LSR #5

3 SUBS R2, R0, R0

Midterm Exam 1 Page 5 of 8

 Mechanical Engineering Department
RCSS 5202.01 - Embedded Real Time Systems
Fall 2018
Dr. M. Watheq El-Kharashi

Question 8......................................................................................................... [10 Marks]

a) Trace the execution of the following ARM code segment in the table below. Write the
values of registers R0 and R1 as well as the flags after the completion of each executed
instruction. The results of all registers should be represented in hexadecimal. Write X in
registers and flags where the value is not yet known. ..........................................[8 Marks]

Instruction R0 R1 N Z C V
MOV R0, #86
AND R0, R0, #63
EOR R0, R0, #0x1F
MOV R1, #6
ADD R1, R1, R1, LSL #4
ORR R0, R0, R1
MOV R1, R1, LSR #3
BIC R0, R0, R1

b) Assume that 32 LEDs are connected to an ARM microcontroller running the above code
segment to display the contents of register R0. The least significant bit of R0 is displayed
by LED 0. From the above code trace, find which LEDs will ON at the beginning of the
code execution and which will be ON after the code completes execution. Draw the
waveform displayed by LED 0. ...............................................................................[2 Marks]

Midterm Exam 1 Page 6 of 8

 Mechanical Engineering Department
RCSS 5202.01 - Embedded Real Time Systems
Fall 2018
Dr. M. Watheq El-Kharashi

Appendix
The ARM Instructions
Mnemonic Operation Definition
ADD Add [Rd]  Op1 + Op2
ADC Add with carry [Rd]  Op1 + Op2 + C
SUB Subtract [Rd]  Op1 - Op2
SBC Subtract with carry [Rd]  Op1 - Op2 + C - 1
RSB Reverse subtract [Rd]  Op2 - Op1
RSC Reverse subtract with carry [Rd]  Op2 - Op1 + C - 1
MUL Multiply [Rd]  Op1 x Op2
MLA Multiply and accumulate [Rd]  Rm x Rs + Rn
AND Logical AND [Rd]  Op1  Op2
ORR Logical OR [Rd]  Op1  Op2
EOR Exclusive OR [Rd]  Op1  Op2
BIC Logical AND NOT [Rd]  Op1  NOT Op2
CMP Compare Set condition codes on Op1 - Op2
CMN Compare negated Set condition codes on Op1 + Op2
TST Test Set condition codes on Op1  Op2
TEQ Test equivalence Set condition codes on Op1  Op2
MOV Move [Rd]  Op2
MVN Move negated [Rd]  NOT Op2
LDR Load register [Rd]  [M(ea)]
STR Store register [M(ea)]  [Rd]
LDM Load register multiple Load a block of registers from memory
STM Store register multiple Store a block of registers in memory
SWI Software interrupt [PC]  [r14], [PC]  8, enter supervisor mode

Midterm Exam 1 Page 7 of 8

 Mechanical Engineering Department
RCSS 5202.01 - Embedded Real Time Systems
Fall 2018
Dr. M. Watheq El-Kharashi

Extra sheet

Midterm Exam 1 Page 8 of 8