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Design of Low RBL Leakage Using 10T SRAM

CHAPTER 1
INTRODUCTION
In this chapter, overview of the project, objective, motivation, software and hardware
used, methodology adopted and organization of the report are discussed.
1.1 Overview of project
Power dissipation has become a first class design constraint as we have hit the
utilization wall, and the low power circuit, architecture, and system level techniques are sought
out. In addition, the static random access memory (SRAM) is the most important digital macro
and its portion on a system-on-chip (SoC) is ever- increasing. Decreasing the power dissipation
of SRAM will not only lower the overall system power dissipation, but will also increase the
yield and improve the SoC reliability. Although the six transistor (6T) SRAM cell is a widely
used standard in industry, it has its own limitations. 6T SRAM not only has conflicting read
and write requirements, it also has read static noise margin (RSNM) degradation. With
increasing process variations, achieving specific yield is getting difficult, and novel designs
and techniques, including read and write assist circuits, are adopted at the cost of area, power
dissipation, or speed to improve the read/write stability and increase the number of cells in a
single column .

1.2 Problem Statement

In essence, 6TSRAM has conflicting read and write requirements and transistor sizing
cannot be done independently. Also, 6T has inherit RSNM problem as the read current passes
through the cell internal node, and it further degrades with VDD scaling. Also, being
considered as baseline design, 6T has overall a higher power dissipation, and higher BL
leakages, as the low power techniques employ a certain mechanism to lower the dynamic
power dissipation, e.g., charge sharing, and hierarchical BL and the leakages (by employing
virtual rails). Many alternative bitcells and techniques have been proposed in the literature to
improve SRAM cell stability, reduce the leakage currents, and achieve low power operation
compared with the conventional 6T design.

1.3 Motivation
SRAM cell must robustly operate under hold, read, and write mode. An SRAM cell
uses the positive feedback of cross-coupled inverters (INVs) to store a single bit of
information in a complementary fashion. Access transistors provide the mechanism for the

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Design of Low RBL Leakage Using 10T SRAM

read and write operation. Before every access, column BL pair (BL and BLB) is precharged to
the supply voltage. For the write operation, one of the precharged BLs is discharged through
the write driver.
1.4 Objective

The main objective is to design 10T SRAM and to reduce the RBL leakage . The
value of RBL leakage is reduced by more than 3 orders of magnitude and (ION/IOFF) is
greatly improved compared with the 6T RBL leakage. The overall leakage characteristics of
6T and 10T are similar, and competitive performance is achieved.

1.5 Methodology Adopted

The new 10T static random access memory cell having single ended decoupled read-
bitline (RBL) with a 4T read port for low power operation and leakage reduction. The RBL is
precharged at half the cell’s supply voltage, and is allowed to charge and discharge according
to the stored data bit. An inverter, driven by the complementary data node (QB), connects the
RBL to the virtual power rails through a transmission gate during the read operation. RBL
increases toward the VDD level for a read-1, and discharges toward the ground level for a
read-0. Virtual power rails have the same value of the RBL precharging level during the write
and the hold mode, and are connected to true supply levels only during the read operation.
Dynamic control of virtual rails substantially reduces the RBL leakage.

1.6 Tools Used


1.6.1 Schematic Design Tools
1. Mentor graphics tools: Schematic editor and EZ wave
2. Simulation: eldonet simulator
3. Technology: 130nm

1.7 Organization of the Report

Chapter 1 presents overview of project, motivation and objectives along with its
specifications and applications. Chapter 2 presents literature survey regarding the project have
been studied and various methods to implement the circuit. Chapter 3 presents description of
SRAM cell. Chapter 4 presents design of 10T SRAM cell. Chapter 5 presents results and
discussion. Chapter 6 presents conclusion and future scope of the project.

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CHAPTER 2
LITERATURE SURVEY
2.1 Introduction
In previous chapter, overview of the project, objective, motivation, software and
hardware used, methodology adopted and organization of the report has been discussed. In
this chapter, literature survey is discussed.

2.2 Introduction to SRAM

The technology scaling to deep submicron feature size and the increasing density of
the transistors in integrated circuits (ICs) has encouraged in the research in low power and
robust memory cell designs. Portable devices with limited battery-life require low standby
power processors and memory. Often, embedded static random access memory (SRAM)
arrays can be the dominant part of the whole static power consumption and also occupy large
chip area, thus minimization of memory power is a crucial area of concern for today’s IC
designers. Energy loss is reduced by limiting voltage differences across conducting devices.

This is accomplished through the use of time-varying voltage waveforms. This is also
called adiabatic charging technique. The SRAM working purely on adiabatic charging
principles needs multiple phase power clocks. The design of the SRAM circuit is complex
and not same as the design of the conventional SRAM, but there is huge saving in energy
during writing as well as reading in the design of the SRAM. To overcome the design
complexity and latency of complete adiabatic SRAMs, SRAMs that make use of the adiabatic
charging technique partially have been designed. Based on whether adiabatic charging is
applied to only power supply line or ground line or bit lines and word lines or only bit lines,
there are many types of adiabatic SRAMs. High resistivity switches are also used to vary the
power supply voltage slowly. Adiabatic (Energy recovery) logic is a new promising approach
because they are able to break the lower limit of the energy dissipation in static CMOS which
amounts to 1 2 𝐶𝑉𝑑𝑑 2. Adiabatic circuits achieve low energy dissipation by recycling the
energy stored on their capacitors instead of dissipated as heat.
Before going to implement the proposed work, in the part of literature survey, the
following research papers have been referred to and considered their contents. The literature
in this field exists in a variety of conference and journal proceedings, design and
implementation of hardware efficient multiplier reversible logic gate approach.

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2.3 Research on SRAM Design


Static Random Access Memory (SRAM) is an indispensable part of most modern
VLSI designs and dominates silicon area in many applications. In scaled technologies,
maintaining high SRAM yield becomes more challenging since they are particularly
vulnerable to process variations due to 1) the minimum sized devices used in SRAM bitcells
and 2) the large array sizes. At the same time, low power design is a key focus throughout the
semiconductor industry. Since low voltage operation is one of the most effective ways to
reduce power consumption due to its quadratic relationship to energy savings, lowering the
minimum operating voltage (Vmin) of SRAM has gained significant interest.[1]
Power consumption is now the major technical problem facing the semiconductor
industry. In comments on this problem at the 2002 International Electron Devices Meeting,
Intel chairman Andrew Grove cited off-state current leakage in particular as a limiting factor
in future microprocessor integration.1 Off-state leakage is static power, current that leaks
through transistors even when they are turned off. It is one of two principal sources of power
dissipation in today’s microprocessors. The other is dynamic power, which arises from the
repeated capacitance charge and discharge on the output of the hundreds of millions of gates
in today’s chips. Until very recently, only dynamic power has been a significant source of
power consumption, and Moore’s law has helped to control it. Shrinking processor
technology has allowed and, below 100 nanometers, actually required reducing the supply
voltage. Dynamic power is proportional to the square of supply voltage, so reducing the
voltage significantly reduces power consumption. Unfortunately, smaller geometries
exacerbate leakage, so static power begins to dominate the power consumption equation in
microprocessor design.[2]
As memory begins to dominate chip area in high performance applications, SRAM
has become the focus of technology scaling. Traditionally, SRAM cell size has scaled in
accordance with technology ground rules; however, with the growing importance of
variability, it is feared that this may no longer be possible. Because minimum gate length and
width devices are used to minimize cell area, SRAM is most susceptible to both process-
induced variations in device geometry as well as threshold voltage variability due to dopant
fluctuations. In addition, the impact of variability is most pronounced in SRAM because cell
operation, which depends upon well-matched FETs, must be satisfactory for each individual
cell (no averaging across multiple stages as in logic). The fundamental concern of cell
stability, which determines minimum array operating voltage and yield, has thus become
increasingly difficult to address.[3]

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Advances in process technologies are leading to steady increases in the speeds of


microprocessors and system LSIs. The speeds of SRAMs, which are needed to serve as cache
memories, must keep pace with these increases. Unlike the situation with the threshold
voltage (Vth) of CMOS logic transistors, however, since the read-static-noise-margin (SNM)
deteriorates with decreases in supply voltage (VDD) and increases with the transistor
mismatch accompanied by geometry scaling, there are severe limits to the degree to which the
Vth of nMOS transistors in SRAM cells can be lowered. The SNM problem also makes it
difficult to apply, to SRAMs, dynamic voltage scaling techniques that have been proposed for
reducing the active power consumption of microprocessors and system LSIs. This is because
the minimum supply voltage of LSIs is limited by their SRAMs for the following two
reasons: 1) with decreasing VDD, SRAM delay increases at a higher rate than does CMOS
logic circuit delay, and 2) Read operations at low-VDD levels result in storage data
destruction in SRAM cells. While techniques for boosting VDD in SRAMs have been
proposed in order to achieve both high-speed data access and stable data retention during
Read operations, the use of these techniques can result in the deterioration of transistor
reliability.[4]
Low-power techniques and design have become an essential way to extend the battery
lifetime of portable systems. Many applications, including medical and wireless applications,
even require ultra-low power dissipation at low-to-moderate frequency performance (10 kHz -
100 MHz) . On-chip Static Random Access Memory (SRAM) contains 50- 90% of the total
chip transistor count in average. It is thus one of the major sources of energy consumption in
System-onChip (SoC) operation. Recent research in the Ultra-Low Voltage SRAM memory
has shown that Vopt is in the range between [300, 500] mV. Achieving successfully low-
voltage operations in SRAM faces a considerable amount of challenges due to the reduced bit
cell stability and the degraded Ion-to-I off ratio, and the reduced voltage margins due to the
increase in device variability, e.g. the Random Dopant Fluctuations (RDF) cause large
threshold voltage variability, which impacts directly the SNM (Static Noise Margin,) and WM
(Write Margin) of the bitcell. Furthermore, sensing and overall architecture is difficult to
design, due also to the CAD device model being less precise in the sub-threshold region.[5]
At the device level, leakage reduction can be achieved by controlling the dimensions
(length, oxide thickness, junction depth, etc.) and doping profile in transistors. At the circuit
level, leakage reduction is achieved by controlling statically or dynamically the voltage of the
different device terminals (i.e., gate, drain, source and substrate). An overview of existing
techniques is beyond the scope of this paper but can be found. From a system architectis

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perspective those techniques are a design constraint and part of the low-power standard cell
library specification. In this paper, we focus on architecture level techniques. One key concept
is to lower the supply voltage (VDD) to operate the SRAM cell in the sub-Vth region
(generally referred to as drowsy mode) or gating off the VDD at the expense of destroying the
cell state. An exponential reduction in leakage power as a function of VDD can be exploited
while ensuring stable operating conditions. Modifications of the memory layout are kept to a
minimum which guarantees a low area and integration overhead. These techniques have been
widely used in drowsy cache designs with assistance of static or dynamic activity analysis and
are also the basis of this work.[6]
2.4 Conclusion
In this chapter, literature survey has been discussed.

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CHAPTER 3

SRAM CELL

3.1 Introduction

In previous chapter, literature survey was discussed and also presented.


In this chapter, SRAM cell are briefly discussed.
3.2 6T SRAM Cell

SRAM is semiconductor memory cell. It stores one bit of information. It is faster and
consumes very less power as compared to other memory cells. Due to its robustness and
stability, researchers are interested in further improvement of SRAM cell. SRAM is vital
component in a chip or microprocessor IC. Designing a SRAM cell in nanoscale regime has
become a challenging task because of reduction in noise margins and increased sensitivity to
threshold voltage variation. 10T SRAM cell performs better then 6T SRAM cell in terms of
reliability and stability. 6T SRAM cell has less reliability at low supply voltage due to
degradation in noise margins.

The memory circuit is said to be static if the stored data can be retained indefinitely, as
long as the power supply is on, without any need for periodic refresh operation. The data
storage cell, i.e., the one-bit memory cell in the static RAM arrays, invariably consists of a
simple latch circuit with two stable operating points. Depending on the preserved state of the
two inverter latch circuit, the data being held in the memory cell will be interpreted either as
logic '0' or as logic '1'.

Fig.3.1 Design of SRAM Cell

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The conventional six-transistor (6T) SRAM is built up of two cross-coupled inverters


and two access transistors, connecting the cell to the bit lines (figure 3.2). The inverters make
up the storage element and the access transistors are used to communicate with the outside.
The cell is symmetrical and has a relatively large area. No special process steps are needed
and it is fully compatible with standard CMOS processes.

Figure 3.2.Six-Transistor (6T) SRAM Cell

3.2.1 Read Operation

The 6T SRAM cell has a differential read operation. This means that both the stored
value and its inverse are used in evaluation to determine the stored value. Before the onset of
a read operation, the Word line is held low (grounded) and the two bit lines connected to the
cell through transistors M5 and M6 (see figure 3.2) are pre-charged high (to VCC) . Since the
gates of M5 and M6 are held low, these access transistors are off and the cross-coupled latch
is isolated from the bit lines.

If a ’0’ is stored on the left storage node, the gates of the latch to the right are low.
That means that transistor M3 (see figure 3.2) is initially turned off . In the same way, M2
will also be off initially since its gate is held high. This results in a simplified model, shown in
figure 3.3, for reading a stored ’0’.

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Figure 3.3.6T SRAM Cell at the onset of read operation (reading ‘0’)

The capacitors, C bit, (figure 3.3) represent the capacitances on the bit lines, which are
several magnitudes larger than the capacitances of the cell. The cell capacitance has here been
represented only through the value held by each inverter (Q=0 and Q=1 respectively). The
next phase of the read operation scheme is to pull the Word line high and at the same time
release the bit lines. This turns on the access transistors (M5 and M6) and connects the storage
nodes to the bit lines. It is evident that the right storage node (the inverse node) has the same
potential as BL and therefore no charge transfer will be take place on this side .

The left storage node, on the other hand, is charged to ’0’ (low) while BL is pre-
charged to VCC. Since transistor M5 now has been turned on, a current is going from C bit to
the storage node. This current discharges BL while charging the left storage node. As
mentioned earlier, the capacitance of BL (C bit) is far greater than that of the storage node .
This means that the charge sharing alone would lead to a rapid charging of the storage node,
potentially destroying the stored value, while the Bit line would remain virtually unchanged.
However, M1 is also turned on which leads to a discharge current from the storage node down
to ground. By making M1 stronger (wider) than M5, the current flowing from the storage
node will be large enough to prevent the node from being charged high .After some time of
discharging the bit line, a specialized detection circuit called Sense Amplifier (see figure 2.4)
is turned on.

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Figure3.4. Sense amplifier for a 6T SRAM

It detects the difference between the potentials of BL and BL and gives the resulting
output. Initially the sense amplifier is turned off (sense enable, SE, is low). At the same time
as the bit lines of the 6T cell are being pre-charged high, so are the cross-coupled inverters of
the sense amplifier. The bit lines are also equalized (EQ is low) so that any mismatch between
the pre-charged of BL and BL is evened out.

When the Word line of the memory cell is asserted EQ and PC are lifted and the pre-
charge of the sense amplifier is discontinued. The column selector CS is then lowered to
connect the bit lines to the latch of the sense amplifier. In figure 3.4, for purpose of clarity,
only one column selector transistor for each side of the sense amplifier is present. However,
normally several bit lines are connected to the same sense amplifier, each one with its own
column selector transistor. In this way, several bit lines can be connected to the same sense
amplifier, and the column selectors are then used to determine which bit lines should be read.

After some time, when a voltage difference of about 50-100mV (for a 0.18μm
process) has developed between the two inverters of the sense amplifier, the sensing is turned
on. This is done by raising SE, and thereby connecting the sources of the NMOS transistors in
the latch to gnd. Since the internal nodes were pre-charged high the NMOS transistors are
open and current is being drawn from the nodes . The side with the highest initial voltage will
make the opposite NMOS (since it is connected to its gate) draw current faster. This will
make the lower node fall faster and in turn shut of the NMOS drawing current from the higher
node. An increased voltage difference will develop and eventually the nodes will flip to a
stable state.

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The Out node in figure 3.4 is then connected to a buffer to restore the flank of the
signal and to facilitate driving of larger loads. Also the Out node is usually connected to an
inverter. This inverter is of the same size as the first inverter in the buffer. This is to make
sure that the two sense amplifier nodes have the same load, and therefore will be totally
symmetric. Note that it is essentially the ’0’ that is detected for the standard 6T SRAM, since
the side with the stored ’1’ is left unchanged by the cell. The output is determined by which
side the ’0’ is on; ’0’ on the normal storage node results in a ’0’ output while ’0’on the
inverse storage ode results in a ’1’ output. Therefore the performance is mainly dependent on
the constellation M1-M5 (see figure 3.2) or M3-M6 and their ability to draw current from the
bit line.

3.2.2 Write Operation

For a standard 6T SRAM cell, lowering one of the bit lines to ground while asserting
the Word line does writing. To write a ’0’ BL is lowered, while writing a ’1’ requires BL to
be lowered. Why is this? Let’s take a closer look at the cell when writing a ’1’ (figure 3.5).

Figure 3.5. 6T SRAM Cell at the onset of writing operation (writing ‘0’ to ‘1’)

As in the previous example of a read, the cell has a ’0’ stored and for simplicity the
schematic has been reduced in the same way as before. The main difference now is that the bit
lines no longer are released. Instead they are held at VCC and gnd respectively. It can be seen
from the left side of the memory cell (M1-M5) that it is virtually identical to the read
operation (figure 3.3). Since both bit lines are now held at their respective value, the Bit line
capacitances have been omitted.

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During the discussion of read operation, it was concluded that transistor M1 had to be
stronger than transistor M5 to prevent accidental writing. Now in the write case, this feature
actually prevents a wanted write operation . Even when transistor M5 is turned on and current
is flowing from BL to the storage node, the state of the node will not change.

As soon as the node is raised transistor M1 will sink current to ground, and the node is
prevented from reaching even close to the switching point. So instead of writing a ’1’ to the
node, a ’0’ will be written to the inverse node. Looking at the right side of the cell we have
the constellation M4-M6. In this case BL is held at gnd. When the Word line is raised M6 is
turned on and current is drawn from the inverse storage node to BL. At the same time,
however, M4 is turned on and, as soon as the potential at the inverse storage node starts to
decrease, current will flow from VCC to the node. In this case M6 has to be stronger than M4
for the inverse node to change its state. The transistor M4 is a PMOS Transistor and
inherently weaker than the NMOS transistor M6 (the mobility is lower in PMOS than in
NMOS).

Figure 3.6. Standard 6T SRAM Cell

Therefore, making both of them minimum size, according to the process design rules,
will assure that M6 is stronger and that writing is possible. When the inverse node has been
pulled low enough, the transistor M1 will no longer be open and the normal storage node will
also flip, leaving the cell in a new stable state.

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Designing a SRAM cell in nanoscale regime has become a challenging task because of
reduction in noise margins and increased sensitivity to threshold voltage variation To access
the data contained in the memory cell via a bit line, we need atleast one switch, which is
controlled by the corresponding word line as shown in Figure 3.6.

SRAM cell must robustly operate under hold, read, and write mode. An SRAM cell
uses the positive feedback of cross-coupled inverters (INVs) to store a single bit of
information in a complementaryfashion. Access transistors provide the mechanism for the
read and write operation. Before every access, column BL pair (BL and BLB) is precharged to
the supply voltage. For the write operation, one of the precharged BLs is discharged through
the write driver. A single column of M 6T SRAM cells, where one cell is accessed in read
mode with data = 0 (Qa=0), while other M −1 cells are in the hold mode. Leakage
components are labeled, and for the worst case leakage, all M −1 cells store data = 1 (Qu= 1).

Iread flows from BL to the VSS through AL and NL of the accessed cell, and the BL
voltage is decreased. The unaccessed cell on the BL exhibits BL leakage. IuLeak0 is the main
component of BL leakage while IuLeak1 is negligible, as VDS of AR of the unaccessed cell is
large, while VDS of its AL is very small (varies from 0 to VBL). These leakage components
decrease the differential BL voltage development. As there are a large number of cells in a
single column, the worst case BL leakage can decrease BLB voltage enough to make an
erroneous read. Thus, Iread must be greater than (M −1)×IuLeak0, whereM is the number of
cells in a single column. During read operation, the internal node of the 6T cell storing a zero
(Qa) lies in the read current path and its voltage increases during the read operation. This
increase in voltage (V) is dependent upon transistor sizing.

For a successful read operation, β ratio, defined as (((W/L)N)/((W/L)A)) must be


larger than 1 (typically 2 to 3). The vulnerability of the internal nodes of an SRAM cell is
captured through metrics HSNM, RSNM, and WNM/write trip point (WTP) during hold,
read, and write mode, respectively. The HSNM and RSNM butterfly curve (top) and the
internal state disturbance of node QB for a slow rising WL signal (bottom).

The increase in node Qa voltage not only decreases the cell stability, but also increases
the short-circuit currentfrom VDD to VSS and lets pass (now) the higher amount of leakage
current from BLB (IaLeak1). This decreases the differential BL voltage (VBL) and requires
the increases in WL pulse duration. A wider read pulse can cause dynamic instability and
increases the power dissipation. In addition, for a successful write operation, access transistors

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of the 6T must be strong enough to take over the pull-up pMOS transistors. Thus, γ ratio,
defined as (((W/L)P)/((W/L)A)) must be smaller than 1. However, a stronger pMOS is
beneficial for read operation (to decrease the V), and a weaker pull-down nMOS is beneficial
for write operation (to let access transistors have more strength for injecting current). Thus,
proper sizing is required for specific conditions and application.

3.3 CMOS SRAM Cell

A low power SRAM cell may be designed by using cross-coupled CMOS inverters.
The most important advantage of this circuit topology is that the static power dissipation is
very small essentially, it is limited by small leakage current. Other advantages of this design
are high noise immunity due to larger noise margins, and the ability to operate at lower power
supply voltage. The major disadvantage of this topology is larger cell size. The circuit
structure of the full CMOS static RAM cell is shown in Figure 3.7.

The memory cell consists of simple CMOS inverters connected back to back, and two
access transistors. The access transistors are turned on whenever a word line is activated for
read or write operation, connecting the cell to the complementary bit line columns.

Fig.3.7 Design of full CMOS SRAM Cell

The access transistors are turned on whenever a word line is activated for read or write
operation, connecting the cell to the complementary bit line columns.

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3.4 CMOS SRAM Cell Design

To determine W/L ratios of the transistors, a number of design criteria must be taken
into consideration. The two basic requirements, which dictate W/L ratios, are that the data
read operation should not destroy the stored information in the cell. The cell should allow
stored information modification during write operation. In order to consider operations of
SRAM, we have to take into account, the relatively large parasitic column capacitance and
and column pull-up transistors as shown in Figure 3.8.

Fig.3.8 CMOS SRAM Cell With Precharge Transistors

When none of the word lines is selected, the pass transistors M3 and M4 are turned off
and the data is retained in all memory cells. The column capacitances are charged by the pull-
up transistors P1 and P2. The voltages across the column capacitors reach VDD - VT.

3.5 6T SRAM Operation

The 10T SRAM cell is designed in cadence virtuoso in 180nm CMOS technology and
its performance characteristic has been analyzed. The designed 10T SRAM has write
capability as good as 6T SRAM and improved read stability than 6T SRAM cell. The power
dissipation, delay, and power delay product of the designed 10T SRAM cell are 22.08 x 10-9
W, 39.95 x 10-9 s and 0.8820 x 10-15Ws respectively.

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Fig.3.9 Design of 6T SRAM Cell

Conventional 6T SRAM cell consists of six transistors. Fig.3.9 shows the conventional
6T SRAM cell. Transistors N2 and N3 are access transistor, while remaining four transistors:
N1, N2, P1 and P2 form two inverters. These two inverters are used to latch data. The data
enters into latching inverter through access transistor. The process of introducing a data is
known as write operation and retrieving a data is known as read operation. Word line (WL)
selects a row of SRAM cell. Bit line (BL) and bit line bar (BLB) are use to select a column of
SRAM cell. When both WL and BL are ON, a particular SRAM cell is selected. A 10T
SRAM cell can be designed by using a conventional 6T SRAM cell and an additional read
circuitry.
3.6 SRAM Block Structure

Figure 3.9 shows an example of the basic SRAM block structure. A row decoder gated
by appropriate timing block signal decodes X row address bits and selects one of the word
lines WL 0–WL N-1. The SRAM core consists of a number of arrays of NxM, where N is the
number of rows and M is the number of bits. If an SRAM core is organized as a number of
arrays in a page manner, an additional Z-decoder is needed to select the accessed page.

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Fig.3.10 Block Structure Of SRAM

SRAMs can be organized as bit-oriented or word-oriented. In a bit-oriented SRAM,


each address accesses a single bit, whereas in a word-oriented memory, each address
addresses a word of n bits (where the popular values of n include 8, 16, 32 or 64). Column
decoders or column MUXs (YMUXs) addressed by Y address bits allow sharing of a single
sense amplifier among 2, 4 or more columns. The majority of modern SRAMs are self-timed,
i.e. all the internal timing is generated by the timing block within an SRAM instance.

3.7 Conclusion
In this chapter, SRAM cell have been discussed comprehensively.

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CHAPTER 4

IMPLEMENTATION OF 10T SRAM

4.1 Introduction
In previous chapter, basics related to 10T SRAM are briefly discussed.
In this chapter, implementation of 10T SRAM are discussed comprehensively.
4.2 Precharge Voltage
Precharge of the powerline voltages in a high voltage DC application is a preliminary
mode, which limits the current of the power source such that a controlled rise time of the
system voltage during power up is achieved. When a high-voltage system is designed
appropriately to handle the flow of maximum rated power through its distribution system, the
components within the system can still undergo considerable stress upon the system "power
up". In some applications, the occasion to activate the system is a rare occurrence, such as in
commercial utility power distribution, which is typically almost all of the time. Yet, in other
systems, such as in vehicle applications, activation will occur with every individual use of the
system. When a long life of the components and a high reliability of the high voltage system
are needed, then a power up method, which reduces and limits the power up stress is required.
Reduction of precharge voltage clearly reduces the power consumption, since the effective
voltage swings on bitlines when reduced. We would expect precharge through enhancement
mode NMOS devices to be more effective from a power viewpoint, since the bitline voltage
rises to at most VDD-Vt . While it would be reasonable to assume that setting the precharge
voltage to VDD/2 would be optimal, since the voltage swings would be minimal, it may not
be practically feasible because of the structure of the bitcell.

4.3 Precharge Control Modification

According to the proposed low power test technique, the SRAM memory can operate
in two different modes: a functional mode in which the memory acts normally and a low
power test mode in which the addressing sequence is fixed to ‘wordline after wordline’. The
pre-charge activity is restricted to two columns for each clock cycle of the selected column
and the following one. During the last operation on the last cell of each row, the memory
returns to functional mode for only one clock cycle, in order to restore voltage level of all the
bitline at VDD for the operations in the next row. We propose a practical implementation of
this method consisting in a modification of the pre-charge control circuitry, which allows

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switching between the functional mode and the low power test mode. In the low power test
mode, the precharge is active for the selected column jand the following one, and for this
purpose, we use a precharge signal (Prj); the column precharge signal (Prj), when the column
j is selected; the previous column selection signal (CSjí1), when the column is not selected;
the new precharge control logic is developed.

4.4 SRAM Functional Mode

In random access memories during functional mode, the addressing sequence is


unpredictable. Consequently, all bitlines need to be precharged to 99 VDD, in order to have
all the array columns ready for a new operation. When a cell is selected for a read/write
operation, the corresponding precharge circuit is normally turned OFF during the time
required for the operation. For the columns that are not involved in the operation, the
precharge circuit is commonly left ON and the corresponding cells undergo a stress called
RES (Read Equivalent Stress), as it has been demonstrated.

For example, in an 8kx32 SRAM, organized as an array of 512 rows x512 column,
when a read/write operation is performed on a cell, the other 511 cells of the same row
undergo RESs. When the cell C(i,0) is selected for a read/write operation, the wordline
selection signal WLi is activated and all the cells of the ith row are selected, and thus
connected with their bitlines.

The proposed SRAM system has storage capacity of 8words of 8bits each. To address
these words in a unique manner, 3:8 row decoders are used. Lyon- Schediwy decoder, which
uses lesser number of transistors than the regular AND/NAND decoder, is used for address
generation. Since the decoder is a faster decoder and uses lesser number of transistors, the
power dissipation is greatly reduced. It has 3 input lines and 8 output lines. This decoder can
accept addresses ranging from 000 to 111. According to the address input, the address
decoder activates one of the rows by asserting one of the wordlines and all the other word
address lines remain low. The logical effort of a decoder can be reduced by observing that
only one of the outputs will be high, so the PMOS transistors can be shared among many
outputs. A NOR gate pulls low efficiently through parallel transistor, but, has a poor logical
effort, because the output is pulled high through wide series transistors.

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Fig.4.1 Proposed 10T SRAM cell with row-wise read port dynamic power lines.

A 10T cell proposed adds a 4T read port for an SE read shown in Fig. 4.1. The cell
was designed to provide ultralow leakage for subthreshold operation. RBL leakage is
substantially reduced at the cost of area and performance.

4.5 PROPOSED CELL AND LOW POWER TECHNIQUE

Design of 10T SRAM Cell

The proposed 10T SRAM cell with SE RBL is shown in Fig4.1. We have added a 4T
read port to the 6T cell to decouple the internal nodes during the read operation. Read port
consists of an INV P1-N1 driven by node QB, and a transmission gate (TG) P2-N2. The
output (Z) of the INV is connected to RBL during the read operation through TG, which is
controlled by (read) control signals. Furthermore, read port is powered by virtual power rails,
VVDD and VVSS, which are dynamically controlled. These virtual power rails (control
signals) run horizontally, and have the true rail values only duringthe read operation.For the
RBL leakage reduction, both the virtual rails have the same level as the precharge level of
RBL. The 10T SRAM cell using an INV and a TG has been proposed earlier . However, our
proposed 10T scheme is different from the previous design in the following aspects.

1) The previous INV+TG-based 10T cell was application specific, while our proposed
design is generic.

2) We have used the dynamically controlled power rails for the read port.

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3) We precharge RBL at VDD/2, while the previous 10T design eliminated the
precharge phase, and used INV to fully charge or discharge the RBL.

4) The basic read technique of both the designs is completely different. The main idea
of the proposed design is “the charging or the discharging of the read BL from VDD/2 for
every read operation.” The previous design either discharges from VDD to VSS, or charges
from VSS to VDD.

5) A powerful INV was used previously to produce full VDD swing on the RBL. In
the proposed design, RBL is precharged at VDD/2, and only a small voltage difference
(comparable with 6T) is produced for every read cycle.

6) In the proposed design, for every read cycle the RBL will exhibit some change
(positive or negative) from its precharged value of vdd/2. However, the RBL would not
change for consecutive similar bit reads. RBL would change only if consecutive read bits are
different.

Fig.4.2 Schematic Diagram of 10T SRAM Cell

4.6 Precharge And Read Operation

The proposed 10T SRAM (hereafter referred to as LP10T) is precharged by VP


supply, which has a value half that of the supply voltage (i.e., VP =vdd/2). For the read
operation, R goes high and RB goes low and thus the TG is activated to connect RBL to the
node Z. If QB is 0, then N1 is OFF and P1 connects node Z to the VVDD, which is high for
the read operation. Thus, the read current flows from VVDD (having value of vdd) to RBL
(which has value of vdd/2) through P1-TG. Hence, the RBL voltage increases toward the vdd

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level. Now, for a read-0 operation (i.e., QB=1), P1 is turned OFF and N1 connects node Z to
the VVSS, which is low (0V) during the read operation. Thus, the read current flows from
RBL (having value vdd/2) to the GND through TG-N1, and hence RBL voltage decreases
toward 0 V. For the efficient read operation, we have used the boosted read (R and RB)
signals, which are 1.2× nominal signal levels. This allows higher current to flow in both the
directions. Boosted signals have been used to improve the performance degradation due to the
half-vdd swing available for each read operation, as is the proposed precharging scheme. The
levels of control signals and the change in RBL voltage during read, precharge, and hold
mode. 8T and LP10T are both SE, and their output is sensed by a sense amplifier with a
reference voltage. The increase and decrease of the RBL level of LP10T is differentiated by
the sense amplifier referenced at the vdd/2 level. LP10T provides voltage differential (VBL)
at RBL for both the read-0 and read-1, which relaxes the performance constraints compared
with the SE 8T. Use of TG in LP10Timprovesthe efficiency of read-1operation,as the single
nMOS could not charge well the RBL through P1. Furthermore, sizing of read port is
important in terms of area and performance.

One precharging circuit is connected for every column to precharge the


complementary bitlines, BL and BLB, to “1” state during inactive state of memory. The
signal ‘PRECHARGE’ is used for this purpose. The precharge circuit is isolated from the
bitlines during the memory write and read operations. The precharge circuit is one of the
essential components used in SRAM. The function of SRAM is to charge the bit and bitbar
lines to VDD=1.8 V.The precharge circuit enables the bitlines to be charged high at all times,
except during read and write operations. The width required for PMOS is minimum i.e., 240
nm and the length is fixed to 180 nm. For each column, a single precharge circuit is used.

Capacitance variation has to be considered in conjunction with precharge transistor


variations to design an optimized timing circuitry. The simulation for write recovery under
global transistor variation, capacitance variation and local mismatch are obtained. Each effect
is brought to the worst (slow) and best (fast) corner to investigate the impact on timing.

4.7 10T SRAM Cell For Precharge Scaling

The 10T SRAM cell with precharge logic is designed to improve the performance and
to increase the speed of operation. The readout inverter fully charges/discharges a read bitline,
there is no precharge circuit on the read bitline. Thus, the power is not consumed by
precharging, but, is consumed only when a readout datum is changed. This feature is suitable

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to video processing since image data have special correlation and similar data are read out in
consecutive cycles shown in Figure 4.2.

The design of 10T SRAM cell with precharge logic is introduced to improve the
performance and to increase the speed of operation. Precharge is used for precharging and
equalizing of bit and bit-bar lines during data hold operation for a better read and write
operations. Here, PMOS transistors are used for precharging and middle transistor is used for
equalization. Generally, precharge voltage level is kept at VDD.

Enhancement mode NMOS devices 97 operating in their active region, depletion


mode NMOS or standard PMOS devices operating in the saturation region are employed. The
second technique uses clock pulse, which clocks the percentage circuitry to ensure that
precharge occurs when the core is not being accessed. It should be apparent that the clocked
technique avoids static power consumption at the expense of power required to drive the
clocked precharage. This method is more advantageous and can only be determined on a case-
by-case basis.

4.8 Leakage Reduction

Virtual power rails run horizontal and are shared by the cells of a row. These rails are
activated during read operation, (i.e., VVDD is connected to VDD, and VVSS is connected to
ground). During the hold and write mode, these virtual rails have value of vdd/2. These
control signals are read and hold/write mode, the state of read port transistors in the
hold/write mode. As both the virtual rails have voltage level vdd/2 during nonread, the
voltage of node Z stays near vdd/2 value. As RBL is precharged at vdd/2 level, and read
signals are not activated (TG is OFF), RBL leakage is reduced substantially due to near zero
VDS of TG. Also, the boosted read signals help reduce the leakage currents, as the VGS of
pMOS (P2) becomes more positive.

4.9 Design Of Sense Amplifier

Sense amplifier (SA) is an important component in any memory design. The choice
and design of a SA defines the robustness of bitline sensing, impacting the read speed and
read power. Due to the variety of SAs in semiconductor memories and the impact they have
on the final specs of the memory, the sense amplifiers have become the separate classes of
circuits. The primary function of a SA in SRAMs is to amplify a small analog differential

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voltage developed on the bitlines by a read-accessed cell to the full swing digital output
signal, thus greatly reducing the time required for a read operation. Since SRAMs do not
require data refresh circuitry after sensing, the sensing operation must be nondestructive.

Fig.4.3 Design Of Sense Amplifier

The sensing starts with biasing the latch-type SA in the high-gain meta-stable region
by precharging and equalizing its inputs. Since, in the latch-type SA, the inputs are not
isolated from the outputs, isolation transistors are needed to isolate the latch-type SA from the
bitlines and prevent the full discharge of the bitline carrying a ‘0’, which costs extra power
and delay. Due to the presence of the column MUX/isolation transistors, two precharge
equalize circuits are needed to ensure reliable sensing.

4.10 Reduction Power In Sense Amplifier Circuit

The function of the sense amplifier is to amplify small differential bitline voltages into
logic levels. This operation should be performed as fast as possible. While numerous sense
amplifiers exist, some of the common forms employed for SRAMs are either simple
differential amplifiers or charge amplifiers that are similar to bit cells. A natural trade-off
occurs between speed and power for such sense amplifiers.

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Fig.4.4 Design Of Sense Amplifier For 10T SRAM

The analog nature of sense amplifiers often results in their consuming an appreciable
fraction of the total power. Sense amplifiers are enabled by a sense amplifier enable signal.
Schemes employed for reducing the power requirements of sense amplifiers can be
differentiated, based upon the point at which they are 120 activated.

The second scheme employs sense amplifiers that automatically cut off after the sense
operation. In fact, detailed techniques required to achieve the first form has been explained
earlier. The self-timed RAM core can be extended for obtaining the sense amplifier enable
signal. It is used to set up an SR flip-flop in the set state. Once the dummy sense amplifier has
finished sensing, it resets the SR flip-flop, which in turn disables the enable for the sense
amplifiers. In every sense amplifier, the sense action gets completed, before the dummy sense
amplifier senses it.

Fig.4.5 Power Output Of Sense Amplifier Circuit In 10T SRAM

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An alternative method shapes the tail current of differential amplifiers by activating


pull-down transistors of different transistors in sequence. Self-latching sense amplifiers
accomplish an automatic limiting of currents after sense. The structure of a latched sense
amplifier is shown in Figure4.4 . The structure can be visualized as a cross-coupled
amplifying inverter loop, with additional transistors to transfer bitline voltages to the inverter
loop.

Table.4.1 Power Calculations Of 10TSRAM Cell Using Precharge Logic

Table 4.1 shows various power calculations with a input voltage range 0 to 1.8V at
different temperature conditions for precharge circuit design during read and write operation
of 10T SRAM cell.

4.11 Comparision Between 8T & 10T SRAM Cell

Table.4.2 Table Representing Comparision Between 8T &10T SRAM

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The 8T and 10T circuits consume less power 81% and 65% respectively and transition
delay decreases as compared to 6T SRAM cell. Though the area increases 30% in 10T SRAM
cell compared to 8T SRAM cell, the power is reduced to 60%.It is also observed that if the
temperature Time (sec) 122 increases from 25°C to high value, the total power increases with
respect to time in 8T SRAM cell. In case of 10T cell, if the temperature increases from 25°C
to 50°C, the power increases, but, above 50°C, the power remains constant.

4.12 10T SRAM Circuitary Clock At 3.1GHZ

Memory plays a continually more important role in digital and mixed-signal circuits,
but a key for future designs is minimizing the amount of chip area occupied by high-speed
memory circuitry. According to an earlier forecast by the International Technology Roadmap
of Semiconductors (ITRS), memory will occupy at least 90% of a digital chip’s area by
2013. The performance of system-on-chip (SoC) devices will increasingly rely on the
capabilities of static random-access-memory (SRAM) circuitry, encouraging the development
of higher-performance SRAM. High-performance process technologies, such as 65-nm silicon
CMOS, offers the means for producing higher-performance SRAM while also maintaining
compact size. Scaling technology, however, has deteriorated the stability of conventional six-
transistor (6T) SRAM cells.This occurs for several reasons, such as process variations that
happen during manufacturing, which lead to SRAM transistor parameter variations.
In addition, threshold mismatches can occur due to intrinsic device fluctuations,
significantly reducing an SRAM cell’s static noise margin (SNM). As a result, external noise
can disrupt the SRAM voltage during a read operation. Also, growing consumption of
memory by leakage energy shrinks the effective amount of memory for an SRAM device. In
modern microprocessors, leakage current consumes more than 40% of total active-mode
energy. For these reasons, the need for a stable, low-power, high-speed SRAM design for
microprocessors and SoCs became evidently clear. The design is a 16-kb, triple-port (one
write port and two read ports, or 1W2R), 10-transistor (10T) SRAM cell.

Here, the SNM is much higher than in a conventional 8T SRAM cell, and supply-
voltage variations exert little effect on read SNM. One large advantage that 8T SRAM cells
offer over 6T SRAM cells is that they can be readily scaled with technology, although 8T
cells will be limited by supply voltage and SNM.

The minimum width and length of the SRAM cell areas are assumed to scale by a
factor of 0.7 per cell generation. If the voltage supply is reduced to +0.8 V dc, the area of the
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standard 6T SRAM cannot be shrunk further due to the large width that’s required for the
pull-down transistors in the 6T memory structure. In conventional 8T SRAMs, the speed of
SRAM access can be increased by using sense amplifiers to detect and amplify bit-line signals
and eventually transform them in a read operation.

During a write operation, write data are transferred to desired cells by driving data on
bit-line pairs by grounding either the main bit-line or complementary bit-line. In contrast, the
10T SRAM cells export full-swing voltages by grounding the single-ended read bit-line and
writing data like an 8T SRAM cell by driving data on the write bit-line pairs. In addition, with
separate read/write ports, a read/write multiplexer is not needed, which generally simplifies
local evaluation circuitry and makes it possible to design a completely independent read/write
path.

4.13 Conclusion
In this chapter, implementation of 10T SRAM has been discussed comprehensively.

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CHAPTER 5

RESULTS AND DISCUSSIONS

5.1 Simulation Results of 10T SRAM

Fig.5.1 Output Waveforms of 10T SRAM

In the above figure, Fig.5.1 ,the inputs given are word line (W), bit line (BL), bit line
bar (BLB), Read Bit (RB), Read (R). The outputs obtained will be read bit line (RBL), Q, QB.

When W=1, BL=1, BLB=0, Q=1 and QB=0. When W=0, BL=0, BLB= 1, Q=1 as it
holds the previous value of BL.

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5.2 Symbol of 10T SRAM

Fig.5.2 Symbol of 10T SRAM

In the above figure, Fig.5.2, the symbol of 10T SRAM is explained. It consists of dc
voltage as 3.3.v and supply voltages.

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CHAPTER 6

CONCLUSION AND FUTURE SCOPE

This thesis concludes by making comments on the contributions and findings of the
research and suggestions for future enhancements.

6.1 Conclusion

In this paper, we have presented our 10T SRAM cell that uses a 4T read port and SE
RBL. RBL is precharged at half the supply voltage and, during the read operation, is charged
or discharged according to the bit stored. For a read-0 operation, RBL discharges through TG
and nMOS transistor, and for the next precharge, RBL is supplied current by VP. For a read-1
operation, RBL is charged from vdd/2 to vdd by virtual read port. For the next precharge,
RBL level is decreased and current flows from RBL to VP. By precharging through VP
(which is half vdd) and charge recycling mechanism, LP10T only dissipates half the average
read dynamic power compared with 6T. Overall leakage power of LP10T is similar to 6T,
however, RBL leakage is reduced by more than 3 orders of magnitude, and thus a higher
number of cell could be integrated on a single column.

6.2 Future Scope

On the basis of the studies and the investigations carried out in this research, as an
extension of this work the following points are suggested.

The 10T SRAM cell can be implemented with 120 nm, 90 nm and 32 nm CMOS
technology for the above low power techniques. Temperature analysis can also be done for all
the circuits using hotspot tool. Static Noise Margin(SNM) is one of the parameters for
designing any SRAM circuit. So, this can be considered for 8T,10T and 12T SRAM cell with
4x4 SRAMs cell array. To increase the pull-up ratio, the speed of operations of SRAM cell
increases. Further, to increase the performance of SRAM cell, the SNM and pull-up ratio can
be varied for the design of SRAM cell. This designed circuit can be implemented with any
type of processor recently used in markets.

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REFERENCES
1. J. Singh, S. P. Mohanty, and D. Pradhan, Robust SRAM Designs and Analysis. New York,
NY, USA: Springer-Verlag, 2012.
2. N. S. Kim et al., “Leakage current: Moore’s law meets static power,” Computer, vol. 36, no.
12, pp. 68–75, Dec. 2003.
3. L. Chang et al., “Stable SRAM cell design for the 32 nm node and beyond,” in Symp. VLSI
Technol. Dig. Tech. Papers., Jun. 2005, pp. 128–129.
4. K. Takeda et al., “A read-static-noise-margin-free SRAM cell for lowVDD and high-speed
applications,” IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 113–121, Jan. 2006.
5. T. Song, S. Kim, K. Lim, and J. Laskar, “Fully-gated ground 10T-SRAM bitcell in 45 nm SOI
technology,” Electron. Lett., vol. 46, no. 7, pp. 515–516, Apr. 2010.
6. E. Seevinck, F. J. List, and J. Lohstroh, “Static-noise margin analysis of MOS SRAM cells,”
IEEE J. Solid-State Circuits, vol. 22, no. 5, pp. 748–754, Oct. 1987.
7. M. H. Abu-Rahma, M. Anis, and S. S. Yoon, “Reducing SRAM power using fine-grained
wordline pulsewidth control,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no.
3, pp. 356–364, Mar. 2010.
8. B. D. Yang, “A low-power SRAM using bit-line charge-recycling for read and write
operations,” IEEE J. Solid-State Circuits, vol. 45, no. 10, pp. 2173–2183, Oct. 2010.

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APPENDIX
Introduction:

This document gives a rough overview of how to design & simulate things with Mentor
graphics Tools. There are Ten basic steps:

1.Invoking Mentor Graphics

2.Creating Library & Cell

3.Creating Schematic

4.Generating Symbol

5.Creating Test bench

6.Simulating the Schematic

7.Creating a Layout

8.Routing the Layout

9.Physical Verification of Layout

10.Waveform Comparision

1.Invoking Mentor Graphics:

First of all we will open the linex os then the view will be

Right click in the linex window Desktop and click on open in terminal

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Type csh and press enter.


Type source /home/softwares/cshrc/cshrc130.cshrc and press enter
Type cd /home/softwares/FOUNDRY/GDK/PYSIS_SPT_HEP and press enter then it will
enter to the PYSIS_SPT_HEP folder.
Type ./pyxismgr and press enter then pyxis project manager window will be invoked
as shown below..

Where the project navigator window is shown then click on the file To create a new project click on
File → new project which invokes the new project window as shown

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Browse on the folder and specify the project path and the file name is user defined and click
on OK

After libraries have to be added to the project. In order to add the technology files browse on
the folder

Browse the folder to


home/softwares/FOUNDRY/GDK/PYSIS_SPT_HEP/ic_reflibs/tech_libs and select the
generic13 file click on OK.

Again click on OK then manage external/logic libraries window will pop up as


shown. Click on the Add Standard Libra

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Then the libraries will be added up as shown below and click on OK

Then the pyxis project manager window will be shown where the technology libraries
are added to the project and are placed below the project name

2.Creating Library & Cell:

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To create a library right click on the project name and select new library Or click on the icon
on the icon bar

Then a new library window will pop up asking for the library name. Then name the
library and click on OK.

To create a cell right click on the library and select new cell Or click on the icon on the icon
bar

Then a new cell window will pop up asking for the cell name. Then name the
cell and click on OK.

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To create a schematic right click on the and select new schematic Or click on the icon on the
icon bar

Then a new schematic window will pop up asking for the schematic name. Then name the
schematic and click on OK

Now name the schematic and click on OK which in turn leads to the pyxis schematic editor
window as shown

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3.Creating Schematic:

In this section you will become familiar with placing primitive analog devices for a
inverter.
You’ll learn how to:
• place primitives on the schematic
• select and manipulate devices
• customizing hotkeys for placing devices
• route devices
• edit device parameter values
• name instances
• check and save the schematic
• create upper hierarchical symbols
• create test bench
• simulate using Eldo
• view results.

From the left icon bar press on add instance icon

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Then a file browser which contains entire libraries will pop up as shown

Next click on the double click on generic13 in the library list

And then follow the path to select pmos from $generic13/symbols/pmos as shown
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Select the pmos and click on OK to place the pmos on the workspace as shown

Then change the width and length of the pmos device can change by using object Editor

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Select the nmos and click on OK to place the nmos on the workspace as shown

Then change the width and length of the nmos device

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To select the VDD and ground from the generic lib or click on the library in the layer palatte
window then layer palatte will be shown as ic library window. Then select generic library and
place VDD and ground

After selecting the generic lib we use the VDD and ground to pick and place in the required
locations

Give the connects in between the VDD to pmos and ground to nmos and both pmos & nmos
gates and, source and drain of p & n mos devices

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Place in IN and OUT ports in a similar way as above from the generic library or click on the
add ports icon in the left icon bar and connect the circuit

To change the name, enter the name in the field given for the net name and
press enter. Then the schematic will be as shown

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After completing the inverter we have to save and chick it

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4.Generating Symbol:

To generate a symbol select Add in the menu bar and then select generate
symbol from pull down menu bar
Add→generate symbol

A generate symbol will pop up as shown

Then activates symbol, replace existing and choose shape and click on the customize pinlist
and click on OK symbol will be generate

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After that click on to chick and save

The chick and save is an impotence to shown the result to an window which shows the error
report where the errors and warnings in the symbol can be seen

5.Creating Test bench:

To create a test bench close the pyxis schematic and symbol windows and go back to
pyxis project manager window. In the project manger window to create new cell right click on
the manual library below the project name and select new cell or select the library and click

on the icon in the icon bar.

Then a new cell window will pop up asking for the cell name in which give the cell name and
click OK Here the test bench cell name has been specified as inv_tb.

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Right click on the test bench cell and select new schematic which in turn opens pyxis
Schematic editor window.

Now instantiate the new inverter symbol by selecting Add > Instance from the left
icon Palette or pressing the hot key i. Select the Symbol view of the inverter cell from the inv
cell of the manual library
Place the symbol on the work space as shown

• Add the IN and OUT net as before by selecting the hot key i. Name the nets with hot key
“q”.

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• Add a DC voltage source dc_v_ source, from the MGC_IC_SOURCES_LIB. Change the
value of the DC property to be 1.2V. Add PULSE voltage source pulse_v_source and
change the value of the pulse_value property to be 1.2V change also the delay to be 0S.
• Add Ground ports in a similar fashion.
Finally the circuit looks like the following

Next click on check/save icon in the icon bar

This will result to an window which shows the error report where the errors and warnings in
the symbol can be seen.

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6.Simulating the Schematic:

After chick and save the schematic test bench then run simulation from this icon

Then entering simulation mode window will be popup in that select New Configuration

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In the New Configuration select SPICE Netlister and type sim in the configuration name and
click on OK

After click on OK then the window will appeared like this

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Go for selecting AC,DC,TRAN then setup simulation window will be open

After appearing setup window select To set up analysis select analysis in the simulation
panel and in the analysis set up select the required analysis and set the values of the analysis
in the beside window as shown above
Here I have selected the DC analysis with the start time as 0ns,stop time=5 ns and
print timestep=0.1ns as shown . After specifying the values click on apply

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Here I have selected the transient analysis with the stop time=1000ns After specifying the
values click on apply

.
To load the libraries, select the libraries in the setup simulation panel and click on Edit

Then Edit libraries window will popup in that we import library from library path
home/softwares/FOUNDRY/GDK/PYSIS_SPT_HEP/ic_reflibs/tech_libs/generic13/mode
ls/lib.eldo file.

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In the edit libraries window we can edit Edit corners/Familes and Edit scenarios also just
selecting TT and click OK

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Select the Edit Probes in the setup simulation panel

Go back to the inverter schematic test bench and select the IN,OUT andcome back to the
setup simulation

In the setup simulation window, set the analysis to both DC and Tran, and Task to plot and
type to voltage, click Add button then the port will be added to the waveform as shown

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After adding the analysis, eldo models and probing waveforms minimize the setup

simulation window and run the simulator.bTo run the simulation select from the
left icon palette or select simulate-> run simulation

View the simulation results by selecting the plot results from latest run icon from the left
icon palatte. This will open EZ Wave for you with the output waveforms. This is how the
waveforms look like after zooming

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EZ wave 12.1 production window popup to the view of waveform for IN & OUT

Click on Measurement tool in the icon bar which opens up the measurement
tool window where we can measure the different properties of your waveforms

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save these waveforms as an idal

7.Creating a Layout:

To create a layout select inv cell ,right click on the cell and select new layout

The new layout window is popup in that the layout name is same as the cell name which is
given in the first and click on OK

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Pyxis layout window will be invoked with a new layout sub settings as shown and click on
OK

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Make the Schematic window active by selecting it with the LMB. Select PMOS and Press on

the Pick & Place icon from the SDL tool bar on the Icon Bar. The tool will
place the device on the Workspace of IC layout window. Similarly select the NMOS and
place it on the workspace

Note: To make SDL toolbar active, goto setup->toolbar->SDL tool bar

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With the layout window active, select the Pick Place Ports icon from the SDL toolbar.

Place Schematic ports window will pop up . Select the VDD port and select a layer for this
port. The Width and Height will be updated automatically according to the minimum metal1
dimensions. Press Apply to place the port.

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Place the rest of the ports

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To add the substrate contacts to the mosfets. Select Add Device icon from the Left Hand
Palette then select Path-based Guard Band select psub

Do the same for but choose nwell instead of psub

To add the over flow lines for both psub & nwell , Select psub then Connectivity > Net > Add
to Net to set psub to Ground and the same for nwell to set it to VDD

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8.Routing the Layout:

Manual roting

To start routing press on the IRoute icon in the SDL toolbar. Once you place the cursor on
where you want to start routing, it will start guided by the fly lines. You can toggle between
the connectivity layers by pressing space-bar

Route the all the ports in the layout except input port as shown

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For routing poly and input port of M1 VIA has to be created.


VIA CREATION:
select route in the ic palatte window as shown

Now select Options in ARoute Setup then following window will be invoked

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Then Advanced route options window pops up,select the VIA OPTIONS check use via
generator and click OK and OK

Select Iroute ,place ploy on the input and start route as shown
Now press SPACE BAR automatic VIA will be created

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And just left click and route to M1,the layout will be as shown

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9.Physical Verification of Layout:

1. DRC
2. LVS
3. PEX

1.DRC:

Now you can verify the layout by running DRC and LVS checks. we will run Calibre
Interactive
RUNNING CALIBRE INTERACTIVE DRC:
• In the pyxis layout window, Select Tools_Calibre_Run DRC
• This will bring up the Calibre Interactive – DRC

Note: Make sure the tabs named Rules,Inputs,Outputs,Run control should be green in color as
shown above which ensures the paths specified are correct. Otherwise paths have to be
changed .

Select Run DRC in the Calibre Interactive window

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The Calibre RVE window will popup and you should see the following results

Click on the result where the red mark is shown

The error in the layout will be highlighted as shown in the fig once if you select on the error

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Here the error is due to the percentage of the polysilicon. It requires polyarea coverage of
14% which is not possible in the smaller circuits. So you can ignore that error

Add text on ports window will pop up. Here click on OK then automatically port names will
be assigned to layout

The ports are added is shown in below

2.LVS:

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Select Tools > Calibre > Run LVS entry from the pull down menu.
The Calibre Interactive – LVS window will popup. The Inputs and Netlist tabs are active as
shown

Select Run LVS in the caliber interactive window shown above

Calibre RVE window will popup and you should see results similar to this

If the comparison is wrong click on the comparison results in the RVE window, which
shows the results and select schematics then the netlists will be displayed as shown

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Click on the comparison result if the comparison is correct or not.

Click on the schematics to see the layout netlist and source netlist

Doble click on the layout netlist and the source netlist to see the connections is correct or not

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3.PEX:

Select Tools Calibre > Run PEX entery from the pull down menu

The Calibre Interactive – PEX window will popup. Make sure Export from schematic
viewer is selected while the Inputs and Netlist tabs are active as shown

Choose the output netlist to be in DSPF Format as in the figure below

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Select Run PEX


The PEX Netlist file windows will be invoked as shown

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Save the PEX net list file

Save the Netlist file as inv.pex.dspf in any location of your computer

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File successfully written click on OK

Select start RVE from caliber interactive pex.


Calibre RVE window will pop up select parasitics in the navigator then extraction results will
be shown as shown below

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Double click on the port name then the parasitic values will be shown

Double click on the value, then corresponding value will be highlighted in the layout as
Shown

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Open the test bench schematic and enter the simulation mode, then select the inverter block

A window named Add DSPF will pop up where browse on the folder to the saved Netlist
inv.pex.dspf and click OK as shown

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Selected the saved Netlist inv.pex.dspf and click OK as shown

Click on OK

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Run the simulation by selecting run simulation icon on left icon panel

View the wave’s output signal

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There is a noticable increase in the delay due to the parasitic


Save the waveforms as practical

10.Waveform Comparision:

To compared the waveforms we must save the both ideal and practical waveforms i.e. test
bench waveform and layout waveform

In EZ wave 12.1 production window select

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Open the both ideal and practical waveforms on the current open database

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In EZ wave 12.1 production window select the tool menu and click on the waveform compare
wizard

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Browse the choose reference dataset from list or disk to the comparing waveforms and click
next batton

Click on the compare all waveforms and click next batton

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Click on finish batton

Then the final result has bee shown

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