1)

A high priority Interrupt has occurred while executing the third instruction. Th
e processor jumps to the vector table location 0x0010 and from there jumps to th
e ISR and executes it. After completing the ISR, to which address the control wo
uld return to?
1000 MOV A, 20
1004 MOV B, 30
1008 MULT A, B, C
100C MOV C, L1

a)0x0010
b)0x0012
c)0x100C
d)0x1008
Sorry, the correct answer is c. When the interrupt occurs while executing an ins
truction, it will complete the current instruction. So, after completing the ISR
, the control would return to fourth instruction.
2)
Which of the following task is not performed as part of the Kernel Startup?

a)Initialization of Memory Management system

b)System enters main and is ready to start C style function
c)Initialize task and inter task communication system
d)Initializes I/O sub systems
Sorry, the correct answer is b. At the end of C startup, the system is ready to
execute C style Functions. It calls the C function main() which in turn performs
the kernel startup
3)
What is FALSE about HAL (Hardware Abstraction Layer)?

a)HAL helps to improve the system performance

b)It helps to port the software to different hardware.
c)If HAL interfaces are defined, then concurrent development of the software and
hardware design can be carried out.
d)It helps to reduce the development cycle
Sorry, the correct answer is a. HAL is an abstraction layer implemented in softw
are, between the physical hardware and the software. The wrapper code adds over
head to the underlying driver codes, making it easy from portability and usage a
ngle, but not from performance point of view
4)
What is the difference between bootloader and boot monitor?

a)Boot monitor actually performs diagnostic support in addition to boot loading

b)It can work as debug agent
c)It can support in firmware upgrade.
d)All of the above.
Sorry, the correct answer is d. Boot monitor usually provides/supports all the t
hree facilities: diagnostics,debug agent and firmware upgrade
5)
DMA controller has a bus clock frequency operating at 100Mhz. It is able to do a
data transfer of 4 byte data at the raising edge of the clock. How many bytes o
f data will be transferred by the controller in 0.5 sec?

a)400 Mbytes
b)200 Mbytes
c)100 Mbytes
d)50 Mbytes
Sorry, the correct answer is b. The amount of data transferred in 1 sec is 4 * 1
00 * 10^6 and hence in 0.5 secs it is 200 Mbytes of data
6)
What is False about DMA controller?

a)Is used to transfer data from one memory to another memory or from an I/O devi
ce to memory
b)It shares the system memory and bus with the CPU and has both bus master and s
lave capability.
c)The DMA controller releases the system bus for the duration of the transfer, t
he process is referred as cycle stealing
d)When CPU uses internal cache memory, the DMA controller can use the system mem
ory parallely.
Sorry, the correct answer is c. The CPU actually releases the system bus for the
duration of transfer, and hence it is referred as cycle stealing. All other sta
tements are true about DMA.
7)
What is not true about the block device drivers?

a)Most block devices have support for character device interfaces

b)Block device classes can be used through UNIX style API's like fopen(), ioctl(
), fclose()
c)Block devices are those for which don't use buffer cache
d)All of the above
Sorry, the correct answer is c. Normally the block devices use buffer cache mech
anism to improve performance.
8)
Which of the following devices is preferred during the initial phase of developm
ent where there is volatility in the requirements?

a)FPGA
b)ASIC
c)GAL
d)All of the above
Sorry, the correct answer is a. The manufactures normally prefer Field programma
ble Gate array during the early stage of the development because it can be repro
grammed to reflect any changes
9)
A 9600 bps serial communication link with asynchronous mode of transmission uses
one start bit, seven data bits, one parity bit and one stop bit. How many chara
cters can be transmitted per second ?

a)800
b)960
c)1200
d)1000
Sorry, the correct answer is b. Each character requires 10 bits (1 start bit + 7
data bit + 1 parity bit + 1 stop bit) to be transmitted for each character. So
, 960 characters can be transmitted over 9600 bps link.
10)
A system has 8 MB of physical memory and 2048 physical pages. What will be the
size of the physical page and the virtual page?

a)2048 Bytes and 1024 Bytes

b)2048 Bytes and 4096 Bytes
c)1024 Bytes and 1024 bytes
d)4096 Bytes and 4096 Bytes
Sorry, the correct answer is d. Physical page size = Physical memory/number of p
hysical page = 4096 Bytes. The virtual page is same as that of physical page siz
e
11)
What is TRUE about the periodic timer?

a)In the periodic timer, count value becomes zero, it generates an interrupt to
the processor ONLY once
b)It is not possible to configure the timer as periodic
c)Periodic timer can be used by the RTOS to carry out scheduling or software tim
er services.
d)None of the above.
Sorry, the correct answer is c. In the periodic timer, when it because zero, the
value is reloaded again and it is possible to configure the timer as oneshot or
periodic using the control registers
12)
An Embedded system receives 4 signals through the 4 pins of an input port. Whic
h of the following will be most suitable to analyze the input signals?

a)ICE
b)Breakpoint
c)Logic Analyser
d)Voltmeter
Sorry, the correct answer is c. Logic analyzer is used to track/analyze differen
t signals simultaneously. Hence it can used to analyze 4 signals simultaneously
13)
You are developing a cost effective embedded system where the LCD display is not
available to display the error messages. Which approach you will take up to ide
ntify the errors so that you can debug it easily?

a)Write error code in shared memory location and use those error codes for debug
ging.
b)If file system is available, log the errors in a error_log.txt file
c)Check the possibility of writing the errors in Non volatile memory
d)All of the above.
Sorry, the correct answer is d. You can write error codes in some shared memory
location and interpret these codes to carry out debugging. If file system is ava
ilable in the embedded system, you can write the error codes to a text file and
use that for debugging. You can also write it in the Non-volatile memory, so tha
t after the system is switched OFF and powered ON you can read the error codes a
nd perform debugging. The option can vary depending upon which is suitable/feasi
ble for that system.
14)
Identify the problem in the below code snippet. Task 1, Task2 and Task3 are of e
qual priority and the system has the time slice of 5msec. Identify the problems
see with respect to Task1,2 and 3? Assume that task 1 starts running 1st.
int write_count = 0;
Task_func1 ()
{
Acquire write_Lock1
Write to the file1
Release write_lock1
Write_count++
}
Task_func2 ()
{
Acquire write_lock2
Write to file 2
Release write_lock2
Write_count++
}
Task_func3(inputbuffer, size)
{
Acquire Read_lock
if(size is 0)
return INVALID
Memorycopy(tempbuffer, inputbuffer, size)
Release read_lock
return SUCCESS
}

a)Task_func1 and Task_func2 will enter deadlock condition

b)Task_func1 and Task_func2 will enter deadlock condition and Task_func3 synchro
nization is not handled properly.
c)Task_func1 and Task_func2 will enters race condition
d)Task_func1 and Task_func2 will enters into a race condition and Task_func3 syn
chronization mechanism is not handled properly
Sorry, the correct answer is d. Task_func1 and Task_func2 are updating a global
variable Write_count++, which is outside the synchronization lock. The context s
witch can happen at any given point while executing Task_func1 and Task_func2 re
sulting in wrong updation of the variable WriteCount. In Task 3, sync mechanism
is not handled properly, i.e. the semaphore Read_lock is not released after the
size 0 condition.
15)
Which of the following is most important aspect of a RTOS?

a)Deterministic behaviour
b)Support for latest chipsets/processors
c)Support for modern protocols
d)None of the above
Sorry, the correct answer is a. Deterministic or predictable behaviour is the mo
st the important aspect of the real time system. Only then, it is possible to ca
lculate the worst case response for time critical events.
16)
Which of the following is CORRECT about the initialisation of a RTOS based embed
ded system?

a)Kernel initialization step initializes only the internal modules of the RTOS.
b)Kernel initialization creates the various RTOS resources needed by the applica
tion.
c)Application Initialization is done as part of the kernel initialization.
d)Application Initialization will never do any hardware initializations.
Sorry, the correct answer is a. Kernel initialization step initializes all the i
nternal modules of the RTOS so that the RTOS is ready to service all the API cal
ls made by the application. It does not create any resources needed by the appli
cation. Application initialisation is done after kernel initialisation. It creat
es all the RTOS resources needed by the application by calling the appropriate c
reate APIs. Hardware initializations are done by the boot loader. Yet, the appli
cation initialisation can also reinitialize some of the hardware according to th
e requirements of the application. It can initialize some of the application spe
cific hardware which was not initialized during the boot load operations.
17)
Which of the following is NOT CORRECT?

a)A task is a RTOS object/resource created inside the RTOS by calling the approp
riate APIs provided by the RTOS.
b)A function becomes a task when it is made as an entry function of a task by pa
ssing it as an argument to the task create API provided by the RTOS.
c)A function should have an infinite loop like a while(1) loop for it to be made
as a task.
d)None of the above
Sorry, the correct answer is c. A task or any other RTOS resource is an object i
nside the RTOS. It is created by calling the appropriate APIs provided by the RT
OS. To create a task, we have to write a function. This function should be passe
d as an entry function to the RTOS API. It is not necessary that the function mu
st be implemented using a while(1) loop. If the function is implemented using an
infinite loop like a while(1) loop, then it becomes a continuous running task a
nd it never finishes it exits explicitly or killed. If it does not have a while(
1) loop then the task ends after the first execution. Typically, in an embedded
application, all tasks are created using infinite loops. During initialisation p
hase, a single execution task may be created and used.
18)
Which of the following is CORRECT when a task t2 preempts a task t1?

a)The current register contents of the CPU are saved into the stack of the outgo
ing task t1 and updated by the values already saved in the stack of task t2.
b)The program counter of the processor is updated with the address of the next i
nstruction of task t2
c)There is only one stack pointer available in the CPU and hence there cannot be
different stacks available for task t1 and t2.
d)When preemption happens, the CPU changes its mode. Each mode has its own stack
from which the registers have to be updated.
Sorry, the correct answer is a. Task t1 is being preempted. Hence the current re
gister contents of CPU will be saved in the stack of t1. t2 is the new task whic
h is getting scheduled. Hence the registers will be updated with the values alre
ady saved in t2 stack. Each task will have a task control block(TCB) in the RTOS
. One of the elements of this structure is a stack pointer (a software pointer).
This will be pointing to the stack allocated to that task. The hardware stack p
ointer register will be updated with this value. Thus each task will have a sepa
rate stack to store its context. There is no hardware mode change happens when a
task is preempted by another task.
19)
Device A and Device B can be treated as equal priority, while Device C has a hig
her priority.
Which two devices can be connected to the same interrupt pin?

a)Device A and Device C

b)Device A and Device B
c)No two devices can be connected to the same interrupt pin.
d)Both A. and B. are true
Sorry, the correct answer is b. "Multiple devices of the same priority alone can
be connected to the same interrupt pin. This allows for boards, where number of
devices is greater than interrupt pins."
20)
Watchdog timer in a processor is used for

a)Providing timing delay in software applications

b)Used for debugging timers
c)Countdown timer, which on expiry resets the processor.
d)Timer used for providing clocks at a different frequency than the system clock
.
Sorry, the correct answer is c. "Watchdog timers are used for detecting deadlock
ed , or starved tasks or infinite loops. It is a countdown timer, which on expir
y will reset the processor. "
21)
Assume memory size is 256 bytes. What needs to be the minimum width of the addr
ess bus to be able to access all the values in the memory?
a)16 bits
b)32 bits
c)8 bits
d)4 bits
Sorry, the correct answer is c. "To address 256 bytes equal to 2 power 8, we nee
d 8 address lines. Hence address bus width should be 8 bits."
22)
What is TRUE of a fetch cycle of an instruction?

a)Whichever address is present in the PC, it fetches the instruction from that a
ddress, and stores the instruction in the Instruction Register
b)Whichever address is present in the instruction register, it fetches from that
address, and stores the instruction in the PC.
c)After fetching the instruction, address contained in the Instruction register
is incremented
d)PC holds the address of the current instruction, while the Instruction registe
r holds the address of the next instruction.
Sorry, the correct answer is a. " PC always holds the address of the instruction
to be fetched. And when the data from the address held in the PC is fetched, th
at data, which is nothing but the instruction opcode, is stored in the Instructi
on Register. After fetching the instruction, PC is incremented to hold the addre
ss of the next instruction to be fetched"
23)
What is TRUE about a zero address machine?

a)A zero address machine has instructions which are stored in the CPU itself and
hence no operand memory address is applicable to these instructions
b)A zero address machine fetches instructions only from stack memory
c)A zero address machine fetches operands only from stack
d)A zero address machine will have zero memory
Sorry, the correct answer is c. " A zero address machine have instructions like
add , move etc which do not specify any operand address. By default the operands
are pushed and popped from/to address stored in stack pointer register, i.e fro
m/to stack."
24)
In memory mapped I/O

a)It is possible for CPU to write data into a device register by writing into sp
ecific memory locations
b)It is possible for CPU to write data into a device register by directly access
ing I/O port
c)It is possible for CPU to write data into a device register only through speci
al instructions
d)It is not possible for CPU to write into device registers
Sorry, the correct answer is a. " In memory mapped I/O, the I/O registers are ma
pped to specific memory locations. By writing into these memory locations, using
the normal memory load and store operations, the data is transmitted from CPU t
o device. "
25)
When a DMA transfer is happening, which of the following statements is TRUE?

a)It is possible for a CPU to read instructions from memory.

b)It is possible for a CPU to read and write data into memory.
c)It is possible for a CPU to be in the execute stage of an instruction.
d)Both a. and b.
Sorry, the correct answer is c. " When a DMA transfer is happening the memory bu
s connecting the CPU and the memory is occupied in the transfer. Hence the CPU c
annot do any memory reads/writes. But it will be able to do register reads, or o
ther operations involving other hardware units within the CPU. It can perform th
e execute stage of the instruction pipeline, even though a DMA transfer is happe
ning at the same time. "
26)
What is the advantage of a CISC machine over a RISC machine?

a)Because its instruction set is complex, the same C code produces more assembly
code lines than in a RISC machine.
b)Results in lower memory footprint.
c)Pipeline is more efficient
d)Instruction lengths are equal
Sorry, the correct answer is b. "CISC machines reduces number of instructions in
a program. Hence it results in lesser code and lesser memory footprint "
27)
Which mechanism can be used to transfer data from a CPU register to I/O port?

a)DMA
b)I/O mapped I/O
c)Memory mapped I/O
d)Both b. and c.
Sorry, the correct answer is d. " Both I/O mapped I/O and Memory mapped I/O can
be used to transfer data from CPU register to I/O port. In the case of I/O mappe
d I/O, this can be done by a special instruction, which transfers the data from
the register to the I/O port and in the case of memory mapped I/O, the I/O ports
are mapped to specific memory locations. By writing into these memory locations
, the data gets transferred from register to I/O port. However in DMA, the data
is always transferred to/from devices and memory, but it doesn t reach the CPU "
28)
What is the advantage of Von Neumann over Harvard?

a)Instruction set will only contain equal length instructions and hence efficien
t pipeline
b)CPU and memory hardware will be more simpler and cheaper
c)Self modifying code is possible only in Von Neumann
d)Both b. and c.
Sorry, the correct answer is b. "Since Von Neumann has a common bus for both ins
truction and data memory transfers, the hardware to send and receive data to/fro
m memory is common. However in Harvard, these buses are separate and the hardwar
e is more complex and costlier"
29)
Which of the following is triggered due to software instruction errors like Divi
de by zero?

a)Interrupt service routine

b)Reset vector
c)Exception Handler
d)Error handler user function
Sorry, the correct answer is c. " An exception handler is not called like a func
tion. It is automatically called whenever there are implicit instruction executi
on errors like Divide by zero. Interrupt service routines are also not called e
xplicitly like functions, but are called when software and hardware triggered in
terrupts occur. Explicit error handler functions are called by user. Reset vecto
r is also implicitly called whenever reset pin is asserted "
30)
An RTOS based application requires the RTOS to provide scheduling time slice of
2msecs and software timer services of 5msecs granularity. It has to provide real
time clock(RTC)feature. But the clock should not drift its accuracy more than 1
sec per day. Assume that there is only one hardware timer and it is designed to
be clocked at 10Mhz frequency.We need to select the correct timer tick, correct
counter value that needs to be loaded to the timer and also the accuracy of the
clock(ppm)needed to meet the RTC requirement. Which of the following options wil
l provide the best chance of meeting all the above criteria?

a)Timer tick = 1ms;HW timer load value=10000;clock ppm value<=11PPM

b)Timer tick = 2ms;HW timer load value=20000;clock ppm value<=12PPM
c)Timer tick = 1ms;HW timer load value=5000;clock ppm value<=12PPM
d)Timer tick = 1ms;HW timer load value=5000;clock ppm value<=15PPM
Sorry, the correct answer is a. " The RTOS requires a hardware timer tick(i.e. t
imer interrupt)for providing scheduling time slice and also for providing softwa
re timer services. Since the time slice has to be of 2msec duration we cannot ch
oose the RTOS timer tick of >2msec period. But the SW timer services provided ne
ed a granularity of 5ms(odd number). If we choose a 2ms timer, then the granular
ity of the SW timer services will get impacted(it will become either 4 or 6ms).
So, to satisfy both, we should choose a 1ms timer tick to be provided to the RTO
S. The timer is clocked at 10Mhz. So, its input clock period is 1/f = 0.1microse
c. For getting a 1ms timer interrupt, we should load the counter value of the ti
mer with a value of 10000. The RTC should not drift more than 1sec per day. A da
y has 24*60*60=86400secs. Converting into ppm(parts per million) it should be (1
/86400)*1000000 = 11PPM(approx). We have to ask the hardware engineer to clock t
he timer module with a crystal oscillator of <=11ppm accuracy to meet the RTC ac
curacy requirement."

31)
A device is providing 10000 bytes/sec of data to a real-time computer. This data
comes in 4 equal bursts of burst duration 10 msecs each within the one sec peri
od. The system is capable of processing the data at 10000 bytes/second. If the s
ystem uses a double-buffer, what should be optimal size of each buffer without l
osing any data?

a)0 bytes
b)10000 bytes
c)2500 bytes
d)1000 bytes
Sorry, the correct answer is c. "Since the data is coming in bursts of 10 ms, an
d in10ms, 10000 * 10 m = 100 bytes can be processed by the consumer. There are f
our bursts in one second and 10000 bytes being produced. Hence, there are 10000
/4 = 2500 bytes being produced in a burst. Hence the processing speed is not suf
ficient. Hence even though the data production and consumption rate is equal in
this case, we need to provide a buffer. The buffer should be capable of holding
at least one burst size, i.e 2500 bytes. For 2500 bytes the processing time will
be 2500/10000 = 250ms. Assuming that the 10ms bursts are equally(periodically)
spaced, it is sufficient to hold one burst size in one buffer. By the time the t
hird burst arrives ( at a time of 500ms, it can overwrite the first buffer, sinc
e it is already processed at the end of the first 260ms ) Note that a single buf
fer will not be sufficient in this case, because by the time the second burst ar
rives, the first burst is not yet consumed. "
32)
In an RTOS based application, which of the following is FALSE?

a)Pipes are typically used for streaming audio and video data between tasks. The
messages posted to pipes cannot be prioritised.
b)Message queues are typically used for exchanging command and control informati
on between tasks. The messages in message queues can be prioritised.
c)Usually, an Event occupies only one bit in an eventgroup. Hence a 32 bit eveng
roup supports 32 events that can be used for communication between various tasks
.
d)None of the above.
Sorry, the correct answer is d. Pipes are used for large chunks of data to be pa
ssed across tasks while message queues are used for exchanging commands and cont
rol information. Messages in pipes cannot be prioritised where as those in messa
ge queues can be prioritised. For using an RTOS event, an eventgroup has to be c
reated and in that eventgroup, each bit represents individual events.
33)
Which of the following is TRUE?

a)From an ISR, sending message to a message queue is allowed as long as it is no

t a blocking call.
b)Sending an event from the ISR to a task is good option since it does not block
and is also faster.
c)We cannot wait for receiving messages or events in an ISR.
d)All the options are correct.
Sorry, the correct answer is d. We can send messages from the ISR to some tasks
but we should not block if the message queue is full. We can send events from th
e ISRs. The event sending APIs do not have blocking options and hence there are
no issues. Since interrupts are asynchronous and have to be completed faster, it
is not possible to be waiting to receive a message or event in an ISR.
34)
Which of the following is TRUE

a)A Mutex is a type of binary semaphore used for protecting critical resources f
rom simultaneous access by multiple threads of execution.
b)When a task which has obtained a mutex, tries to acquire the same mutex again,
it will acquire it successfully without getting blocked.
c)If a task has obtained a mutex and a different task tries to acquire that mute
x, it will block on that mutex.
d)All the above.
Sorry, the correct answer is d. A Mutex is a type of binary semaphore used for p
rotecting critical resources from simultaneous access by multiple threads of exe
cution. The mutex remembers the task which has already acquired it and if the s
ame task tries to acquire it again, it keeps a count of the number of such reque
sts and allows successful acquisition. When the mutex is being released, that ta
sk has to release it that many times so that the mutex will be available for acq
uisition by any other task. If a different task tries to acquire an already acqu
ired mutex, it will immediately block
35)
Which of the following is TRUE about the characteristics of an RTOS and a
monolithic OS like Linux?

a)In RTOS and Linux, kernel mode execution is preemptible.

b)In RTOS and Linux preemption happens when the time slice is over.
c)Linux and RTOS are monolithic operating systems
d)None of the above.
Sorry, the correct answer is d. In RTOS, kernel mode execution is preemptible wh
ere as in Linux Kernel mode execution is not preemptible. Linux uses round robi
n scheduling where preemption happens only when the time slice is over whereas i
n RTOS it also happens when a higher priority task becomes READY. Unlike Linux,
a RTOS is not monolithic. Hence its components like file system, network stack
etc can be removed to get smaller memory foot print.
36)
Which of the following is FALSE about calling the scheduler of an RTOS?

a)A periodic timer interrupt has to call the scheduler function.

b)Scheduler has to be called by the RTOS API which is called by the application
c)RTOS has to call the scheduler without any assistance from the application or
the timer interrupt.
d)None of the above.
Sorry, the correct answer is c. The scheduler function of the RTOS does the sche
duling of the various tasks. But who calls this scheduler function? The ISR of
a periodic timer interrupt calls the scheduler periodically. This period is call
ed the time slice. Also it has to be called whenever the RTOS API is called by
the application. Once the API completes its functionality, it will call the sch
eduler at the end of the API. So, it is not that the RTOS has to call the schedu
ler without the assistance of the application or the interrupts
37)
Assume that a RTOS based multitasking application has the following 3 tasks. All
the 3 tasks have the same priority and hence will be scheduled in round robin f
ashion. The time slice is 1ms.
Assume that send and receive message APIs take negligible time.
Assume that context switch time is negligible. Assume task A starts first at 0th
ms.
List out various tasks that will be running at 1ms interval
from 0th to 10th ms assuming task A starts at 0th ms.
task A
{
Simulate_msg()//Simulate msg from task C for the first time this
task is scheduled.Takes negligible time.
while(1)
{
receive(msg from task C);// blocks here to get a message (except for the f
irst time)
process_msg();
send(msg to task B);//takes 2ms till send completes.
some_more_processing()// takes 1ms
}
}
task B
{
while(1)
{
receive(msg from task A);//blocks here to get a message
process_msg();
send(msg to task C);//takes 2ms till send completes.
some_more_processing()// takes 1ms
}
}
task C
{
while(1)
{
receive(msg from task B);//blocks here to get a message
process_msg();
send(msg to task A);//takes 2ms till send completes.
some_more_processing()// takes 1ms
}
}

a)A A B A B C B C C C
b)A B C A B C A B C A
c)A A B B C C C A B B
d)A A B B C A B C C A
39)
If a function uses global variables, which of the following is true regarding th
e reentrancy of the function?
a)Protect the access to each of those global variables using one or more mutex i
nside that function.
b)Make those global variables as part of a private control block which will be u
sed only by one task.
c)If the function will be called by only a single thread of execution, then it i
s safe to use the global variable without any mutex protection.
d)All the above.
Sorry, the correct answer is d. If a task uses a global variable and if that var
iable is shared with any other task, then it has to be protected by a mutex. If
it is not a multi tasking environment and if there are no interrupts which are
sharing that variable, then there is no need for protecting the variable using m
utex. Similarly, if the global variable is stored in a private data structure us
ed only by that task, then also it need not be protected by the mutex.
40)
Which of the following is TRUE?

a)Task A and Task B are in race condition if their behaviour and hence the syste
m behavior changes based on the order in which they are scheduled.
b)Race condition can be avoided by sequencing the tasks by using semaphores or m
essages or events.
c)Deadlock condition can be avoided by enforcing an order in which the semaphore
s can be obtained.
d)All the above.
Sorry, the correct answer is d. Two tasks can race against each other and result
in an unexpected behavior based on the order of execution. This can be avoided
by sequencing their execution by using semaphores. When using multiple semaphore
s, we can enforce an order in which the semaphores have to be used. This will av
oid the deadlock conditions.
41)
In a priority based preemptive system, which of the following is TRUE?

a)A task which runs without blocking has to be given the highest priority.
b)A task which runs without blocking has to be given the lowest priority.
c)Whether it blocks or not, does not impact the decision of its priority.
d)None of the above.
Sorry, the correct answer is b. A task which continuously runs without blocking
has to be given the lowest priority. Otherwise it will not allow any other task
lower than its priority to be scheduled.
42)
Which of the following is TRUE?

a)Round robin scheduling is first-in-first-out scheduling without time slice.

b)Priority preemptive system does not preempt a task unless a higher priority ta
sk gets ready.
c)When an interrupt occurs, the scheduler switches out the current running task
and schedules the ISR.
d)None of the above.
Sorry, the correct answer is d. Round robin scheduling is first in first out wit
h time slice. Priority preemptive systems will follow round robin scheduling am
ong tasks of equal priority. In such a case, the preemption happens when the tim
e slice is over. When an interrupt occurs, the CPU directly takes the control to
the interrupt vector and then to the ISR. It is not scheduled by the scheduler.

43)
Consider the following set of tasks, with the time values given in msecs.
TaskName Burst Time Arrival Time Priority
A 2 2 P1
B 4 0 P2
C 3 4 P2
D 1 3 P3
Each task prints the numbers starting from 1, 2, 3,...,incrementing the number b
y 1 for every 1 millisecond it is executed. The printed number is prefixed with
corresponding task id. The system uses priority based preemption scheduler with
1ms time-slice. What would be the output for this
scenario?
Note: CPU Burst time is the time a task requires to complete execution when it e
xecutes alone and has all resources required. Arrival time is the first occurren
ce of task execution. Also note that priority P1 is the highest priority.

a)B1 B2 A1 A2 B3 C1 B4 C2 C3 D1
b)B1 B2 A1 A2 C1 B3 C2 B4 C3 D1
c)A1 A2 B1 B2 B3 C1 B4 C2 C3 D1
d)B1 B2 A1 A2 B3 B4 C1 C2 C3 D1
Sorry, the correct answer is a. Task B arrives at time 0 and runs for 2 ms till
Task A arrives at 2nd msec. Task A runs for 2ms and completes. Then task B runs.
But task C has already arrived at 4rd msec. But it is not scheduled and only ta
sk B is scheduled because task B got preempted by task A and got into the ready
queue at the 2nd msec itself. Task B and C have the same priority. So, as per ro
und robin Task B gets scheduled again and runs for 1msec. Then task C runs for 1
msec. Once task B and C complete, the lowest priority task D gets scheduled and
runs for 1msec.
44)
Consider an embedded system running 3 tasks shown below. The context switching t
ime is negligible.
What is the approximate CPU utilization of each of these tasks if they are sched
uled in a round-robin fashion, if the scheduler time-quantum is 2 ms?
send_task()
{
while(1)
{
do_something();//takes 2 msec
send_io_data();//waits for 2msec for send to be completed by the i/o devic
e
}
}

receive_task()
{
while(1)
{
do_something();//takes 2 msec
recv_io_data();//waits for 2msec for i/o device to fill recv buffer
}
}
process_data_task()
{
while(1)
{
process_data();//Takes 4msec every time called
}
}

a)Send - 17% Rcv - 17% Process - 66%

b)Send - 25% Rcv - 25% Process - 50%
c)Send - 33% Rcv - 33% Process - 33%
d)None of the above.
Sorry, the correct answer is b. When a task is doing a I/O bound operation, the
CPU is not loaded and the I/O device is busy doing sending or receiving of data.
During this time, the CPU is not being utilised. Since it is round robin, each
task gets a time slice of 2ms per cycle. Once all tasks get one time slice, agai
n the next round starts Here, once the send and receive tasks spend 2ms each, th
ey are into the I/O bound mode where the CPU is not used and the I/O device is b
usy. During this time the send and receive tasks do not use the time slice and h
ence the process task gets that time also. So,for every 4 time slices, send task
uses one time slice, receive task uses 1 time slice and the process task uses 2
times slices. So, send task uses 2 out of 8 msecs, receive task uses 2 out of 8
msecs and process task uses 4 out of 8 msecs.
45)
In a priority preemption RTOS based system, assume the following 3 tasks t1, t2
and t3 with priorities p1,p2 and p3 respectively where p1<p2<p3. There are 3 mut
exes m1, m2, m3 being shared by them as shown in the code.
int t1 (void)
{
while (1)
{
lock_m3();
lock_m2();
do_job1();
release_m2();
release_m3();
}
}
int t2 (void)
{
while (1)
{
lock_m1();
 lock_m2();
do_job2();
release_m2();
release_m1();
}
}
int t3 (void)
{
while (1)
{
lock_m1();
lock_m2();
lock_m3();
do_job3();
release_m3();
release_m2();
release_m1();
}
}
Will there be deadlock caused by this code? If so how to fix it?

a)No deadlock and no fix needed.

b)Causes Deadlock. Make t1 code similar to t3
c)Causes Deadlock. Make t1 code similar to t2
d)Causes Deadlock. Make t1 and t2 code similar to t3.
Sorry, the correct answer is b. Take all mutexes in the same order and release t
hem in the correct order to prevent dead lock. Task t1 has lower priority than t
ask t3. Assume that it got preempted by task t3 after taking the mutex m3. Now t
ask t3 takes m1 and m2 and tries to take m3 and it will block since m3 is alread
y taken by task t1. So, task t1 will get scheduled and it will try to take m2. B
ut m2 has already been taken by task t3 and hence task t1 also will block. This
is a deadlock condition. To fix this, change the code of task t1 to take all mut
exes in the same order in which task t3 is taking and release them in the correc
t order to prevent dead lock. This same order has to be maintained by any other
task which tries to take these mutexes. Then we can avoid the dead locks. Task t
2 does not have to change the code like that of Task t1 since it does not use m3
. It uses only m1 and m2 and it is being taken in the correct order as taken by
the task t3.