MODEL PAPER-1

Subject: Fundamentals of HDL SUBJECT CODE: 06ES45

Max marks : 100 Duration: 3Hrs
Note: Answer any five full questions selecting at least two from each part

Q Part A marks

1 a Differentiate between VHDL and Verilog HDL 6

b Discuss different logical operators used in HDL. Illustrate each of them with an 10
example.
c What is logic synthesis? 4
2 a Write a data flow description of a full adder with enable. Draw the Truth table of 4
this adder and derive the Boolean function after minimization.

b With relevant example, explain the signal declaration and signal assignment 4
statements.
c What are the data types available in VHDL? 4
3 a Explain different loop statements in HDL 8
b Write a Behavioral Description of D Latch using Variable and Signal assignments. 12
4 a What is module Instantiation, explain with an example 8
b Write the HDL description of 2x1 Multiplexer with Active Low Enable in 12
VHDL / Verilog.

Part B

5 a Write a HDL code for converting a binary(fraction) to a real number. 10

b Describe all file processing tasks in Verilog with examples. 10

6 a Explain implementation of two dimensional arrays in VHDL 10
b Explain Fetch and Execute cycles of a basic computer for an addition operation. 10
7 a How to invoke VHDL module from a Verilog module. 10
b Explain Mixed Language Description of an AND gate 10
8 a Explain synthesis steps 10
b Explain function mapping with example. 10
 MODEL PAPER-2

Subject: Fundamentals of HDL SUBJECT CODE: 06ES45

Max marks : 100 Duration: 3Hrs
Note: Answer any five full questions selecting at least two from each part

Q Part A marks

1 a Describe different types of HDL Description with suitable example. 10

b Discuss different types of HDL objects. 6

c What is HDL? Why do you need it? 4
2 a The following VHDL code describes an SR latch. Translate the code to Verilog. 10
Entity SR is
Port (S, R : in bit; Q : buffer bit; Qb : out bit);
End SR;
Architecture SR_DtFL of SR is
Begin
Q <= s or ( not R and Q);
Qb <= not Q;
End SR_DtFL;
b Write a data flow description of a system that has three 1-bit inputs a(1), a(2) and 10
a(3) and one 1-bit output b. The least significant bit is a(1) and b is 1 only when
(a(1)a(2)a(3) = 1, 3, 6 or 7 ( all in decimal), otherwise b is 0. Derive a minimized
Boolean function of the system and write the data-flow description.
3 a What are the facts of Behavioral Description. 4
b Explain the Booth algorithm with a flow chart. Write VHDL/Verilog description for 10
4X4 Booth algorithm.
c Use the case statement to describe a 3 bit logical shift of register. The register 6
should have a right/left control signal to control the direction of shift
4 a What is Binding? Discuss binding between library & components 6
b Design a counter that counts 0, 2, 3, 5, 7, 0, 2, … using the state machine approach. 14
Show all details of your answer. Write VHDL/Verilog code.
Part B

5 a Explain the following with syntax (i) Procedure in VHDL (ii) Tasks in Verilog 10
with suitable examples in both the cases.
b Describe all file processing tasks in VHDL with examples 10
6 a What is necessity of Mixed-Type Description 4
b Write about User-defined types and Packages in VHDL 8
c Write a program to arrange ‘n’ numbers in ascending order using 8
one dimensional array
7 a How to invoke Verilog module from a VHDL module. 10
b Explain Mixed Language Description of a JK flip-flop with a clear pin 10
8 a What is synthesis information from entity and module 10
b Explain signal assignment statements and variable assignment statements with 10
example