Development of a FPGA-based Control IC for PMSM Drive

with Adaptive Fuzzy Control

Ying-Shieh Kung*, Member IEEE Chia-Sheng Chen Kiing-Ing Wong Ming-Hung Tsai
Department of Electrical Engineering
Southern Taiwan University of Technology
No.1 Nan-Tai Street, Yung-Kang, Tainan County, 710
TAIWAN
*e-mail:kung@mail.stut.edu.tw

Abstract – A new generation of Field Programmable Gate Array
(FPGA) technologies enables to integrate an embedded
processor IP (Intellectual Property) and an application IP into a
SoPC (System-on-a-Programmable-Chip) environment. The
development of high performance speed control of a permanent
magnet synchronous motor (PMSM) drive based on this SoPC
environment is presented in this paper. Firstly, the mathematic
model of PMSM is defined and the vector control used in the
current loop of the PMSM drive is explained. Then, an adaptive
fuzzy controller is constructed by using the fuzzy basis function
and parameter adjustable mechanism, which is used to cope
with the dynamic uncertainty and external load effect in the
PMSM drive. After that, a FPGA-based control IC is designed
to realize the controllers. The FPGA-based control IC has two
IPs, an Nios embedded processor IP and an application IP. The
Nios processor is used to perform the function of an adaptive
fuzzy control in speed loop of PMSM drive. The application IP is
used to perform the current vector control of the PMSM drive,
which includes SVPWM generation, coordinate transformation,
PI controller and the pulse detection of the quadrature encoder.
The former is implemented by using software due to the
complicated control algorithm and low sampling frequency
control (speed control: less than 1kHz). The latter is
implemented by hardware due to the need of high sampling
frequency control (current loop: 16k Hz, PWM circuit: 4~8MHz)
but simple computation. At last, an experimental system has
been set up and some experimental results have been
demonstrated.
I. INTRODUCTION
Owing to the advantages of the superior power density,
high performance in motion control - fast positioning and
better accuracy, permanent magnet synchronous motors
(PMSM) have gradually used in many automation control
fields as an actuators [1]. But in industrial applications, there
processor, low power consumption and higher density for the
implementation of the digital system [5]. Many practical
applications in ac motor control have been studied [6-8]. But,
the researchers used the FPGA only to realize the hardware
part of the overall servo control system.
Nowadays, an embedded processor and IP design can be
developed and downloaded into FPGA to construct a SoPC
environment [9-10]. Therefore, in this paper, a high
performance servo control IC with adaptive fuzzy control is
designed for PMSM drive under this SoPC environment, and
it is shown in Fig.1. In the proposed FPGA-based control IC,
it has two IPs, a Nios embedded processor IP and an
application IP. The Nios processor IP is used to implement an
adaptive fuzzy control algorithm by software, and the
application IP is used to realize the current vector control
scheme by hardware. Therefore, all of the functions to build
up a high-performance PMSM drive can be integrated in a
single FPGA. The FPG chip here adopts Altera Cyclone
EP1C20, which has 20,060 LEs, maximum 301 user I/O pins,
total 294,912 RAM bits, and a Nios embedded processor has
a 16-bit or 32-bit configurable CPU core, 1 to 20Kbytes
available on chip and maximum 4G bytes off-chip memory.
II. SYSTEM DESCRIPTION AND DESIGN
The internal architecture of the proposed FPGA-based
servo system for the PMSM drive is shown in Fig. 2. The
adaptive fuzzy control in the speed loop is realized by using
the software method under the Nios embedded processor. The
current vector control scheme for PMSM is implemented by
using PLD.
Rectifier
L Inverter
+ + +
TA TB TC

ac source U,V,W
are many uncertainties, such as system parameter uncertainty, C
−
TA TB
− −
TC Load
external load disturbance, friction force, unmodeled
uncertainty, always diminish the performance quality of the encoder

PMSM
pre-design of the motor driving system. To cope with this Isolated and driving circuits

problem, in recent years, many intelligent control techniques PWM1 PWM6

LP filter
circuit
[2-4], such as fuzzy control, neural networks control, adaptive ia
fuzzy control and other control method, have been developed ADC

and applied to the precision position control of servo motor Digital circuit (PLD) ib
of current vector ADC

drive to obtain high operating performance. External

control for PMSM
A, B
A, A
B, B

Due to the progress of VLSI technology in recent year, the memory

z
Comparator
circuit
z, z
FPGA has brought more attention before. The advantages of Embedded Processor IP Application IP
(Nios Processor)
the FPGA includes their programmable hard-wired feature,
FPGA_based control IC
fast time-to-market, shorter design cycle, embedding
Fig.1 FPGA-based control IC system for PMSM drive

0-7803-9252-3/05/$20.00 ©2005 IEEE 1544

 FPGA-based control IC

Current vector control for PMSM

Adaptive fuzzy control for speed loop of PMSM Implemented by hardware (Application IP)
Rectifier AC110V
Implemented by software using Nios embedded Modify
− −
processor IP Park 1 Clarke 1 + −
i d* = 0 vd vα vrfx PWM1
U
PI α,β
α,β a, b, c v
ω*r
PWM2
e +ωr− rfy ω PWM3 3-Phase V PMSM
+
Inference
uf Ku i*q vq
d, q
d,q vβ vrfz
SVPWM
r PWM4
inverter W
α, β
α,β PWM5

_ ∆e FI Mechanism
DFI
1 − Z −1 +
PI PWM6

1 − Z −1 −
id iα ia iu
ωr α,β
α,β a, b, c
ib Current
A/D LPF Encoder
Knowledge
Base iq i β α,
α,ββ ic detector iw
d,q
d, q A/D LPF

Park Clarke +
A , A ,B
− +

Adjust ωr θe P θp Encoder A Comparator

−
B ,Z ,Z
+ −

Sin&Cos B
2 detector &
Mechanism Transform.
Z Circuit

em
_
Reference ωm + ωr θp
1 − Z −1
Model

Current loop: 16kHz,

Speed control:less than 1kHz
PWM circuit: 4~8MHz
Fig. 2 The internal architecture of FPGA-based servo control IC for PMSM drive
A. Mathematical model of PMSM park, park-1 in Fig.2, can be described in synchronous rotating
reference frame. The relations of coordination transformation
The mathematical model of a typical PMSM can be
in the rotating motor among stationary a-b-c frame, stationary
formulated in synchronous rotating reference frame, as
α-β frame and synchronously rotating d-q frame are shown in
follows [1]
Fig. 3, where fs represents a space vector refer to current,
di d R Lq 1 (1) voltage or flux. The formulations in Fig.3 are as follows:
= − s id + ω e iq + vd
dt Ld Ld Ld ‰ Clarke: stationary a-b-c frame to stationary α-β frame.
di q Ld R λf 1 (2) 2 −1 − 1  f 
(7)
= −ω e id − s iq − ω e + vq  fα   3 3 3  f 
a

dt Lq Lq Lq Lq f = 1 
−1   b
 β  0  f 
where vd, vq are the d and q axis voltages; id, iq, are the d and q  3 3   c 
axis currents, Rs is the phase winding resistance; Ld, Lq are the ‰ Clarke −1 : stationary α-β frame to stationary a-b-c frame.
d and q axis inductance; ω e is the electrical angular speed;
 fa   1 0 
λ f is the permanent magnet flux linkage. The developed  f  =  −1 3 
 fα  (8)
2 
electromagnetic torque is given by [1]  b  2
− 3  β
f 
 f c   2 
−1
2 
3P (3)
Te = ( λd iq + λq id )
4 ‰ Park : stationary α-β frame to rotating d-q frame.
The current control of a PMSM drive is based on a vector  f d   cosθ e sin θ e   f α  (9)
control approach, such that, if we control id to 0 in Fig.2, the f =  
 q  − sin θ e cosθ e   f β 
PMSM will be decoupled. So control a PMSM will become
easy as to control a DC motor. Therefore, (3) can be ‰ Park −1 : rotating d-q frame to stationary α-β frame.
simplified to
 fα  cos θ e − sin θ e   f d  (10)
3P (4) f  =   
Te = λ f iq ∆ K t iq  β   sin θ e cos θ e   f q 
4
with q β
3P b
Kt = λf (5)
4 f
fS
ωe
β
Considering the mechanical load, the dynamic equation of d
f qs
PMSM can be written as follows: f ds
d (6) θ α
J m ω r + B m ω r = Te − TL e
fα a
dt
where Te , K i , J m , Bm and TL are the motor toque, the torque stator
a − b − c stationary axes
rotor
constant, the inertial value, the damping ratio and the load α − β stationary axes
d − q synchronou sly rotating axes
toque, respectively. c
The coordination transformation about clark, clark-1, Fig. 3 Transformation between stationary axes and rotating axes

1545
B. Adaptive fuzzy controller in speed control loop derived, at initially, assume TL to be zero in (6), and taking
Laplace transformation of (4) to (6)
The solid rectangular area in FPGA of Fig. 2 presents the
structure of an adaptive fuzzy controller for PMSM drive. It ω r ( s)  K i  Bm / J m (18)
= 
consists of a fuzzy controller, a reference model and an i q* ( s )  B m  s + B m / J m
adjusting mechanism. In Fig.2, the tracking error e and the Next, the bilinear transformation is used to derive the
error change ∆e are defined by following difference equation of PMSM drive system.
e( n) = ω r* ( n) − ω r ( n) (11) ω r (k )  K i  (1 − e − BmT / J m ) z −1 (19)
= 
∆e(n) = e(n) − e(n − 1) (12) i q* (k )  Bm  1 − e − BmT / J m z −1

and uf represents the output of the fuzzy controller. The design where z −1 is a back-shift operator and T is the sampling
procedure of the fuzzy controller is as follows: period. Additionally, in Fig.2, the current command, iq* is
(1) Take Ke*e, Kde*∆e and uf as the input and output variable
formulated by the output of fuzzy controller, u f .
of fuzzy controller, and define their linguist values as
{ A1 , A2 , E} based on the symmetrical triangular iq* (k) = iq* (k −1) + ku u f (k) (20)
membership function:
From (19) and (20),
xi ≤ xim − wim / 2
 0
 xi − xi + wi / 2
m m wm (13) ω r ( k + 1) = Aω r ( k ) + Bi q* ( k − 1) + BK u u f ( k ) (21)
xim − i < xi < xim
 m 2
 w /2
ξ m ( xi , xim , wim ) =  m i m when m wim with A = exp(−BmT / J m ) , B = Ki (1− A) / Bm . The chain rule is
xi + wi / 2 − xi x < xi < xi +
m
 i
2
 wim / 2 used to rewrite, the partial differential equation for J (k + 1) in
 wm
0 xi ≥ xim + i
2 (17) can be rewritten as
where xi is the input value; ξ m (•) is the output value; xim , ∂J ( k + 1) ∂ω (k + 1) ∂u f (k ) (22)
= −αe m (k + 1) r
w im are mean and width of the triangular function. ∂c j (k ) ∂u f (k ) ∂c j (k )
(2) Select the initial fuzzy control rules by referring to the From (15) and (21), we can get
dynamic response characteristics [4], such as, (23)
∂u f ( k ) µj
IF e is A1m and ∆e is Am2 THEN u f is Em , m=1,2,..,M (14) =
(3) Construct the fuzzy system, u f ( x | θ ) , by using the
∂c j ( k ) ∑ µm
m

singleton fuzzifier, product-inference rule, and central and

average defuzzifier method. Therefore, (14) is replaced ∂ωr (k + 1) (24)
= BKu
with the following expression: ∂u f (k )
M M
Therefore, (23) and (24) are substituted into (21) and (17), and
∑ cm[∏i =1 ξ m ( xi , xim , wim )] ∑ cm µm
2
(15) then the parameters c j of fuzzy controller described by (15)
u f ( x |θ ) = m =1
M
∆ m =1
M
∑ [∏ ∑ µm
2
ξ ( x , x m , wim )]
i =1 m i i
can be adjusted using the following expression.
m =1 m =1
µj µj (25)
where c1 , c 2 ,.., c M are adjustable parameters. ∆ c j ( k ) = α BK u e m ( k ) ≈ α Sgn ( B ) K u e m ( k )
∑ µm
m m
∑ µm
The gradient descent method is used to derive the fuzzy
control law in Fig. 2. The primary purpose of adjusting the Because the motor parameter B is not easily to determined, so
parameters of the fuzzy controller is to minimize the square the sgn(B) is used in (25). It is unity because B is positive. The
error (instantaneous cost function) between the rotor speed sgn(.) represents the sign operator.
and the output of the reference model. The instantaneous cost C. The proposed FPGA-based servo control IC for PMSM
function is defined by drive
1 1 (16)
J (k + 1) = e (k + 1) 2 = [ω (k + 1) − ω (k + 1)]2
m m r The internal architecture of the proposed SoPC-based servo
2 2
control IC for PMSM drive is shown in Fig.4. The SoPC
and the parameters of cj are adjusted according to technology is developed by Altera Corporation and consists of
∂J ( k + 1) ∂J (k + 1) (17) a FPGA and a Nios embedded processor. The FPGA in this
∆c j (k + 1) ∝ − = −α paper used Altera - Cyclone EP1C20, which has 20,060 LEs,
∂c j (k ) ∂c j (k )
maximum 301 user I/O pins, total 294,912 RAM bits, and a
where α represents learning rate. The formulations for the Nios embedded processor which has a 16-bit or 32-bit
adjustment of the parameters c j of the fuzzy controller are configurable CPU core, 1 to 20Kbytes available on chip and
maximum 4G bytes off-chip memory. A custom software
development kit (SDK) consists of a compiled library of

1546
software routines for the SoPC design, a Make-file for used as the rotor’s position sensor. The inverter has 6 sets of
rebuilding the library, and C header files containing structures IGBT type power transistors. The collector-emitter voltage of
for each peripheral. In Fig.4, the proposed FPGA-based the IGBT is rating 600V, the gate-emitter voltage is rating
control IC has two IPs, a Nios embedded processor IP and an ±20V, and the collector current in DC is rating 25A and in
application IP. The Nios processor is used to perform the short time (1ms) is 50A. The photo-IC, Toshiba TLP250, is
function of an adaptive fuzzy control in speed loop of PMSM used for gate driving circuit of IGBT. Input signals of the
drive and its flow chart of interrupt service routine (ISR) for inverter are PWM signals from FPGA device. For the
intelligent adaptive fuzzy control are plotted in Fig. 5. The implement, the PWM switching frequency of inverter,
controller program is coded in C language. The application IP dead-band and the control sampling frequency of position
for current vector control of PMSM in Fig.4 is implemented loop are designed to 16kHz, 1µs, and 1kHz, respectively. In
by hardware using PLD due to the need of high-speed but the proposed FPGA-based servo control IC, the current
simple computation and it includes frequency divider, circuits controller is implemented by using PLD hardware and the
of two PI controllers, coordinate transformation of Clarke, adaptive fuzzy speed controller is realized by using software
Park, inverse Park, inverse Clarke and circuits of SVPWM, under in the Nios embedded processor.
QEP and ADC conversion control. Figure 6 shows the digital To verify the correctness of SVPWM circuit in Fig. 4, an
circuit of PI controller, which includes 3 adders, 2 multipliers, experimental block diagram is constructed in Fig. 9(a), where
2 D-type flip-flops and 3 max value limiters. Figures 7 to 8 are the input signal is a constant voltage with 0 to 360 degree
the circuits of Clark-1 and Park-1 transformation in (8) and (10), phase variations. The transformation of Park-1, modified
respectively. The design of PWM circuit in Fig. 4 refers to [6] Clarke-1 and SVPWM computation are used simultaneously to
but not to show here. PWM circuit is designed to be 16 kHz generate PWM1~PWM6 output. These are serially connected
frequency and 1µs dead-band. The overall circuits included a to a RC circuit with 10Ω resistor and 47µf capacitor,
Nios embedded processor IP (25.7%) and an application IP respectively. The load torque of brake is set to 2N*m. The
(28.2%) in Fig. 4, use 53.9% utility of Cyclone EP1C20. waveforms of PWM1, PWM3 and PWM5 are measured and
shown in Fig. 9(b). To validate the effectiveness of the current
vector control in Fig. 1, the input current
III. EXPERIMENTS AND RESULTS
command, ( i* ,i* ) = ( 0 A,6 A ) is set, and the currents of, id , iq
d q

The overall experimental system is depicted in Fig. 1, and and corresponding to current at a-b-c axes are measured and
it includes a FPGA (Cyclone EP1C20), a voltage source IGBT shown in Fig. 10. The results have shown that the measured
inverter and a PMSM. The power of the PMSM is 2000W, the current can tracks current command well. The experimental
rating speed is 2000rpm, and the torque magnitude of the results validate the success of current vector control, and it
brake is adjustable in the range of 0.2 to 5N*m. An will make the PMSM decouple.
incremental optical encoder (2,500 ppr) attached to PMSM is
Altera FPGA (Cyclone EP1C20)

CLK-ctrl ADIN[11]
CLK Frequency ADIN[10]
CLK CLK-sys

divider CLK-sp Application IP ADIN[9]

ADIN[8]
ADIN[7]
ADIN[6]
ADIN[5]
A[22] ADIN[4]
Nios Embedded Processor IP ADIN[3]
I-U[11..0] ADIN[2]
ADIN[1]
ADIN[0]
A[0] CPU UART I-W[11..0] BDIN[11]
D[31] BDIN[10]
BDIN[9]
Avalon Bus
Avalon Bus

On-chip PIO IQ[11..0] ADC BDIN[8]

BDIN[7]
ROM BDIN[6]
D[0]
QEP[15..0] Control BDIN[5]
sram_be[3] BDIN[4]
sram_be[2] Timer CLK-sys BDIN[3]
On-chip BDIN[2]
sram_be[1] CLK-ctrl
BDIN[1]
sram_be[0] RAM BDIN[0]
I-U[11..0]
sram_oe SPI CHA
sram_we I-W[11..0] CHB
sram_cs RCA
RCB
STSA
STSB
CLK-sys
KI-p[11..0] Servo on

CLK-ctrl Dead-band[11..0] PWM-1

ID[11..0]=‘0’
CLK-sys PI PWM-2
SVPWM
PWM-f[11..0]
ID[11..0] PWM-3
IDD[11..0] Controller VA[11..0] PWM-4
KP-p[11..0] VB[11..0] PWM-5
Servo on VC[11..0] PWM-6
KI-q[11..0]
CLK-ctrl
IQ[11..0] CLK-sys
IQ[11..0] PI
IQQ[11..0]
KP-q[11..0]
Controller VDD[11..0]
VQQ[11..0] CLK-sys
QEP[15..0]
rotor-position[15..0]
Servo on CLK-sys Modified VA[11..0]

INV PARK VAA[11..0] VB[11..0]

CLK-sys
VBB[11..0]
INV CLARK VC[11..0]

CLK-sp
CLK-sys
SIN/COS
QEP[15..0]
Encoder-A
EN-A
EN-B
QEP EN-Z Estimation
Encoder-B
Encoder-Z
EN-Z of Flux
Flux-angle[11..0]
CLK-sys angle IQQ[11..0]
CLK-sys

CLK-sp
IDD[11..0] PARK IAA[11..0]
CLARK I-W[11..0]
IBB[11..0]

CLK-sys I-U[11..0]

Fig. 4 The block diagram of internal circuit of a FPGA-based servo control IC

1547
 Have confirmed the effectiveness of the current vector IV. CONCLUSIONS
control, the dynamic performance of PMSM drive of the
adaptive fuzzy controller applied in speed control loop of Fig. An application of SoPC technique using a FPGA and a
1 is tested. The transfer function of the reference model is Nios embedded processor to the servo control IC of PMSM
chosen by a second order system with the natural frequency of drive is successfully developed in this paper. This
20 rad/s and the damping ratio of 1. To choose an adequate FPGA-based servo control IC allows a fully digital function
learning rate α in (17), a square wave speed command with and high performance control for the PMSM drives, therefore
amplitude of 300~600 rpm and external load torque of 1.0 the current vector control scheme, SVPWM generation,
N*m are applied. The tracking results between the output of coordinate transformation, QEP detection and adaptive fuzzy
reference model and the actual rotor speed under different control strategy are all realized and integrated in a single
learning rate of 0.1, 0.2, and 0.3 is shown in Fig. 11. In Fig. FPGA. The experiments are successfully validated, and the
11(a), α is chosen as 0.1 and the tracking is slow. However, experimental results show a good performance.
when α is 0.3, as in Fig. 11(c), the rotor speed can fast track vα va
the output of the reference model after one square wave
1/2 2‘S COMPLEMENT
command. For further testing of the robustness of the adaptive
characteristics of the proposed controller, the final tuned 1/2

parameters ci in Fig. 11 are use directly as the initial 1/4

parameters in the following two cases. The first case is that the 1/16 adder vb
amplitude of speed command is 300~600 rpm and the external 1/32
load torque is 0.2 N*m. The second case is that the amplitude vβ adder
1/64
of speed command is 1000~1300 rpm and the external load 1/256
adder 2‘S COMPLEMENT vc
torque is 1.0 N*m. The experimental results of the speed 1/512
tracking and current response in those two cases are shown in
1/2048
Figs. 12 to 13. In Fig. 12, at initial, the rotor speed tracks the
output of reference model with oscillation, meanwhile the Fig. 7 The designed circuit of Clarke −1 formulation
parameters of fuzzy controller tuning toward reducing the
error between the output of the reference model and the rotor cosθe 12 bits
speed at each control sampling interval. After one square wave multiplier
command tracking, the parameters of fuzzy controller are vd 12 bits vα
adder
tuned to the adequate value, and the actual rotor speed can get − sin θ e 12 bits
a good following with the output of the reference model. vq multiplier
Figures 12 and 13 also show that the control current in case II
is larger than case I. Therefore, from Figs. 11 to 13, it sin θ e 12 bits
demonstrates that the proposed servo control IC using SoPC
technology for PMSM drive is effectiveness and robustness. vd multiplier
12 bits
cos θ e 12 bits
adder vβ
Start of Start of ISR
multiplier
main program ( each 1kHz )
vq
Read QEP from current Calculation of q-axis
Initial interrupt
vector control IP and current command and Fig. 8 The designed circuit of Park −1 formulation
calculate velocity of send to current vector
PMSM control IP
Initial timer FPGA-based Control IC PWM2
PWM1
Modified PWM3
Calculation of Calculation of error − −1
Park 1 Clark
Initial all speed error and between position of PWM1
peripherals v =0 vα vref1 a
the change of error motor and output of d α, β a, b, c PWM2 10 Ω
reference model PWM3 47 µ F
2ψ→3ψ vref2
v SVPWM PWM4 10 Ω
Setting of Calculation of output vβ
q d, q α, β vref3 PWM5 b
speed command of fuzzy controller Parameters adjusting PWM6
of fuzzy controller 47 µ F
10 Ω
Calculation of θe c
loop SIN
SIN Angle
speed loop &
End generator 47 µ F
COS
COS
Fig. 5 Flow chart of main and ISR program in DSP chip (a)
PWM1 PWM3 PWM1 PWM2 PWM1 PWM2
PI Controller

CK
CK
D-Type Ui(k-1) 16KHz
FF +/-
Ki Adder
saturate Ui(k)
CK Multi
D-Type
CK
CMD FF
e(k) e(k-1)
+/-
FBK Sub
saturate CK
U(k)
Up(k) +/- PWM1-PWM3 waveform 1μs dead-band
Kp Multi Adder
saturate
(b)

Fig. 6 Digital circuit of PI controller Fig. 9 (a) PWM experimental block (b) PWM output waveforms

1548
 6 iu iv iw Output of
1400 reference model

Speed (rpm)
4
1200
Current (A)

2
1000
0 Rotor speed
800
-2 0 1 2 3 4 5 6 7 8 9 10
(a) Time (s)
-4
5
-6 4

Current (A)
0 10 20 30 40 50 60 70 80 90 100 3
(a) Time (ms)
10 2

iq 1
Current (A)

0
0 1 2 3 4 5 6 7 8 9 10
5 (b) Time (s)
Current command: i*
q= 6 A
Fig. 13 (a) Speed tracking under 1000~1300 rpm command and
id i*
d=0A
1.0N*m load torque (b) Response of the measured current.
0

100 200 300 400 500 600 700 800 900 1000 V. ACKNOWLEDGMENT
(b) Time (ms)

Fig. 10 (a) Three phase waveforms (b) i , i and i d , i q response in *

d
*
q
This work was supported by National Science Council of
current control loop the R.O.C. under grant no. NSC 94-2213-E-218-032.
800
Output of
Learning rate :α=0.1 VI. REFERENCES
Speed (rpm)

reference model
600
[1] B.K. Bose, Power Electronics and Variable Frequency
400
Drives – Technology and Application, IEEE Press, 1997.
200 Rotor speed [2] B.K. Bose, “Expert System, Fuzzy Logic, and Neural
1 2 3 4 5 6 7 8 9 10 Network Applications in Power Electronics and Motion
(a) Time (s) Control,” Proc. IEEE, vol. 82, no. 8, 1994, pp. 1303-1323.
800
Output of
Learning rate :α=0.2 [3] F.J. Lin, C.H. Lin and P.K. Huang, “Recurrent fuzzy neural
Speed (rpm)

reference model
600 network controller design using sliding-mode control for
400 linear synchronous motor drive,” IEE proc.-control Theory
Application, July 2004. vol. 151, no.4, pp407-416.
200 Rotor speed
[4] C.M. Liaw and Y.S. Kung, “Fuzzy Control with Reference
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