.
Very-high Speed Control of an FPGA-based Finite-Element-Analysis Permanent
Magnet Synchronous Virtual Motor Drive System
Christian Dufour Handy Blanchette
Opal-RT Technologies, 1751 Richardson, suite 2525, Montréal, Québec, Canada
www.opal-rt.com
{christian.dufour, handy.blanchette, jean.belanger}@opal-rt.com
Abstract- Presented in this paper are the results of tests
involving high-speed closed-loop control of a virtual permanent
magnet synchronous motor (PMSM) drive implemented on a
field-programmable gate array (FPGA) card, connected to an
external controller. Three types of motor drive models are
actually implemented on the FPGA card of the RT-LAB based
real-time simulator used: a Park (d-q) model along with two
different implementations of Finite Element Analysis (FEA) based
models. The first FEA model, previously published, is an FPGA
implementation of a FEA model with an inductance calculation
routine running on an associated CPU of the real-time simulator.
The second FEA model has its inductance routine coded in the
FPGA. One of the main objectives of the paper will be to compare
the performance of the two FEA models. By virtue of the faster,
FPGA-located, inductance routine update rate of the new model,
it is expected that its precision at very high speed will be greater
than the previous model, which was shown to be limited to 400 Hz
electric frequency.
The tests will be made in closed-loop mode for current control
mode, at fixed speed, and also in speed control model. The
controller is designed using Rapid Control Prototyping (RCP)
methodology based on Simulink, and is also run on a second RT-
LAB real-time simulator. The controller and the motor drive are
interfaced through I/O channels only, not unlike a real motor
drive: Analog I/O signals for motor current and resolver signals,
and Digital I/O for the IGBT gate pulse signals and quadrature
encoder signals. In contrast to a previously published work, the
resolver signal decoding will be made with an Xilink System
Generator (XSG) implementation of a Synchro/Resolver-To-
Digital converter.
The FPGA-based motor model is designed with the Xilinx
System Generator (XSG) blockset with no HDL hand coding.
Both motor models compute motor currents using a phase-
domain algorithm solver that can take into account the
instantaneous variation of inductance and non-sinusoidal induced
voltage. The FEA-type model uses inductance and Back-EMF
profiles computed with JMAG-RT. The d-q model uses sinusoidal
induced Back-EMF voltage and phase inductance values
computed from Ld and Lq using the well-known Park
transformation. A 3-phase IGBT inverter implemented in the
FPGA chip drives the PMSM machine.
The motor controller is a PWM vector controller designed in
Simulink and running at a sample time of 50 microseconds. It is
implemented on an RT-LAB simulator using standard Opal-RT
FPGA-based I/O cards for Analog Input capture and PWM
generation.
The paper will present results from the closed-loop control of
the PMSM drive in both current control and speed control modes
and discuss the advantages of using such a virtual test bench for
motor drives.
k,((( 
Jean Bélanger
I. INTRODUCTION
A critical aspect in the deployment of motor drives lies in
the early detection of defects in the design process. The later in
the process that a problem is found, the greater the cost to fix
it. Rapid prototyping of motor controllers is one methodology
that enables the control engineer to quickly deploy control
algorithms and find eventual problems. This is typically
performed using a small real-time simulator called a Rapid
Control Prototyping system (RCP) connected in closed-loop
with a physical prototype of the drive to be controlled. Modern
RCPs take advantage of a graphical programming language
(such as Simulink) with automatic code generation support.
Later in the design process, when this code has been converted
and fitted into a production controller (using mass-production
low-cost devices), the same engineer can verify it against the
same physical motor drive, often a prototype or a pre-
production unit.
This methodology implies that the real motor drive is
available at the RCP stage of the design process. Furthermore,
this set-up requires a 2nd drive (such as a DC motor drive) to be
connected to the motor drive under test to emulate the
mechanical load. This is a complex setup, however it has been
proven to be very effective in detecting problems earlier in the
design process.
In cases where a physical drive is not available, or where
only costly prototypes are available, an HIL-simulated motor
drive can be used during the RCP development stage. In such
cases, the dynamometer, real IGBT converter, and motor are
replaced by a real-time virtual motor drive model. This
approach has a number of advantages. For example, the
simulated motor drive can be tested with borderline conditions
that would otherwise damage a real motor. In addition, setup of
the controlled-speed test bench is simplified since the virtual
shaft speed is set by a single model signal, as opposed to a
using real bench, where a 2nd drive would need to be used to
control the shaft speed.
Other advantages of using a virtual motor drive system
include the ability to easily study the impact of motor drive
parameter variations on the controller itself.
Of course, the fidelity of the motor drive model is an
important aspect of this process. Classical models, like the
PMSM single-frame d-q model [1], are often adequate but lack

some aspects of real motor drives, such as saturation and
inductance variations caused by stator slots. FEA-based models
handle this limitation well [2][7]. The simulator latency also
adds a delay in the control loop, which may change its
response.
Finally, most motor drives include high-bandwidth on-board
protection that cannot be simulated on conventional RCP
systems. For example, a real motor drive may include DC-link
current motoring for short-circuit detection. If this condition is
detected, IGBT pulses are disabled. Despite a sampling time
below 10 microseconds, a high-performance classical CPU-
based HIL simulation [4] is still too slow to simulate these
effects. FPGA-based HIL simulation offers a solution to this
challenge.
A previous paper[2] describes a FEA-based PMSM model
implementation on an FPGA in which the inductance
calculation were computed on an associated CPU of the real-
time simulator. Tests showed that the slower update rate of the
CPU (near 50 μs) had the effect of limiting the accuracy of the
model for stator frequencies above 400 Hz. In this paper, we
will evaluate a similar FEA-based PMSM model in which the
inductance values will be stored on the FPGA firmware. We
expect this will enable the model to achieve greater accuracy at
higher speeds than the previous model.
II. RT-LAB EDRIVESIM SIMULATOR MODELS
The various eDRIVEsim models used to create the HIL
simulation of the PMSM motor drive are described here. Each
of the motor models use the same phase-domain solver
described in A). This solver has the natural advantage of
enabling the simulation of open-phase conditions by directly
acting on the stator resistance vector.
A. General PMSM machine equations
The general PMSM equation in the phase domain is:
dψ abc
[ L]−1 ∫ (Vabc − − RI abc )dt = I abc (1)
dt
where
[L] is the inductance matrix,
Iabc is the stator current inside the windings,
ψabc is the magnet flux linked into the stator windings,
R is the stator resistance and
Vabc is the voltage across the stator windings.
Both the d-q and JMAG-type models’ currents are solved
using equation (1). The only difference is that [L] and ψ are
sinusoidal in the d-q model, while [L] and ψ are FEA-
computed in the JMAG case. Also, most operations are made
using 18-bit numbers with the notable exception of the flux
integrators, which have 48 bits because of the 20-nanosecond
integration step used.
k,(((
.
B. Inverter model
The inverter model includes controlled switches with
forward voltage drop, conduction losses and anti-parallel
diodes. These diodes turn on only during dead time with a
logic that depends on the load current (ex: if the current flows
into the load, then the lower diode turns on). Since the signal
resolution of the IGBT gate is 10 nanoseconds on the FPGA
itself, no interpolation mechanism is used, unlike in the CPU
implementation of HIL motor drive[4]. The model does not
account for switching losses[6].
The proposed inverter model can also work in fully rectifying
mode with no IGBT pulses. Depending on the motor speed and
the DC-link voltage, the drive can work in a mode where the
motor Back-EMF voltage makes the inverter act as a diode
rectifier. This is an improvement over the inverter model
proposed in [1].
C. D-Q-Based PMSM model [1]
Fig. 1 describes the two-axis (d-q) PMSM and IGBT inverter
models that were designed in XSG and executed on the RT-
LAB real-time simulator. With this model, all calculations are
made in the FPGA itself: the model uses FPGA-stored inverse
inductance and nominal-speed Back-EMF tables. During the
calculations, the real Back-EMF is found by multiplication of
the nominal value by the actual speed. The gate signals of the
IGBT inverter can come from external I/O, from a controller
model running on one CPU of the simulator, or from an
internal PWM source. This internal PWM generation feature is
useful for model self-verification and to validate the model
against reference models without the use of an externally
connected controller.
L(θ)=T(θ)*Ldq0*T-1(θ)
IGBT inverter
Inductance
θrotor
PMSM
N
FPGA
(Op5130)
S
vbackEMF θrotor
iabc BackEMF=f(θ,ω)
6 (sinusoidal)
Digital Input (10 ns) Analog Output Digital Out
I/Os
(IGBT gates) (Iabc, resolver) (quad encoder)
Controller under test
Fig. 1 D-Q-based PMSM drive implemented on the FPGA
D. Finite-Element-Analysis-Based PMSM model [2]
In the FEA-based PMSM model, the electric equations of the
PMSM and its IGBT inverter are still computed on the FPGA
computational engine using the same phase-domain solver as
the d-q model. Notably, this includes the 1-D nominal speed
Back-EMF table, derived from JMAG-RT, developed by JRI

 .

Solutions Ltd. The 2-D inductance inverse matrixes L-1(θ,Iabc)
as well as the electrical torque are computed on the CPU and
transmitted on the FPGA where interpolation methods are used
to up-sample the inductance at 10 nanosecond rate. This
scheme is depicted in Fig. 3
E. FEA-PMSM model with inductance storage on the FPGA
In this FEA-based PMSM model, the inductance data is
stored on the FPGA and all electric equations of the PMSM
and its IGBT inverter are still computed on the FPGA
computational engine using the same phase-domain solver as
the other FPGA model. The 2-D inductance inverse matrixes
L-1(θ,Iabc) are first extracted using an off-line simulation
routine and then stored in FPGA RAM. The FEA electrical
torque is still computed on the CPU. This scheme is depicted in
Fig. 4

CPU Torque (JMAG-RT)

(Intel/AMD)

L-1=f(θ,Ιabc)
(JMAG pre-computed)
FPGA
(Op5130) iabc L-1 (θ,iabc) θrotor

Fig. 2 Lq inductance profile computed by the JMAG model

IGBT inverter Inductance
(with sqrt(3/2) factor) PMSM
The Lq profile of the motor used in this paper is shown in N
Fig. 2. It is also normal to compute the electrical torque on the
CPU because the device speed is usually computed from many S
different torque sources like, for example, mechanical torque vbackEMF θrotor
produced by the engine in hybrid propulsion cars[3]. iabc BackEMF=f(θ,ω)
6 (JMAG pre-computed)
As for the d-q model, the storage of the nominal speed Back-
Digital Input (10 ns) Analog Output Digital Out
EMF profile of the JMAG model on the FPGA enables the I/Os (Iabc, resolver) (quad encoder)
(IGBT gates)
computation of real Back-EMF voltages by multiplication of
the fixed table stored value by the actual speed.
Controller under test

Fig. 4 FEA-based PMSM drive on an FPGA with firmware-based

Inductance and torque inductance storage
CPU data pre-computed from PMSM
(Intel/AMD) JMAG software
FEA inductances storage on FPGA firmware
iabc L-1 (θ,iabc) θrotor The FEA inductances are extracted, in offline simulations, as
a function of rotor angle, current magnitude and current
IGBT inverter Inductance sectors. The resulting inductance value for all rotor angles and
PMSM current magnitude must be stored in some way. The method
N used in this case is to properly sample the inductance for angle
FPGA and current magnitude and then to use 2-D interpolation to
S obtain a correct estimate at all times.
(Op5130)
vbackEMF θrotor
This method must be repeated for the 6 current sectors of the
iabc
6 BackEMF=f(θ,ω)
(JMAG pre-computed)
machines. The resulting data is stored in a contiguous way in
the RAMblocks of the FPGA card as described in Fig. 5. In the
Digital Input (10 ns) Analog Output Digital Out
I/Os (IGBT gates) (Iabc, resolver) (quad encoder)
figure, the major index is used to step around the stored current
amplitudes, the middle index is used to step around the 6
current sectors and the minor index refers to the rotor angle.
Controller under test

Fig. 3 Real-time simulation of FEA-based PMSM drive on an FPGA

k,((( 

Fig. 5 Inductance data storage in the FPGA memory.
FEA torque calculation
The FEA torque is to be used on the CPU mainly because it
is used in the mechanical equations in closed-loop control tests.
The easiest way to incorporate the FEA torque in the drive
model is to directly use the JMAG-RT torque module in the
CPU of the simulator, like in [2].
Alternative FEA torque method
However, in some real-time systems, the C++ Linux library
of the JMAG-RT modules cannot be linked with other real-
time libraries because of linking process protections of the
Linux system (only libraries compiled with the same OS
revision are compatible with one another). In that case, an
alternative method had to be found.
The look-up table method for torque is difficult to achieve
because the torque is continuously dependent on rotor position,
current magnitude and current angle, whereas the inductance is
constant on the 6 current sectors. The method currently under
study is to first extract the null-current torque (cogging torque)
and then to compute the remaining torque using energy
principle.
The power balance of the machine can be described by the
following equation.
2 d ( I abc LI abc )
Vabc I abc − RI abc = 0 .5 + Pem
dt
which means that the net input power to the machine,
excluding losses, is transformed in electromagnetic field
energy and mechanical power. The LIabc quantity being directly
available in the simulation model, the motor rotation speed is
then computed from the net change in total rotational energy:
2⎛
+ ∫ (Tcog − Tmec ) ω dt ⎞⎟
2 I abc LI abc
ω= ⎜ ∫ (Vabc I abc − RI abc )dt −
J⎝ 2 ⎠
where Tmec is the mechanical torque externally applied to the
machine, Tcog is the offline extracted cogging torque and J is
the inertia of the machine. Note that this equation can be
k,(((
.
simulated without an algebraic loop because of the integral
term on ω in the right side of the equation. The method is
interesting because it does not require additional look-up tables
and avoids speed division to compute the torque.
III. EXPERIMENTAL RESULTS
In this section, HIL results obtained with the original JMAG
model, having its inductance value computed in the CPU of the
real-time simulator, are presented. Note that the paper do not
show results for the new JMAG-FPGA model with inductance
stored on the FPGA firmware.
The experiments were conducted using the FPGA-based
PMSM drive (JMAG) in closed-loop with a motor controller
running on a 2nd independent simulator as a Rapidly
Prototyped Controller. Using the set-up and models previously
described, current and speed control tests were performed.
A. Real-Time Simulator Hardware set-up
As previously mentioned, the controller and the motor drive
are implemented on two independent RT-LAB simulators. The
controller is running on an MX Station-type RT-LAB
simulator (middle box) with I/O connections on the back. The
MX Station is a 2.3 GHz Core2 Duo-based PC. The MX
Station I/Os are based on 2 different Opal-RT FPGA cards: the
OP5110 (PCI) implements the digital inputs and outputs while
the OP5130 implements the analog inputs for the SRTD
device. The Digital I/Os are isolated in both systems and the
opto-coupler circuits are powered by the 12V power supply of
the RCP.
The motor drive is running on the eDRIVEsim RT-LAB
simulator (bottom box). The eDRIVEsim simulator is a 2.3
GHz dual quad-core (Intel Core2) PC with an onboard FPGA
card (Virtex 5 FPGA). The FPGA card holds the PMSM
machine and inverters models. One core of the PC computes
the machine electrical torque with the mechanical equations as
well as the inductance values (in the case of the first JMAG
model).
B. Machine Drive Parameters
The machine under test is a 4 pole (2 pairs) interior magnet
machine (IPM) with the parameters described in Table 1. The
800V DC-link voltage is rather high and allows the motor to
operate at 12000 RPM without flux weakening.
TABLE 1. MOTOR PARAMETERS
Quantity Value
Stator resistance 3.3 Ω
Park equivalent direct inductance 0.0109 H
Park equivalent quadrature inductance 0.0310 H
Magnet flux 0.1584 Wb
Number of pairs of poles 2
Total number of slots 24

 .

Inertia 1.854*10-4 kg.m2

Friction 5.396*10-5 N.m.s
Applied mechanical torque 1 N.m.
DC-link voltage 800 V
FPGA sample time 10 ns
CPU sample time 65 μs
Quadrature encoder 1024 pulses/channel

C. Controller Parameters
The motor controller is a classical vector controller using the
Park d-q transform to control motor currents and torque. An
outer speed control loop completes the controller. This enables
the torque control of the motor by acting on the Iq current
component. For this experiment, no flux weakening is applied
and the Id current command is therefore set to zero. PWM Fig. 6 Synchro/Resolver-to-Digital response to a 50 Hz to 10 Hz step
generation can be made in either sinus or space-vector at the resolver input signal.
modulation with user variable carrier frequency and dead time.
In our tests, the PWM frequency is 5 kHz and dead time is 5 E. Current control mode tests
microseconds. All models are made with Simulink. One great advantage of a virtual motor drive test bench over
The controller parameters used in these tests are enumerated a real one is ease of the hardware set-up. This becomes even
in Table 2. The reference Id value is set to 0 in all tests as no clearer when one tries to test motor current control loops. In
flux weakening is made. The Vdq limits are really the entry to this case, with a real bench, one really needs two motor drives:
the dq-abc transform that produce the modulation indexes for the PMSM drive itself and a second motor drive to control the
all phases and are therefore limited to ±1. All PI controllers shaft speed. With a virtual bench, one simply has to set the
have anti-windup mechanisms. shaft speed state-variable to the desired speed.
TABLE 2. CONTROLLER PARAMETERS

Quantity Value
Current controller Ki Kp/Ki gains 22.7 0.0017
Vdq limits (from current controller) ±1 pu
Speed controller Ki Kp/Ki gains 3.5 0.026
(except section E)
Iq limits (from speed controller) ±9.5 A
PWM frequency 5 kHz
Dead time 5 μs
Sample time 50 μs

D. Synchro/Resolver-to-Digital (SRD) model

The RCP controller is equipped with an XSG model of a
Synchro/Resolver-To-Digital model. The model works on the
principle of synchronous demodulation of the SRD input
signals by an internal VCO, which is closed-loop controlled to
null its phase with the incoming signals (See [9] for more
details). Up to 64 such SRD devices can be implemented on
the OP5130 Opal-RT FPGA card, but only one was used in
these tests. Fig. 6 shows the SRD unit step response. The SRD
VCO closed-loop PID gain can be adjusted to optimize this
response.
Fig. 7 Current command step (JMAG model, 1500 RPM)
Fig. 7 shows the JMAG model response of the current
control at 1500 RPM, corresponding to a 50 Hz stator
frequency and a commanded Iq current step from –2 to 6 A. In
the figures, the Iq component is recognizable as the one
following the current amplitude.
The two figures actually display two acquisition frames
acquired at the Windows console station of the RCP. This
means that there is a time discontinuity in the figures. In Fig. 7
for example, the two frames begins at 0.14 and 0.25 sec. Since

k,((( 
 .
the command is applied asynchronously from the motor drive,
this enables verification of the drive response relative to the
motor rotor angle at the time of the command application. The
results of Fig. 7 show that the controller response does not
depend on the motor angle.
F. Speed control mode tests
Following the adjustment of current control parameters,
closed-loop speed control tests are performed. Fig. 8 shows
the speed response of the motor drive for the JMAG model, for
Fig. 8 Speed step (JMAG model, 1000->3000 RPM)
a speed command step of 1000 to 3000 RPM. It is interesting
to see that because of the asynchronous speed step application,
the phase current responses differ from one frame to another
mainly because of the initial conditions of the motor at each
application of the speed command steps.
CONCLUSION AND WORK TO BE MADE FOR THE FINAL PAPER
This paper has presented experimental results of a motor
controller connected to a virtual motor drive. The controller
was designed in Simulink and implemented on an RT-LAB
RCP system. The motor drive was also designed in Simulink,
and implemented on an FPGA processor using Xilinx System
Generator blockset. A FEA-computed PMSM model was used
for the tests.
Future work will include comparison results of this model
with a similar one that has the inductance data stored in the
FPGA firmware and characterization of the Synchro/Resolver-
to-Digital model that was coded in XSG.
k,((( 
REFERENCES
[1] C. Dufour, S. Abourida, J. Bélanger,V. Lapointe, “Real-Time Simulation
of Permanent Magnet Motor Drive on FPGA Chip for High-Bandwidth
Controller Tests and Validation”, 32nd Annual Conference of the IEEE
Industrial Electronics Society(IECON-06), Paris, France, November 7-
10, 2006.
[2] C. Dufour, J. Bélanger, S. Abourida, V. Lapointe, “FPGA-Based Real-
Time Simulation of Finite-Element Analysis Permanent Magnet
Synchronous Machine Drives”, Proceedings of the 2007 Power
Electronics Specialists Conference (PESC-07), Orlando, Florida, June
17-21, 2007
[3] C. Dufour, T. Ishikawa, S. Abourida, J. Bélanger, “Modern Hardware-In-
the-Loop Simulation Technology for Fuel Cell Hybrid Electric
Vehicles”, Proceeding of the 2007 IEEE Vehicle Power and Propulsion
Conference (VPPC-07), Arlington, Texas, Sept. 9-12, 2007
[4] M. Harakawa, H. Yamasaki, T. Nagano, S. Abourida, C. Dufour, J.
Bélanger, “Real-Time Simulation of a Complete PMSM Drive at 10 us
Time Step”, Proceedings of the 2005 International Power Electronics
Conference (IPEC 2005) – April 4-8, 2005, Niigata, Japan.
[5] S. Abourida, C. Dufour, J. Bélanger, T. Yamada, T. Arasawa,
“Hardware-In-the-Loop Simulation of Finite-Element Based Motor
Drives with RT-LAB and JMAG”, EVS-22 Symposium, Yokohama,
Japan, October 23-28, 2006.
[6] G.G. Parma, V. Dinavahi, “Real-Time Digital Hardware Simulation of
Power Electronics and Drives”,Transactions on Power Delivery, Vol 22,
No. 2, April 2007
[7] O. A. Mohammed, Fellow IEEE, S. Liu, Member IEEE, and Z. Liu,”A
Phase Variable PM Machine Model for Integrated Motor Drive
Systems”, 35th Annual IEEE Power Electronics Specialists Conference,
Aachen, Germany, 2004, pp. 4825-4831
[8] C. Dufour, S. Abourida, J. Bélanger, V. Lapointe, “InfiniBand-Based
Real-Time Simulation of HVDC, STATCOM, and SVC Devices with
Commercial-Off-The-Shelf PCs and FPGAs”, 32nd Annual Conference
of the IEEE Industrial Electronics Society (IECON-06), Paris, France,
November 7-10, 2006
[9] Analog Devices AD2S90 rev.D specs sheet “AD2S90: Low Cost,
Complete 12-Bit Resolver-to-Digital converter”