Silicon MicroFabrication Technology

Introduction to Semiconductor
microfabrication technology
Felix Lu
Introduction to MEMS
ECE@ Duke University
Overview
I. Raw materials to wafers
I. Si refinement from sand
II. Si boule growth techniques
III. Wafer preparation
II. Doping
I. Diffusion
II. Oxidation
III. Ion implantation
III. Material growth and Deposition

I. Material deposition
II. Epitaxy
III. Wafer bonding
IV. Device processing

I. Etching
II. Contacts
III. Device fabrication overview
Fall 2005 Microfabrication Technology Introduction to MEMS

Silicon refinement from sand
• Quartzite sand (silica) is reacted with carbon from coal
(coke) to make metallurgical grade silicon (MGS).
SiO2 + 2C ! Si + 2CO
MGS is ~98% pure trichlorosilane
MGS HCl (g) SiHCl3+ H2 (g)
Impurity Fractional
chlorides distillation
increases
purity.

Silicon refinement from MGS
Electronic grade Si (EGS) ~ 99.999999% pure
SiHCl3+ H2 (g) 2Si + 3HCl
Very pure Polycrystalline Si
Re-melt and recrystallize

into single crystal.
Czochralski
2 examples:
Float Zone

Single crystal pulling
Czochralski (CZ) technique
Single
crystal Si
boule Seed
crystal
http://en.wikipedia.org/wiki/Czochralski_process
http://lachlan.bluehaze.com.au/usa2003/octob
er2003/16oct2003a/
Molten Si
http://www.isomet.com/FinalWebSite/FOHomePage/FOXtalGrowth.htm
Interaction with the crucible introduces up to ~1018 cm-3 oxygen!

Horizontal Bridgeman
window
Low Temperature furnace (~630 °C) High temperature furnace (~1200 °C)
Stationary tube
GaAs seed
Excess arsenic GaAs melt
Quartz ampule
After T.R. AuCoin and R.O. Savage, in Gallium Arsenide Technology, D.K. Ferry, ed., Sams (1985)

http://www.tf.uni-kiel.de/matwis/amat/elmat_en/kap_6/advanced/t6_1_3.html
Float Zone
Very pure Si crystals
Melting and purification done at the

same time.
Impurities prefer to stay in the liquid so

solid is very pure, also making hard to
dope uniformly along the length!
T.F. Ciszek, M.R. Page, T.H. Wang, and J.A. Casey; Float-
Zone and Czochralski Crystal Growth and Diagnostic
Solar Cell Evaluation of a New Solar-Grade Feedstock
Source, 29th IEEE PV Specialists Conference New Orleans,
Louisiana May 20-24, 2002

Si wafer process
http://smtbook.com/instructor_guide.pdf

Wafer Orientation
for 6” wafers or smaller*
(111) p-type (111) n-type See also, SEMI M1-0302,
http://wps2a.semi.org/wps/portal/_pagr/116/_pa.116/121?docName=P0
01204
(111A) (111B)
45°
_ _ 90° 90°
(01 1) (01 1)
Si GaAs
(100) p-type (100) n-type
Sometimes flat is here
90° 135°
_ _ 1230
(01 1) (01 1) From www.usna.edu/EE/ee452/LectureNotes/05-Processing_Technology/18_Silicon.ppt
After W.R. Runyan and T.J. Shaffner, Semiconductor Measurements & Instrumentation, 2nd Ed., McGraw Hill, 1998.

Single crystal properties of Si
Kurt Petersen, Silicon as a mechanical material, Proc. of the IEEE,

1982, vol. 70, no. 5, pp. 420.
Wafer surface characterization
Dektak
http://www.veeco.com/appnotes/AN526-StylusCap_04065.rf.pdf
Nomarski differential interference contrast

Optical
zygo® profilometer
http://www.zygo.com/?/products/nv6000/
http://www.microscopyu.com/articles/dic/reflecteddic.html

Temperature and Pressure
measurement
Fabrication involves processes which have to take place in a narrow range of
temperatures and pressures.
Temperature measurement: Peltier/Seebeck junction thermocouple
http://www.electronics-cooling.com/Resources/EC_Articles/JAN97/jan97_01.htm
http://www.picotech.com/applications/thermocouple.html
http://www.omega.com/temperature/Z/pdf/z021-032.pdf
Pressure measurement:
thermocouple Ionization gauge
http://www.lesker.com/newweb/Pressure_Measurement/Thermocouple
http://www.duniway.com/images/pdf/pg/hot-filament-ion-gauge-tube.pdf

A sampling of cleaning methods
• Chemical
– Wet
• Pirahna : H2SO4:H2O2 (4:1) [90 °C for 15 minutes]
• RCA (or SC)
– RCA1 (SC1) removes organics and particulates
» NH4OH:H2O2:H2O (1:1:5) 70 °C for 10
– RCA2 (SC2) removes metallic contaminants minutes
» HCl:H2O2:H2O (1:1:5)
– Dry
• oxygen plasma: reactive oxygen ions convert hydrocarbons to CO2 and H2O.
• UV/Ozone: reactive O3 oxidize hydrocarbons.
• Mechanical
– Ultrasonic Small scale mechanical agitation…
http://www.techsonic.fr/megatheory.htm
– megasonic

Doping of Semiconductors
Metals : ~10-7 to ~10-8 Ohm·m
Resistivity of Semiconductors : ~10-6 to ~107 Ohm·m (including semi-insulating III-V’s)
Insulators : ~1010 to ~1015 Ohm·m
http://www.geokem.com/images/pix/periodic.gif
http://www.astro.virginia.edu/class/oconnell/astr511/lec11-f03.html

Doping considerations
Doping vs. alloying
~ 1ppm or less ~.1 – 99%

“Si:P” “SixGe1-x”
Selective etching of layers and dopant selective etching

Mostly for III-V’s
Intrisic Si from n+ Si: KOH(40%) at 60 °C and ethylenediamine-pyrocatechol
(EDP)(After G.E. Rittenhouse et al., J. Vac. Sci. Tech., B 10(6), 2860-3 (1992))

http://www.occdsb.on.ca/~pop/Music.htm
Why “Si is king”

• SiO2: acts as etching mask, passivation for surface
states, high quality gate insulator.
• III-V oxides : typically unstable.
• GeO : soluble in water!

•Masato Aizawa, Anne M. Cooper, Marek Malac, and Jillian M.
Buriak, Silver Nano-Inukshuks on Germanium, Nano Letters,
VOLUME 5, NUMBER 5, MAY 2005, American Chemical Society
Pictures from http://sinclair.ece.uci.edu

Thermal oxidation of Si
H2O
O2 H2O
O2
amorphous Diffusion through amorphous
SiO2 oxide SiO2 Diffusion through
oxide
Reaction with Si
Reaction with Si
Si Si
Wet oxidation : faster but dirtier, both from extra oxygen in water.
Dry oxidation: slower but cleaner.
SiO2 is less dense (and amorphous) than Si and so a film of SiO2 of
thickness x0 consumes about 0.45 x0 of Si. [after Mayer and Lau, 1990]

Wafer bowing
e.g.
oxide
Top layer is under substrate

compressive stress from the
substrate.
Top layer is under tensile

stress from the substrate. substrate

The oxide surface
H H H
HF dipped Si surfaces tend to
be hydrophobic : Si Si Si
H termination minimizes water
interaction with Si. Drop of water
on Si surface.
Freshly oxidized Si surfaces
tend to be hydrophilic :
Silanol groups (Si-OH) stick to water.
Joanne Deval, et al., Reconfigurable
hydrophobic/hydrophilic surfaces in
microelectromechanical systems (MEMS), J.
Micromech. Microeng. 14 (2004) 91–95
After Tong and Gösele,

Semiconductor Wafer Bonding,
John-Wiley & Sons, 1999
“mature” oxides can also be hydrophobic

depending on surface chemistry of oxide.

example
Forming S and D for p-MOSFET.
Predeposition (“predep”)
Anneal BN wafer (which has B2O5) with Si wafer in N2.
oxide mask
Si wafer with
BN
wafer B2O5 http://www.bn.saint-gobain.com
Drive-in
Anneal doped Si wafer with steam and oxygen.
The oxidation over the S

and D, minimize out
diffusion of B.
http://plasticdog.cheme.columbia.edu/undergraduate_research/projects/patricia_wang_project.htm

Ion implantation
http://bmrc.berkeley.edu/courseware/ICMfg92/images/gif/doping.gif
Implantation of H ions of 50 kV into Si
After
http://humanresources.web.cern.ch/Humanresources/exter
nal/training/tech/special/ELEC2002/ELEC-
2002_11Apr02_3_PDF.pdf
After F. Lu, Ph.D. thesis, (2004)

Material deposition and growth
“deposition” – amorphous or polycrystalline layer
– Contact metal
– Insulating layer
“growth” - single crystal layer

- epitaxy : MBE, CVD

Evaporation
Pump down to get a good vacuum.
A good vacuum increases the mean free

path of the evaporant.
Maximize distance between source and target

for more uniform coverage.
Thermal evaporation: materials which have a very high

melting point (comparable to the boat) or materials
http://www.haanappel.net/ryan/resume/experience-
which form a eutectic with the boat cannot be thermally
dielectric.php evaporated.
Adhesion layers for Au to Si:

Electron beam evaporation Ti, Cr
http://www.mpi-halle.mpg.de/~mbe/si.html

Sputtering
What is sputtering? (a.k.a. physical vapor
deposition)
Why sputtering? What’s wrong with

evaporation?
- some materials are difficult to evaporate.
http://www.ece.utep.edu/research/webedl/cdte/Fabrication/pictures/sputter.htm - low melting point substrates.
- evaporating thick layers quickly may burn photoresist or
heat up target.
- Adhesion of sputtered films is often better.
- Deposition is different from evaporation- which is from a
point source.
Layer stoichiometry = target stoichiometry
(source) - changes in composition easy to do.

Electroplating
Typically to make thick layers of metal
(>~1µm) on top of evaporated and
patterned metals.
http://www.ganoksin.com/borisat/nenam/electroplating-and-electropolishing.htm
V
Unplating biases remove asperities unplating
time
plating

Chemical Vapor Deposition
a.k.a. CVD, VPE,
and for III-V’s : MOCVD, OMCVD,
MOVPE, OMVPE
http://www.esi-group.com/SimulationSoftware/CFD_ACE/MOVPE.html
http://python.rice.edu/~arb/Courses/Images/360_02_handout9.jpg
PECVD – able to deposit films at much lower temperatures by using a plasma

to “crack” the gas into its components.

From two Greek words: “epi” = “on” and “taxis” = “arranged”, after John
Orton, “The Story of Semiconductors”, Oxford University Press 2004, p. 6
Molecular Beam Epitaxy

Highly abrupt
interfaces
Effusion cells
http://www.veeco.com/images/mbe_structure.jpg
RHEED
www.sandia.gov/media/NewsRel/NR2000/laser.htm
cryopanels
Appropriate other meanings of MBE:

Mostly Broken Equipment
Massive Beer Expenditures
Maniac Bloodsucking Engineers
Mega-Buck Evaporator
Many Boring Evenings (how do you think this list came about?)
Minimal Babe Encounters (see previous item)
Mainly B.S. and Exaggeration
Flourescent screen Medieval Brain Extractor
http://www.ece.utexas.edu/projects/ece/mrc/groups/street_mbe/mbechapter.html http://www.ece.utexas.edu/projects/ece/mrc/groups/street_mbe/mbeacronym.html

Lattice mismatched epitaxy
a1
a2
Misfit dislocation
a2
Separate layers thickness of epilayer thickness of epilayer

< critical thickness > critical thickness
• J.W. Matthews, A.E. Blakeslee, “Defects in epitaxial multilayers,” Journal of Crystal Growth, 27, 118 (1974).
• R. People, J.C. Bean, “Calculation of critical layer thickness versus lattice mismatch for GexSi1-x/Si strained-layer
heterostructures,” Applied Physics Lett., 47, 322 (1985).

Heterogeneous integration
Deposition techniques:
Allow amorphous or polycrystalline material layers on single
crystal substrates.
Crystal growth techniques (MBE, CVD)

Mix and match epilayers of different materials
Thermal expansion coefficient

If not matched well enough:
Lattice mismatch high dislocation density at the interface
Single crystal layer

…but what if you want layers that do not match well with each other for a particular
device?
…or, if you want a single crystal layer on top of an amorphous layer?
Si on Insulator (SOI)
Semiconductor on Insulator
Device layer ~ 1µm High energy particle
Buried oxide (BOX)
e-
h+
substrate
e-
e- h+
- h+
e -e h+
h+
e-
h+
Radiation hardened
High speed circuits
Coupling through the substrate

increases RC delay

Wafer bonding & wafer fusion
Definition:
The permanent attachment of two ultrasmooth surfaces without any kind of glue.
“Wafer bonding” " bonding of two wafers with an oxide inbetween them.
“Wafer fusion” " bonding of two wafers without an oxide between them.
• Can be used to combine materials

with different lattice constants and
thermal expansion coefficients.
• Can be used to get monocrystalline
layers on top of amorphous layers.
• Applications : SOI, heterogeneous
integration, Si-InGaAs APD, MEMs
P. Mages, Ph.D. Thesis, UC San Diego (2003)

Bonding chemistry
After Tong and Gösele, Semiconductor Wafer Bonding,

John-Wiley & Sons, 1999
After P. Mages, Ph.D. thesis, (2003)

Hydrophobic bonding
IR Transmission Si-Si wafer bonded interface
One example of this is bonding a
III-V piece to Si.
III-V piece is ~10× more expensive that Si so we
don’t want to use the whole wafer.
Artifacts from poor cleaving
Pictures from P. Mages, Ph.D. thesis, 2003

High thermal stress bonding
After P. Mages Ph.D. Thesis, UC San Diego, 2003

Low thermal stress bonding
After P. Mages Ph.D. Thesis, UC San Diego, 2003

Hydrophilic bonding
Cleaning procedure:
For Si with thin oxide: Acoustic microscope images of plasma

activated bonded Si-OX 4” wafers.
Spin cleaning with solvents
Dilute HF (1%) dip
Modified RCA-1 (1:1:38)
For Si with thick oxide:

Spin cleaning with solvents Si with native oxide : Si with native oxide :
Si with native oxide Si with thick oxide
Modified RCA-1 (1:1:38) (5000 Å)

Bond strength
! 1.1 µm
IR camera
E = Young’s modulus
tw = wafer thickness
tb = blade thickness
Important to measure L accurately
L = crack length since small changes in L = large
" = bond energy changes in "!

Plasma activation of the surface
plasma activated Si/OX wafers
(30 s, 150 W)
RCA-1(45 s), DI water (2 min)
3500
3000
Bond strength (mJ/m )

2
2500
2000
1500
1000
oxygen plasma + RCA1
500 Oxygen plasma + DI water
Argon plasma + DI Water
Nitrogen plasma + DI Water
0
0 100 200 300 400 500 600
Anneal Temperature (°C), 2 hr. in air
From T. Suni, Master’s thesis, Helsinki Institute of Tech., (2001)
How does plasma activation increase OX

et
e the bond energy so much? Water from
pl t Si oxide
m a is
co l th th - general concensus : surface surface
o de ns OX
N o ai becomes more porous Possible
m xpl Water diffuses
e t… - water may be trapped in the pores Si to gaps during model
ye annealing
OX Wet oxidation of Si
- wet oxidation of Si wafer to close
up gaps ! increase contact area. Si Gaps close

Layer transfer techniques
Oxygen ion implantation
~1022 cm-2
Bond wafers
Try to Anneal out defects
Grind and
polish
SIMOX BESOI
Silicon implanted with oxygen Bond and Etch back SOI
See also http://www.mse.berkeley.edu/~pzhang/MSE225/TICS5GRP7.pdf

Unibond® (a.k.a. Smart-Cut®, Ion-cut®)
• Initial motivation
Re-use of expensive wafers.
Thin film of Si on Corning 1737F glass.
http://www.mpi-halle.mpg.de/~waf_bond/cut.html
After F. Lu, Ph.D. thesis (2004)

Device processing
• Start with layered structure
• Etching patterns for current and/or
optical isolation/confinement
Semiconductor optical
waveguide
http://www.compoundsemiconductor.net/articles/magazine/9/
SOI MOSFET 6/2/1/csbipolar3_6-03
BJT

Isotropic/anisotropic etching
http://www2.nano.physik.uni-muenchen.de/~schoeff/RR_Web_01/images/Anlagen/RIE/IsotropicEtchPix.jpg
www.memsnet.org/mems/processes/etch.html

Wet etching
Pros Cons
• Cheap and easy to set up • Can be sensitive to temperature
(affects repeatability)
• Can be highly selective
• Etch rates may be a function of
• Often does not damage stirring and stirring rate
substrate • Can have particulates in solution (may
not be very clean)
• Large amounts of chemical waste
Ambient
temp.

Common etchants in Si processing
Si etchants:
KOH (potassium hydroxide)
TMAH – Tetramethylammonium hydroxide
EDP – Ethyylene diamine pyrocatechol
HF:HNO3:Acetic acid
SiO2 etchant:
~1200 Å/min at RT
HF (hydrofluoric acid)
BOE – buffered oxide etch (buffered HF)
Al etchant:
Produces bubbles during
H3PO4: H2O: HNO3 (16:4:1) etching – shake wafer to
remove bubbles
Etch masks:
photoresist, thermal SiO2, deposited SiOx, SiNx
Source: Kurt E. Petersen, Silicon as a mechanical material, Proceedings of the IEEE, vol. 70, no.5, May 1982, pp. 420

Dry etching
Chemical and/or physical process using a plasma for etching substrates.
Etch rates: much slower than wet etching
Parallel plate configuration Barrel configuration
Plasma has no
directionality
vertical sidewalls
www.ulvac.com/foundry/index.asp

Etching mechanics
Etching of single crystal :
– Diffusion
• Movement of etchant to sample surface
– Reaction
• If sample is not directly soluble in etching solution, change it.
– Typically done by oxidizing the surface (e.g. H2O2, HNO3), oxidizing the
sample is another name for removing electrons, or injecting holes.
• Use another component of the etching solution to remove the new

product.
Often, CH3COOH is used because it wets
the surface better, better wetting results in
Example: etch Si using HNO3:HF:H2O smoother surfaces.
The nitric acid changes Si to SiO2, and HF etches the SiO2: SiO2 + 6HF ! SiF6 + 2H2O
Electrolytic etching, light induced etching

Extra electrons speed up reaction SiF6 is soluble in water

Contacts to devices
• Purpose: fulfill electrical specs and resist contact
degradation. I I
V V
Ohmic Rectifying
junction junction
metal
isolation Metal-semiconductor junction typically rectifying

Highly doped layer Metal-highly doped semiconductor typically ohmic
substrate
Backside contact Backside contact acts ohmic due to large size.
Acts like a lot of resistors in parallel.

Fabrication of a MOSFET
1. Clean n-Si wafers:
RCA1, HF dip, RCA2, BOE dip.
2. Wet oxidation of Si (~2000 Å)

Heat wafers up to 1000 °C, bubble oxygen
through 95 °C DI water into furnace.
3. Pattern S and D through holes in wet oxide.
Photolithography, cover backside with resist. BOE through the wet
oxide. Result: only front side holes go through to Si.
4. Boron doping of S and D.
Activate Boron Nitride (BN) wafers,
Predep: anneal Si with oxidized BN in N2 at 1050 °C
Drive-in: anneal Si without BN wafer in wet oxygen.
5. Strip off wet oxide.

BOE dip until wafer is hydrophobic.
6. Grow dry (gate) oxide (~1000 Å)

Heat wafers up to 1000 °C in ultra pure oxygen.

MOSFET fab (cont’d)
7. Pattern gate oxide to open up windows for metal to
contact S and D.
BOE dip (since S and D windows are so small, you can’t use the hydophobic test to
see if oxide has etched through), how do you know when to stop?
8. Evaporate Al over front side of wafer. (~1000 Å)
9. Etch Al, leaving only contacts to S and D.

H3PO4:HNO3:Acetic acid – shake the wafer to remove bubbles.
10. Evaporate Al on the backside of the wafer.
11. Anneal Al for good contacts.

450 °C in nitrogen for 10 min.
when to stop etching the windows.
Answer: since you’re going to put Al on the backside for a body contact, you can use the backside as a gauge to see


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Introduction to Semiconductor

III. Material growth and Deposition

IV. Device processing

Fall 2005 Microfabrication Technology Introduction to MEMS

MGS HCl (g) SiHCl3+ H2 (g)

Fall 2005 Microfabrication Technology Introduction to MEMS

SiHCl3+ H2 (g) 2Si + 3HCl

Very pure Polycrystalline Si

Re-melt and recrystallize

Fall 2005 Microfabrication Technology Introduction to MEMS

Interaction with the crucible introduces up to ~1018 cm-3 oxygen!

Fall 2005 Microfabrication Technology Introduction to MEMS

Melting and purification done at the

Impurities prefer to stay in the liquid so

Fall 2005 Microfabrication Technology Introduction to MEMS

Fall 2005 Microfabrication Technology Introduction to MEMS

(01 1) (01 1) From www.usna.edu/EE/ee452/LectureNotes/05-Processing_Technology/18_Silicon.ppt

Fall 2005 Microfabrication Technology Introduction to MEMS

Kurt Petersen, Silicon as a mechanical material, Proc. of the IEEE,

Nomarski differential interference contrast

Fall 2005 Microfabrication Technology Introduction to MEMS

Fall 2005 Microfabrication Technology Introduction to MEMS

Fall 2005 Microfabrication Technology Introduction to MEMS

Fall 2005 Microfabrication Technology Introduction to MEMS

~ 1ppm or less ~.1 – 99%

Selective etching of layers and dopant selective etching

Fall 2005 Microfabrication Technology Introduction to MEMS

Why “Si is king”

• III-V oxides : typically unstable.

• GeO : soluble in water!

Pictures from http://sinclair.ece.uci.edu

Fall 2005 Microfabrication Technology Introduction to MEMS

Fall 2005 Microfabrication Technology Introduction to MEMS

Top layer is under substrate

Top layer is under tensile

Fall 2005 Microfabrication Technology Introduction to MEMS

After Tong and Gösele,

“mature” oxides can also be hydrophobic

Fall 2005 Microfabrication Technology Introduction to MEMS

The oxidation over the S

Fall 2005 Microfabrication Technology Introduction to MEMS

Implantation of H ions of 50 kV into Si

After F. Lu, Ph.D. thesis, (2004)

Fall 2005 Microfabrication Technology Introduction to MEMS

“growth” - single crystal layer

Fall 2005 Microfabrication Technology Introduction to MEMS

A good vacuum increases the mean free

Maximize distance between source and target

Thermal evaporation: materials which have a very high

Adhesion layers for Au to Si:

Fall 2005 Microfabrication Technology Introduction to MEMS

Why sputtering? What’s wrong with

Fall 2005 Microfabrication Technology Introduction to MEMS

Fall 2005 Microfabrication Technology Introduction to MEMS

PECVD – able to deposit films at much lower temperatures by using a plasma

Fall 2005 Microfabrication Technology Introduction to MEMS

Molecular Beam Epitaxy

Appropriate other meanings of MBE:

Fall 2005 Microfabrication Technology Introduction to MEMS

Separate layers thickness of epilayer thickness of epilayer

Fall 2005 Microfabrication Technology Introduction to MEMS

Crystal growth techniques (MBE, CVD)

Thermal expansion coefficient

Single crystal layer