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In general, an instruction set can be classified according to the type of

operand used by each instruction. The operand is located either in a register
or in a memory location. The typical classes of instructions are
1. Memory-to-memory instructions. Both operands are in memory.
2. Memory-to-register instructions. One of the operands is in memory,
the other in a register.
3. Register-reference instructions. The operation is performed on
the contents of one or more registers.
4. Memory-reference instructions. The operation is performed on
the contents of memory locations.
5. Control instructions. These are branching, halt, pause, and the
like.
6. Input/output instructions.
7. Macroinstructions. These are equivalent to a set of (more than
one) instructions of the types 1 through 6.

Note that the arithmetic and logic instructions are a subset of the memory
and register reference instructions

machines with large instruction

sets and powerful instructions were designed, ushering in the era of
complex instruction set computers (CISC).

the silicon area on an

IC chip saved by using a small instruction set can be used to implement
more powerful hardware operators and greater word lengths. Such designs
produce reduced instruction set computers (RISC).

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The length of an instruction is a function of the number of addresses in the
Instruction

Based on the number of addresses (operands), the following instruction

organizations can be envisioned:
1. Three-address
2. Two-address
3. One-address
4. Zero-address



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ADD A, B, C M[C] M[A] þ M[B]
SUB A, B, C M[C] M[A] _ M[B]
366 Chapter 7
MPY A, B, C M[C] M[A] _ M[B]
DIV A, B, C M[C] M[A] = M[B]
A, B, and C are memory locations.
Each of the above instructions requires three memory accesses during
execution. In practice, the majority of operations are based on two operands
with the result occupying the position of one of the operands. Thus, the
instruction length and address computation time can be reduced by using a
two-address format, although three memory accesses are still needed during
the execution.
 

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ADD A, B M[A] M[A] þ M[B]
SUB A, B M[A] M[A] _ M[B]
MPY A, B M[A] M[A] _ M[B]
DIV A, B M[A] M[A] = M[B]
The first operand is lost after the operation.
If one of the operands can be retained in a register, the execution
speeds of the above instructions can be increased. Further, if the operand
register is implied by the opcode, a second operand field is not required in
the instruction, thus reducing the instruction length:
 

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ADD A ACC ACC þ M[A]
SUB A ACC ACC _ M[A]
MPY A ACC ACC _ M[A]
DIV A ACC ACC = M[A]
LOAD A ACC M[A]
STORE A M[A] ACC
µµACC¶¶ is an accumulator or any other register implied by the instruction.
(An accumulator is required here.) If both the operands can be held in
registers, the execution time is decreased. Further, if the opcode implies the
two registers, instructions can be of zero-address type:


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ADD SL SL þ TL, POP
SUB SL SL _ TL, POP
Processor and System Structures 367
MPY SL SL _ TL, POP
DIV SL SL = TL, POP
LOAD A PUSH, TL M[A]
STORE A M[A] TL, POP
SL and TL are the second- and top-level respectively of a last-in, firstout
stack. In a zero-address machine, all the arithmetic operations are performed
on the top two levels of a stack, so no explicit addresses are needed
as part of the instruction. However, some memory reference (one-address)
instructions such as LOAD and STORE (or MOVE) to move the data
between the stack and the memory are required.

Assuming n bits for an address representation and m bits for the

opcode, the instruction lengths in the above four organizations are:
Three-address: m þ 3n bits
Two-address: m þ 2n bits
One-address: m þ n bits
Zero-address: m bits.

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Assignment of opcode for instructions in an instruction set can significantly
influence the efficiency of the decoding process at the execute phase of the
instruction cycle. (ASC opcodes have been arbitrarily assigned.) Two
opcode assignments are generally followed:
1. Reserved opcode method
2. Class code method.
In the reserved opcode method, each instruction would have its own opcode.
This method is suitable for instruction sets with fewer instructions. In the
Processor and System Structures 369
Figure 7.1 Programs to compute F = A _ B + C _ D
class code method, the opcode consists of two parts: a class code part and an
operation part. The class code identifies the type or class of instruction and
the remaining bits in the opcode (operation part) identify a particular operation
in that class. This method is suitable for larger instruction sets and for
instruction sets with variable instruction lengths. Class codes provide a
convenient means of distinguishing between various classes of instructions
in the instruction set. The two opcode assignment modes are illustrated here:
Reserved opcode instruction.
Opcode addresses

Class code instruction.

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The majority of machines use a fixed-field format within the instruction
while varying the length of the instruction to accommodate a varying number
of addresses. Some machines vary even the field format within an
instruction. In such cases, a specific field of the instruction defines the
instruction format.