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The paper addresses the use of multi-objective evolutionary algorithm for the synthesis of hybrid
CBL/CMOS cell. The evolutionary algorithm named as ‘Strength Pareto Evolutionary Algorithm
(SPEA) is used to find sizes of transistor ratio W/L of hybrid CBL/CMOS cell. The transistor
sizes so obtained are called ‘Pareto Optimal Solutions’, which are intended to optimize some
circuit specifications. These circuit specifications are formulated as objective functions to be
minimized. The paper has focused on following objective functions (also called ‘cost factor’).
ELDO simulator has been used to carry out simulation and measurement of each coded
solution. The non-dominated W/L solutions of each transistor are plotted w.r.t given
objective function and thus optimum value of W/L ratio is extracted for each transistor. In
conclusion, dependency of various objective functions (Idd(peak), Vdd(peak), Idd(rms), Pow(avg.),
propagation delays, PDP) is shown and final solutions are discussed in tabular form.
Methodology: The work has been divided into three sub-sections to achieve the final
solutions.
The deviation (relative error) between calculation and simulated sizes is observed which
comes out to be 21% of PMOS tree and 0.4% of the PMOS CBL transistor.
Next, SPEA (a stochastic optimization procedure) optimizes the vector of objective functions
as described above. The solutions obtained from SPEA are called non-dominated Pareto-
optimal solution. Following values of various parameters is used for SPEA in all the runs of
algorithm.
The solutions are stored in external archive E where clustering algorithm is applied. Main
goals of clustering algorithm are:-
1. To avoid that the external archive size does not exceed the user defined maximum size.
- It converges faster than any other multi-objective optimization method used for example-
as Energy minimization evolutionary algorithm (EMEA).
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