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03/97 Page 1
Applications Note
Understanding Static RAM Operation
Data Inputs
performance. Unlike DRAMs, SRAM cells do not DI0
need to be refreshed. This means they are avail- DI1 Memory Array
able for reading and writing data 100% of the ...
time.
The basic architecture of a static RAM includes one An SRAM memory cell is a bi-stable flip-flop made
or more rectangular arrays of memory cells with up of four to six transistors. The flip-flop may be in
support circuitry to decode addresses, and imple- either of two states that can be interpreted by the
ment the required read and write operations. Addi- support circuitry to be a 1 or a 0.
tional support circuitry used to implement special Many of the SRAMs on the market use a four tran-
features, such as burst operation, may also be sistor cell with a polysilicon load. Suitable for
present on the chip. medium to high performance, this design has a rela-
Figure 2 shows a basic block diagram of a synchro- tively high leakage current, and consequently high
nous SRAM. As you read, you may wish to refer to standby current. Four transistor designs may also be
the diagram to help you visualize how the SRAM more susceptible to various types of radiation-
works. induced soft errors. IBM's SRAMs all use a six tran-
sistor memory cell (also called a six-device cell) that
is highly stable, relatively impervious to soft errors,
and has low leakage and standby currents.
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Applications Note
Understanding Static RAM Operation
Recognizing the superiority of the six-device cell toward the six-device cell via intermediate designs.
while trying to avoid using the extra chip real estate, IBM's commitment to the six-device cell stems from
many industry SRAM producers are migrating slowly its functional superiority and reliability.
VDD VDD
P1 P2
P1 P2
N1 GND
N2
LWL N3 N4
GND
BL0 BL1
Support Circuitry CMOS while the interface circuits (including the driv-
ers) are bipolar. A few, including all of IBM Micro-
The memory chip's support circuitry allows the user electronics' high performance, synchronous SRAMs,
to read the data stored in the memory's cells, and are made entirely with CMOS circuits.
write data to the cells. This circuitry generally
includes:
Packaging
• Address logic to select rows and columns.
• Translation logic that "reads" the data in a cell IBM Microelectronics' SRAMs come in three differ-
and sends that data to the data I/O. ent packages depending on their cost and perfor-
• Write logic that takes the user data applied at mance. PC-compatible SRAMs are usually sold in
the input and stores it in a memory cell.
52-pin PLCC or 100-pin TQFP packages. These
• Output enable logic to prevent data from appear-
packages comply with the JEDEC standards for
ing at the outputs unless specifically desired.
• Internal counters and registers to keep track of pinout and footprint. Ultra-high performance
burst address sequences, pipelined data, and SRAMs, including most of the SRAMs geared to
other control functions on the chip. high-end workstations, require a higher performance
• Clock circuitry to control the timing of the read package — the 119-pin Ball Grid Array (BGA) pack-
and write operations and all of their variations. age. The BGA package has superior performance
characteristics such as shorter leads from chip to
Silicon Technology package and internal planes that result in lower
inductance and reduced package-related noise.
High performance SRAMs currently on the market
are manufactured using one of three basic pro-
cesses. A small number of offerings are made using
bipolar circuits. Most are made using a BiCMOS
technology in which most of the internal circuitry is
03/97 Page 3
Applications Note
Understanding Static RAM Operation
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Applications Note
Understanding Static RAM Operation
operation, this signal is used to prevent data from occurs and data at the data input pins is ignored.
appearing at the output until needed. Prior to a write
operation, OE is sometimes used to tri-state the In IBM SRAMs, Write Enable may be implemented
data bus to avoid data contention. OE is ignored in two different ways. Some SRAMs have a single
during a write operation. OE is an asynchronous sig- WE that controls the read or write operations, and
nal. It can be switched at any time and the SRAM several Byte Write control pins that permit the user
will respond to the signal. Use of the output enable, to mask individual bytes during a write operation.
although recommended, is optional. Some IBM SRAMs have several Write Enable pins
(WEx) that combine the write enable and byte write
K Clock The K clock is the primary clock. On single mask functions.
clock SRAMs, this clock controls when input signals
are latched at the beginning of a read or write opera- Byte Write Enable (WEx or SBWx) The Byte Write
tion, and when output signals appear at the output Enable pins permit the user to mask one or more
pins. On dual clock SRAMs, the K clock controls bytes when writing data to the memory. In some IBM
only the input signals; the output signals are con- SRAMs, the byte write mask and the write enable
trolled by the C clock. On late write SRAMs, the K functions are combined; these SRAMs have several
clock is a differential input (the input pins are K WE pins, one for each byte of data (set of 9 DQs).
and K). Some IBM SRAMs have separate Byte Write Enable
pins for each byte of data (set of 9 DQs). They must
C Clock The C clock is only used in dual clock be selected along with the write enable if data is to
SRAMs. The C clock is used to time the appearance be written. Each byte contains eight data bits and a
of data at the output pins. A K clock is used to con- parity bit. (Parity is not evaluated on the chip and
trol the input signals. On late write SRAMs, the C must be provided by the user.)
clock is a differential input (the input pins are C
and C). On SRAMs with a WEx for each set of 9 DQs (and
no WE), the appropriate WE must be low to write the
Chip Select (CS or SS) The Chip Select is used to corresponding memory locations. To write data to
block or allow input signals to the chip. When CS is the memory cells associated with all of the chip's
high, input signals applied to the chip's input pins DQs, all of the WEx pins must be low (active).
are ignored. When CS is low, input signals may be
applied to the chip's input pins, and the signals will On SRAMs with a write enable and byte write enable
be latched at the appropriate time in the clock cycle. pins, you must select WE (low) and the Byte Write
Enable pins for the bytes that are to be written. If the
Write Enable (WE or SW) Write Enable is used to Byte Write Enable is high, no data is written to the
choose between a read and a write operation. When memory locations associated with the DQs con-
WE is low, data applied at the data input pins is writ- trolled by that input.
ten into memory. When WE is high, a read operation
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Applications Note
Understanding Static RAM Operation
1 cycle
CLK 1
ADDR 2 A0 A1 A2
Setup Hold
Chip Select
CS or SS 3 7
Write Enable
(WE) Setup
4
Output Enable
(OE) 5
Data Output
(DQ)
6 DQ0 DQ1 DQ2
Note: DQ0 is the data associated with Address 0 (A0). DQ1 is the data associated with Address 1 (A1).
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Applications Note
Understanding Static RAM Operation
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Applications Note
Understanding Static RAM Operation
1 cycle
CLK
ADDR A0
Flow Thru 1
Output DQ0
(DQ)
Pipeline 2
Output DQ0
(DQ)
3
Register to Latch
Output DQ0
(DQ)
Burst Pipeline 5 5 5
Output DQ0 DQ1 DQ2
(DQ)
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Applications Note
Understanding Static RAM Operation
1 cycle
CLK 1
ADDR 2 A0 A1 A2
Chip Select
CS 3
Setup Hold
Write Enable
WE 4
Data Input
5 DI0 DI1 DI2
DI
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Applications Note
Understanding Static RAM Operation
In the third clock cycle, address A2 is selected (4). In the fifth cycle, address A4 is applied (9), and a
The data corresponding to address A1 (DQ1) read operation is selected (10). The contents of
appears at the outputs (5). Because the data must address A4 will appear at the outputs in the sixth
be tri-stated before data can be applied during the cycle (not shown).
write operation, DQ1 may not be usable since it may
not be valid for a sufficient period of time. In most
cases, the second cycle, and DQ1 will be lost. This
is called a “dead cycle.”
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Applications Note
Understanding Static RAM Operation
1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle
CLK
ADDR 1 A0 2 A1 4 A2 6 A3 9 A4
Write Enable 10
7
WE
5 Write Active
Read Read Tri-State Write Read from A3
3 5 8 Tri-State 11
STANDARD WRITE
Data I/Os DQ0 DQ1 DI3 DQ3
DI, DQ
DQ2 lost
read cycle read cycle dead cycle write cycle
Read Read Read Write
12 13 14 15
LATE WRITE
Data I/Os DQ0 DQ1 DQ2 DI3
DI, DQ
Tri-State Tri-State
read cycle read cycle dead cycle write cycle
03/97 Page 11
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