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INTRODUCTION
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INTRODUCTION
Embedded memory test design has become an essential part of the system-on-chip
(SOC) development infrastructure. According to the recent ITRS report, the memory cores will
occupy more than 90% of the chip area in less than ten years. The yield of on-chip memories
thus will dominate the chip yield. Go/no-go testing is no longer enough for embedded memories
in the SOC era. Memory diagnostics is quickly becoming a critical issue, so far as manufacturing
yield and time-to-volume of SOC products are concerned. Effective memory diagnostics and
failure analysis (FA) methodologies will help improve the yield of SOC products, especially with
Memories are one of the most universal cores. In Alpha 21264, cache RAMs
represent 2/3transistors and 1/3 area. In StrongArmSA110, the embedded RAMs occupy 90%
area In average SOC, memory cores will represent more than 90% of the chip area by 2010
[ITRS 2000]. Here we mentioned different reasons why memory testing is important
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• Embedded memories: access, diagnostics & repair,
compression, etc.
• BIST/BIRA/BISR generation
• Isolation (accessibility)
BIST is considered the best solution. Because, for Embedded memories accessibility of Pins is
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CHAPTER 2
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MEMORIES AND MEMORY FAULT ANALYSIS
SOC consists of many memory models. Like, SRAM, FLASH, ROM etc, we
consider here only SRAM type of memory core. In this section we will see what the functional
model of SRAM is and what types of Functional Faults, Fault Models and Defects exist in
Basic functional model of SRAM is shown below. Many sub functional models are
there, fault can be any where in the sub modules. Faults can be exist in address decoder logic,
cell array, write driver etc. In section 2 we will see how different faults exists and what are the
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2.2 FAULT ANALYSIS
Failure analysis (FA) and diagnosis of memory cores plays a key role in system-on-
FAULT ANALYSIS
ST0 ST1
Transition Fault (TF): The 0!1 (or 1!0) transition is impossible on a cell or a line.
Coupling Fault (CF): When a cell is written to 0!1 (or 1!0), the content of the other cell is
changed. CF is generalized to a k-coupling fault when k-1 cells are changed and is classified into
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Address Decoder Fault (ADF): No cell will be accessed with a certain address or multiple
cells are accessed simultaneously or a certain cell can be accessed with multiple addresses.
Address Decoder Open Faults (ADOF): CMOS address decoder open faults are caused
by open defects in the CMOS logic gates of the memory address decoders, and due to their
Retention Faults (RF): A cell fails to retain its logic value after some time. This fault is
sensitive faults preventing the base cell from being transited to a certain value is called
‘static’NPSF, and an NPSF is called `dynamic' when a transition on the neighborhood cells
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2.3 RAM TEST ALGORITHM
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CHAPTER 3
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BIST (Built-in Self Test)
Built-in Self Test, or BIST, is the technique of designing additional hardware and
software features into integrated circuits to allow them to perform self-testing, i.e., testing of
their own operation (functionally, parametrically, or both) using their own circuits, thereby
chip easier, faster, more efficient, and less costly. The concept of BIST is applicable to just about
any kind of circuit, so its implementation can vary as widely as the product diversity that it caters
to.
The main drivers for the widespread development of BIST techniques are the fast-rising
costs of ATE testing and the growing complexity of integrated circuits. It is now common to see
complex devices that have functionally diverse blocks built on different technologies inside
them. Such complex devices require high-end mixed-signal testers that possess special digital
and analog testing capabilities. BIST can be used to perform these special tests with additional
on-chip test circuits, eliminating the need to acquire such high-end testers.
1) Lower cost of test, since the need for external electrical testing using an ATE will be reduced,
if not eliminated;
2) Better fault coverage, since special test structures can be incorporated onto the chips;
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3) Shorter test times if the BIST can be designed to test more structures in parallel;
Built-in self-test (BIST) has been proven to be one of the most cost-effective and
The last advantage mentioned can actually allow the consumers themselves to test the chips prior
1) Additional silicon area and fab processing requirements for the BIST circuits;
3) Additional pin (and possibly bigger package size) requirements, since the BIST circuitry need
4) Possible issues with the correctness of BIST results, since the on-chip testing hardware itself
can fail
BIST techniques are classified in a number of ways, but two common classification
of BIST are the Logic BIST (LBIST) and the Memory BIST (MBIST).
LBIST, which is designed for testing random logic, typically employs a pseudo-
random pattern generator (PRPG) to generate input patterns that are applied to the device's
internal scan chain, and a multiple input signature register (MISR) for obtaining the response of
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the device to these test input patterns. An incorrect MISR output indicates a defect in the
device.
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CHAPTER 4
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MBIST (memory built in self test)
MBIST, as its name implies, is used specifically for testing memories. It typically
consists of test circuits that apply, read, and compare test patterns designed to expose defects in
the memory device. There now exists a variety of industry-standard MBIST algorithms, such as
the "March" algorithm, the checkerboard algorithm, and the varied pattern background
algorithm.
−Embedded memories: access, diagnostics & repair, heterogeneity, custom design, power &
Widely used solutions for memory testing for the following reasons:
(3) Tests can run at circuit speed to yield a more realistic test time;
(4) On-chip test pattern generation to provide higher controllability and observability.
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4.2 MEMORY CORES ON SOC
--- SRAM
--- DRAM
--- ROM
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4.3 VARIOUS MBIST ALGORITHMS
Classical test algorithms are either (1) simple, fast but have poor fault coverage,
such as Zero-one, Checkerboard; or (2) have good fault coverage but complex and slow, such as
Walking, GALPAT, Sliding Diagonal, Butterfly, MOVI, and etc.. Due to these imbalanced
Element is specified by an address order and a number of reads and writes. Examples of some
March-based tests are MATS, MATS+, Marching 1/0, March C-, March Y, March A, March B,
and etc.. Since March-based tests are all simple and possess good fault coverage, they are the
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4.4.2 DESCRIPTION
BIST Controller
BIST controllers are mainly used to control pattern generators and comparators, and to
strictly allow the controller to perform write and read operations in compliance with the Memory
BIST Protocol.
Pattern Generator
Pattern generators are mainly used to generate different patterns required for a
Memory BIST operation. These Patterns can be Marching ones and zeros, Alternations ones
Comparator
Comparators are mainly used to compare the Memory Read data and compare
against the expected values, the values generated by the pattern generator. Any failing
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CHAPTER 5
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MBISR (memory built in self repair)
memories on a single chip Due to their high density memories is more prone to faults. These
faults impact the total chip Yield. One way to solve this problem is to enhance the memory by
(memory BIST). The second testing strategy is the preferred method for embedded memories.
The present BIST concept prefers a redundancy logic that is placed in parallel to a
memory without spare rows and spare columns. There will be no additional delay for the word
registers. Furthermore, the application can be started immediately after the memory
BIST passes. The redundancy logic calculation will not increase the test time of the
memory BIST.
The MBISR concept contains an interface between MBIST logic and redundancy
wrapper for storing faulty addresses. The MBIST controller output must provide three signals to
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mbist
MUX
sram
o_read
contr
Control
oller
Redundancy logic
logic Data_out
5.2 ARCHITECTURE
5.2.1 Description
Bist controller reads data from every memory location and compares with the actual
written data.
If the read data is different from actual written data in that particular memory location
Bist controller sends all the fault address to the redundancy logic and those addresses are
write then the input address is compares against all the fault address stored.
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If input address matches with any of the fault address the data to be written will be saved
If the external operation is to be performed is read then the address in is compared against
If the address matches with any of the fault address and also if fill bit is 1 then the output
If the input address is not matched with the fault address the output data will be read from
ram.
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5.2.2 Architecture diagram
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Bist Address_In Wr in Data in Clk Rst
MBIST 23
CONTROLLER
MUX
1
Bist Address_In Wr in Data in Clk Rst
MBIST
CONTROLLER
MUX
1
Error
MUX
2
RAM
REDUNDANCY
X3
M
U
LOGIC
Dataout_Redundancy
Out_Select
MU
X
Data_out
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Mbist controller
Address
Write data
FA
Address expected data
ram
fail_address expected_data
fail
FA
address data
FA
address data
FO
address data
fail_overflow Controller
data out
Micro architecture
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CHAPTER 6
VHDL CODE
VHDL CODE
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6.1 Design units:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top_module is
port(clk:in std_logic;
rst:in std_logic;
bist:in std_logic;
wr_in:in std_logic;
end top_module;
component bist_controller
port(clk:in std_logic;
rst:in std_logic;
bist:in std_logic;
error:out std_logic;
wr:out std_logic;
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address:out integer range 0 to 15;
end component;
component mux_control
port(a:in std_logic;
b:in std_logic;
select_l:in std_logic;
c:out std_logic);
end component;
component mux
select_l:in std_logic;
end component;
component mux_integer
select_l:in std_logic;
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c:out integer range 0 to 15);
end component;
component memory
port(clk:in std_logic;
rst:in std_logic;
wr_en:in std_logic;
end component;
component redundancy_logic
port(clk:in std_logic;
rst:in std_logic;
error:in std_logic;
wr_in:in std_logic;
bist:in std_logic;
end component;
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signal error:std_logic;
signal wr_en:std_logic;
signal wr:std_logic;
begin
mbist:bist_controller
port map(clk=>clk,
rst=>rst,
bist=>bist,
error=>error,
address=>address_bist,
data1=>data_bist,
data2=>data2,
wr=>wr,
fault_address=>fault_address);
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mux_int:mux_integer
port map(a=>address_in,
b=>address_bist,
select_l=>bist,
c=>address_mem);
mux1:mux
port map(a=>data_in,
b=>data_bist,
select_l=>bist,
c=>data1);
mux2:mux_control
port map(a=>wr_in,
b=>wr,
select_l=>bist,
c=>wr_en);
memory1:memory
port map(clk=>clk,
address=>address_mem,
rst=>rst,
wr_en=>wr_en,
data1=>data1,
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data2=>data2);
redundancy_logic1:redundancy_logic
port map(clk=>clk,
rst=>rst,
error=>error,
wr_in=>wr_in,
bist=>bist,
address_in=>address_in,
fault_address=>fault_address,
data_in=>data_in,
dataout_redundancy=>dataout_redundancy);
mux3:mux
port map(a=>data2,
b=>dataout_redundancy,
select_l=>error,
c=>data_out);
end Behavioral;
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY bist_controller IS
port(clk:in std_logic;
rst:in std_logic;
bist:in std_logic;
error:out std_logic;
wr:out std_logic;
END bist_controller;
BEGIN
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process(clk)
begin
if(rst='1')then
data1<="ZZZZ";
address_reg<=0;
read_address<=0;
expected_data<="ZZZZ";
error<='0';
count3<=not count3;
wr<=count3;
address_reg<=count1;
read_address<=address_reg;
end if;
end process;
process(clk)
begin
if(count3='1') then
value<=value+1;
data1<=value;
count1<=count1+1;
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address<= count1;
if(count1=15) then
count1<=0;
end if;
if(data2=value) then
error<='0';
else
error<='1';
fault_address<=read_address;
end if;
else
address<=count1;
expected_data<=value;
end if;
end if;
end process;
END;
6.1.3 Memory
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity memory is
wr_en : in STD_LOGIC;
rst : in STD_LOGIC;
clk : in STD_LOGIC);
end memory;
signal Mem:Memory;
begin
process(clk,data1,address,wr_en)
begin
--Mem(1)(2)<='0';
--mem(3)<="0000";
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if (wr_en='1')then
Mem(address)<=data1;
elsif(wr_en='0')then
data2<=Mem(address);
end if;
end if;
end process;
end Behavioral;
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity redundancy_logic is
port(clk:in std_logic;
rst:std_logic;
error:in std_logic;
wr_in:in std_logic;
bist:in std_logic;
end redundancy_logic;
signal reg_address:reg1;
signal f:f1;
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signal index:integer range 1 to 4;
begin
process(clk)
begin
if(rst='1') then
reg_address(1)<=0;
reg_address(2)<=0;
reg_address(3)<=0;
reg_address(4)<=0;
reg_data(1)<="ZZZZ";
reg_data(2)<="ZZZZ";
reg_data(3)<="ZZZZ";
reg_data(4)<="ZZZZ";
f(1)<='0';
f(2)<='0';
f(3)<='0';
f(4)<='0';
dataout_redundancy<="ZZZZ";
if(bist='1') then
if(error='1') then
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reg_address(index)<=fault_address;
index<=index+1;
else
index<=index;
end if;
else
if(wr_in='1') then
if(address_in=reg_address(1)) then
reg_data(1)<=data_in;
f(1)<='1';
elsif(address_in=reg_address(2)) then
reg_data(2)<=data_in;
f(2)<='1';
elsif(address_in=reg_address(3)) then
reg_data(3)<=data_in;
f(3)<='1';
elsif(address_in=reg_address(4)) then
reg_data(4)<=data_in;
f(4)<='1';
end if;
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else
dataout_redundancy<=reg_data(1);
dataout_redundancy<=reg_data(2);
dataout_redundancy<=reg_data(3);
dataout_redundancy<=reg_data(4);
end if;
end if;
end if;
end if;
end process;
end Behavioral;
6.1.5 Mux_int
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_integer is
select_l:in std_logic;
end mux_integer;
begin
process(a,b,select_l)
begin
c<=a;
else
c<=b;
end if;
end process;
end mux_int;
6.1.6 Mux1
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux is
select_l:in std_logic;
end mux;
begin
process(a,b,select_l)
begin
c<=a;
else
c<=b;
end if;
end process;
end Behavioral;
6.1.7 Mux2
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_control is
port(a:in std_logic;
b:in std_logic;
select_l:in std_logic;
c:out std_logic);
end mux_control;
begin
process(a,b,select_l)
begin
c<=a;
else
c<=b;
end if;
end process;
end mux_control;
6.1.8 Mux3
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux is
select_l:in std_logic;
end mux;
begin
process(a,b,select_l)
begin
c<=a;
else
c<=b;
end if;
end process;
end Behavioral;
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_bench_vhd IS
END test_bench_vhd;
COMPONENT top_module
PORT(
clk : IN std_logic;
rst : IN std_logic;
bist : IN std_logic;
wr_in : IN std_logic;
END COMPONENT;
--Inputs
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SIGNAL data_in : std_logic_vector(3 downto 0) := (others=>'0');
BEGIN
PROCESS
BEGIN
clk<='0';
clk<='1';
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END PROCESS;
process(clk)
begin
cnt<=cnt+1;
addr1<=addr1+1;
addr2<=addr2+1;
if(cnt>35) then
if(cnt<45) then
wr_in<='1';
address_in<=addr1;
data_in<="1111";
end if;
if(cnt>45) then
wr_in<='0';
address_in<=addr2;
end if;
end if;
end if;
end process;
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end;
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CHAPTER 7
SIMULATION RESULTS
SIMULATION RESULTS
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CHAPTER 8
SYNTHESIS REPORT
SYNTHESIS REPORT
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Device utilization summary:
Number of IOs: 16
Timing Summary:
Macro Statistics
# RAMs :1
# Counters :3
3-bit up counter :1
4-bit up counter :2
# Registers : 22
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1-bit register :4
4-bit register : 18
# Comparators :9
# Tristates :6
Macro Statistics
# Registers : 77
Flip-Flops : 77
# Shift Registers :4
Design Statistics
# IOs : 16
Cell Usage
# BELS : 97
# GND :1
# INV :3
# LUT2 :9
# LUT2_L :1
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# LUT3 : 20
# LUT4 : 45
# LUT4_D :6
# LUT4_L :4
# MUXF5 :8
# FlipFlops/Latches : 81
# FDC : 12
# FDCE : 16
# FDE : 52
# FDP :1
# RAMS :4
# RAM16X1S :4
# Shift Registers :4
# SRL16E :4
# Clock Buffers :1
# BUFGP :1
# IO Buffers : 15
# IBUF : 11
# OBUF :4
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8.1 RTL SCHEMATICS
8.1.1 RTL_TOP
8.1.2 RTL_MBSIR
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8.1.3 RTL_BIST CONTROLLER
8.1.4 RTL_MEMORY
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8.1.5 RTL_MUX
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8.2 TECNOLOGY SCHEMATICS
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CONCLUSION
Memories are the most universal component today. Almost all system chips contain
some type of embedded memory, such as ROM, SRAM, DRAM, and flash. Memory testing is
very important but challenging. Memory BIST is considered the best solution due to various
engineering and economic reasons. March tests are the most popular algorithms currently
implemented in BIST hardware. Various implementation schemes for memory BISTs are
presented and their trade-offs are discussed. Integrating self repair feature improves the chip
yield.
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