VLSI PROJECT TITLES

DATA ALCOTT SYSTEMS

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VLSI TITLES CONTENT

ENERGY-EFFICIENT DESIGN METHODOLOGIES: HIGH-PERFORMANCE VLSI
ADDERS........................................................................................................1

DESIGN OF SHA-1 ALGORITHM BASED ON FPGA...........................................1

ON BUILT-IN SELF-TEST FOR MULTIPLIERS....................................................2

A FAST CARRY CHAIN ADDER FOR VIRTEX-5 FPGAS.....................................2

PARALLEL LFSR RESEEDING FOR MIXED-MODE BIST....................................2

HARDWARE IMPLEMENTATION OF THE DOUBLE-TREE SCAN ARCHITECTURE

.....................................................................................................................2

EFFICIENT ABSOLUTE DIFFERENCE CIRCUITS IN VIRTEX-5 FPGAS................3

DESIGN AND IMPLEMENTATION FOR MD5-BASED DATA INTEGRITY

CHECKING SYSTEM.......................................................................................3

ULTRA HIGH THROUGHPUT ARCHITECTURES FOR SHA-1 HASH ALGORITHM

ON FPGA.......................................................................................................3

VLSI IMPLEMENTATION OF HIGH-SPEED SHA-256.........................................3

LOW-POWER MULTIPLIER OPTIMIZED BY PARTIAL-PRODUCT SUMMATION

AND ADDER CELLS........................................................................................3

EFFICIENT IMPLEMENTATION OF CARRY-SAVE ADDERS IN FPGAS................4

S.N
O TITLE YEAR ABSTRACT
Energy-efficient design requires exploration of available algorithms, recurrence
structures, energy and wire tradeoffs, circuit design techniques, and circuit sizing and
ENERGY-EFFICIENT system constraints. In this paper, methodology for energy-efficient design applied to 64-
DESIGN bit adders implemented with static CMOS, dynamic CMOS and CMOS compound domino
1 METHODOLOGIES: HIGH-
2010 logic families, is presented. We also examined 65 nm, 45 nm, 32 nm, and 22 nm
technology nodes to explore the applicability of the results in deep submicron
PERFORMANCE VLSI technologies. By applying energy-delay tradeoffs on various levels, we developed adder
ADDERS topology yielding up to 20% performance improvement and 4.5-x energy reduction over
existing designs.
 SHA (Secure Hash Algorithm) is famous message compress standard used in computer
cryptography, it can compress a long message to become a short message abstract. The
algorithm can be used in many protocols or Secure Algorithm, especially for DSS. In this
DESIGN OF SHA-1 paper, the Improved version SHA-1 is analysised, then improved and implemented in
2 ALGORITHM BASED ON
2010 HDL (Hardware Description Language) and FPGA. Nowadays, network is not only a way
for us to get more information. It has already become a new life-style for people. For
FPGA example, network bank, net-shopping, online chat, e-government, etc. All these need a
high security network. So networks security has become a very important problem in
information age.

Multipliers are extensively used in digital signal processors (DSPs). Many current Field
Programmable Gate Arrays (FPGAs) incorporate embedded cores such as memory and
DSPs in addition to logic blocks. For example, Xilinx Virtex-2 and Spartan-3 series FPGAs
incorporate 18×18K-bit random access memories (RAMs) with 18×18-bit multipliers
3 ON BUILT-IN SELF-TEST 2010
associated with each RAM in addition to the configurable logic blocks (CLBs). Xilinx
FOR MULTIPLIERS Virtex-4 and Virtex-5 series FPGAs incorporate DSP cores. Since the multipliers are often
part of larger complex circuits like DSPs they are less controllable and less observable
and hence an effective Built-In Self-Test (BIST) approach is required.

This paper proposes a fast adder structure for Xilinx Virtex-5 FPGAs. The generic n-bit
adder is split into two n/2-bit adders. The portion, which computes the n/2 most
significant sum bits, receives the carry input signal from a purpose-designed fast carry
A FAST CARRY CHAIN generator instead of the n/2-bit adder generating the least significant sum bits. This
4 ADDER FOR VIRTEX-5
2010 allows outperforming the ripple carry adders implemented in the chosen FPGA family.
The fast carry chain propagation is reached by optimizing the use of 6-input LUTs
FPGAS together with the dedicated MUXCY resources available in the Virtex-5 FPGA chip. A 64-
bit adder designed as proposed here is 11% and 35% faster than the standard carry
chain adder and the DSP-based adder implementation, respectively.

In this paper, a novel parallel LFSR reseeding technique for mixed-mode BIST that is
suitable and applicable to a multiple scan chain design. This approach can be applied to
generate test cubes that detect Random Pattern Resistant (RPR) faults. A multiple test
vector is used to guide the LFSR in order to generate target test cube at the application
PARALLEL LFSR time. Using a system linear equation solves the encoded test seed. Experimental results
5 RESEEDING FOR MIXED-
2010
have been discussed by performing the largest ISCAS 89 benchmark circuits.
MODE BIST Advantages: 100% test coverage, reduction of test application, reduction of test data
storage, requiring few additional hardware, high fault coverage as intended by the
deterministic test, and capability to generate any deterministic test cubes without
proportional to the largest number of specified bits.
 In a scan-based test architecture, the scan power and and test data volume can be
reduced by utilizing a double-tree scan (DTS) architecture. This paper presents a novel
hardware implementation of the DTS architecture and compares the hardware overhead
with the conventional scan architecture. The implementation proposed utilizes a clock
structure, which greatly decreases the number of clocked flip-flops and thereby reduces
HARDWARE power consumption. The power and energy consumption during the test of integrated
6 IMPLEMENTATION OF 2010 circuits can become very large. Due to the high activity factor of the digital logic during
THE DOUBLE-TREE SCAN the scan operation, the power consumption of a circuit under test can be many times
larger than the same circuit under normal functionality. The larger power consumption
ARCHITECTURE
causes many problems, ranging from IR-drop and inductive power supply losses to
excessive total chip power dissipation. The power dissipation can limit the test
application speed and therefore increase test time. A number of different approaches
have been proposed to decrease the power consumption or test time

This paper presents a novel architecture optimized for realizing efficient absolute
difference circuits in Virtex-5 FPGA devices. The proposed structure efficiently uses the
6-input look-up-tables available within the chosen devices family to maximize speed
performance and to minimize the amount of occupied resources. Field Programmable
EFFICIENT ABSOLUTE Gate Arrays (FPGAs) are attractive for supporting all applications in which a good trade-
7 DIFFERENCE CIRCUITS IN
2010
off between costs, flexibility and performance plays a crucial role. In fact, FPGAs are
VIRTEX-5 FPGAS reconfigurable and achieve low time-to-market. Moreover, thanks to the use of ever
more scaled CMOS technologies, FPGAs offer integration capabilities and computational
speeds comparable with ASICs. In order to make FPGA-based designs fast,
reconfigurable devices are typically provided with high-speed dedicated logic and
routing resources.

With the increase of the amount of data and users in information system, the
requirements of data integrity in system need to be improved as well. This article
DESIGN AND presents a data integrity-checking method based on MD5 in order to ensure that the
IMPLEMENTATION FOR data of information system is in correct state. It also elaborates the principle of MD5
8 MD5-BASED DATA
2010 algorithm, researches a way to utilize data integrity checking method on the protection
of information system. Finally, the paper designs and implements a data integrity
INTEGRITY CHECKING checking system based on MD5 algorithm. Practice has shown that the IT departments
SYSTEM of the enterprise achieve the system management and security auditing with the data
integrity checking system.

This paper first presents a new architecture of SHA-1, which achieved the theoretical
upper bound on throughput in the iterative architecture. And then based on the general
ULTRA HIGH proposed architecture, this paper implemented other two different kinds of pipelined
THROUGHPUT architectures, which are based on the iterative technique and the loop unrolling
9 ARCHITECTURES FOR
2009
technique respectively. The latter with 40-stage pipeline reached a throughput up to
SHA-1 HASH ALGORITHM 76.195Gbps on an Altera Stratix II GX EP2SGX90FF FPGA. At least to the authors'
knowledge, this is the fastest published FPGA-based design at the time of writing. At last
ON FPGA the proposed designs are compared with other published SHA-1 designs, the designs in
this paper have obvious advantages both in speed and areas
To accelerate the speed of iterative computation for the existing SHA-256 algorithm,
using 7-3-2 array compressor is proposed to reduce the critical path delay in this paper.
The frequency of the proposed scheme is 1.7 times higher than other VLSI
implementations under the same process. In addition, the paper designs a new universal
1 VLSI IMPLEMENTATION 2009
architecture for implementing SHA-2 algorithms. The design is synthesized with the slow
0 OF HIGH-SPEED SHA-256
library of Synopsys Design Compiler in SMIC 0.18 um CMOS process. Its function has
been verified sufficiently on FPGA. Furthermore, compared with the existing SHA-256
core, the results of the ASIC synthesis and FPGA verification are more preferable. This
design is convenient to implant into SOC and embedded system with the versatile
architecture and high clock frequency
 This work presents a low-power multiplier using a Dynamic-Range Determination (DRD)
unit and a modified Upper/Lower Left-to-Right (ULLR) structure in the Partial-Product
Summation (PPS) unit. Prior to executing a multiplication, effective dynamic ranges of
LOW-POWER MULTIPLIER
1 OPTIMIZED BY PARTIAL- 2009
two input data are estimated by the DRD unit to determine that these input data with
smaller and larger dynamic ranges are multiplier and multiplicand for Booth decoding,
1 PRODUCT SUMMATION respectively. Such approach can exhibit that partial products in high precision have a
high chance of being zero. Due to this phenomenon, the ULLR structure is modified by
AND ADDER CELLS
moving the correction bits from the upper part to the lower part of the PPS unit to
reduce switching power.
Most Field Programmable Gate Array (FPGA) devices have a special fast carry
propagation logic intended to optimize addition operations. The redundant adders do
not easily fit into this specialized carry-logic and, consequently, they require double
hardware resources than carry propagate adders, while showing a similar delay for small
size operands. Therefore, carry-save adders are not usually implemented on FPGA
EFFICIENT devices, although they are very useful in ASIC implementations. In this paper we study
1 IMPLEMENTATION OF 2009
efficient implementations of carry-save adders on FPGA devices, taking advantage of
2 CARRY-SAVE ADDERS IN
the specialized carry-logic. We show that it is possible to implement redundant adders
with a hardware cost close to that of a carry propagate adder. Specifically, for 16 bits
FPGAS and bigger word-lengths, redundant adders are clearly faster and have an area
requirement similar to carry propagate adders. Among all the redundant adders studied,
the 4:2 compressor is the fastest one, presents the best exploitation of the logic
resources within FPGA slices and the easiest way to adapt classical algorithms to
efficiently fit FPGA resources.