EC6201- Basics of VLSI Lab

Mini - Project
Monsoon Semester – 2010
Submitted By,
Rakesh Madala (M100258EC)
Pavan Kumar K (M100278EC)
GSNS Krishna (M100413EC)

Introduction: The XOR circuit is basic building block in various circuits, especially-
Arithmetic circuits (Full adder, and multipliers), Compressors, Comparators, Parity Checkers,
Code converters, Error detecting or Error-correcting codes, and Phase detector. The performance
of the complex logic circuits is affected by the individual performance of the XOR circuit that is
included in them. Therefore, careful design and analysis is required for XOR circuit to obtain full
output voltage swing, lesser power consumption and delay in the critical path. Additionally, the
design should have a lesser number of transistors to implement XOR circuit.
We would like to analyze and compare an XOR gate build using CMOS Logic and Pass
Transistor Logic (PTL) individually. The noise margins and delays are to be analyzed
individually for both CMOS Logic and Pass Transistor Logic. And then we would like compare
the both technologies based on the values obtained in the analysis stage.

XOR Gate Using CMOS Logic:

Initially we created a two input NAND gate using CMOS technology with L min =
180nm.Using this NAND gate as a unit we created an XOR gate using minimum number of
NAND gates. The dimensions are as follows: (W/L) N = 2; For PMOS transistors the sizing is
varied from 1 to 4.
(W/L)P = (W/L) N to 4(W/L) N.

Figure 1: Basic NAND Gate. Figure 2: XOR Gate using NAND Gates.
By performing DC analysis for this XOR gate we have obtained the following values.
A = 1.8V and B = 0 to 1.8V A = 0 to 1.8V and B = 1
NML NMH PStatic NML NMH PStatic
(W/L)P = (W/L)N 684mV 1.08V 175.5pW 720mV 1.04V 175.5pW
(W/L)P = 2(W/L)N 792mV 972mV 178.3pW 828.02mV 936.02mV 178.3pW
(W/L)P =3 (W/L)N 828mV 936mV 189pW 864.03mV 900mV 189pW
(W/L)P =4 (W/L)N 936mV 864.mV 201.9pW 900mV 864mV 201.9pW

è As the width of PMOS transistor is increased, NML increases and NMH decreases. This is due
to the fact that as the width of PMOS transistor is increased the VTH moves towards VDD. Then
VIL increases and VIH decreases.
è As the sizing is increased, static power dissipation is increased. The reason is that as the width
is increased the resistance of the PMOS transistors decreases. This causes an increase in the
current flow and thus static power dissipation increases.

During Transient analysis the inputs given are square waves with different pulse widths.
For A: Pulse width = 30ns and f = 16.66MHz; For B: Pulse width = 25ns and f = 20MHz.
Here XOR gate taken is with the unit NAND Gate having (W/L)P = 4(W/L)N.

TPLH TPHL
A =1: B =1 0 0.189ns A =1: B =0 1 0.208ns
A =0: B =0 1 0.124ns A =0: B =1 0 0.123ns
A =1 0: B =1 0.195ns A =0 1: B =1 0.222ns
A =0 1: B =0 0.128ns A =1 0: B =0 0.117ns

è Simulated for a time of 400 ns and the total dynamic power dissipated in this time is 443.7nW.

XOR Gate Using Pass Transistor Logic: Using PTL we created an XOR gate with the
following dimensions. Inverters are used in the circuit to generate complement of the input
signals. For inverter (W/L)pmos = 4(W/L)nmos.The sizing of the transistor used in the circuit is
varied from (W/L)NMOS = 2 to (W/L)NMOS = 4.

Figure 3: XOR gate using Pass gates. Figure 4: Finding delays in XOR gate.
DC Analysis:
A = 1.8V and B = 0 to 1.8V
VOH VIH VOL VIL PStatic
W = 2 L to 4L 1.57V 936mV 0V 2.42mV 39.8pW

A = 0 to 1.8V and B = 1.8V

VOH VIH VOL VIL PStatic
W = 2 L to 4L 1.657V 1.04V 105.5mV 760mV 39.8pW

è Though the Width of the NMOS transistor is increased from 2L to 4L there is no variation in
the static parameters.
è The noise margins are found to be very low for the XOR gate using Pass Transistor logic. The
reason for this condition is that the output will be VDD - VTH i.e., threshold voltage drop at the
output of the pass transistor gate.

The Transient analysis of the XOR gate gave us the following values. During Transient analysis
the inputs given are square waves with different pulse widths.
For A: Pulse width = 30ns and f = 16.66MHz; For B: Pulse width = 25ns and f = 20MHz.
TPLH TPHL
A =1: B =1 0 0.0544ns A =1: B =0 1 0.008ns
A =0: B =0 1 0.0719ns A =0: B =1 0 0.042ns
A =1 0: B =1 0.049ns A =0 1: B =1 0.062ns
A =0 1: B =0 0.023ns A =1 0: B =0 0.0334ns

è Simulated for a time of 400 ns and the total dynamic power dissipated in this time is 13.25nW.

Comparison:
.
Area:
è For CMOS logic case the number transistors required are 16.Because we used 4 NAND gates.
è For PTL case, it requires only 2 NMOS transistors to implement the XOR gate. But to provide
the complement of inputs we required 2 inverters which use 4 transistors.
è Comparing the both cases, CMOS logic is using more number of transistors and hence more
area.

Noise Margin:

è The noise margin for CMOS logic case is high compared to PTL case. Because in CMOS
logic the VOH and VOL are VDD and 0 respectively. But for PTL case the VOH = VDD - VTH and
VOL is slightly increased from 0 to few mV.
è This is the main drawback of the PTL XOR.

Speed:

è Comparing the transient analysis of both the logics, the CMOS logic is having more delay
compared to PTL.
è This is due to the fact that CMOS logic is having more number of transistors and more
capacitance. Because of this internal capacitance the delay is more pronounced in CMOS logic
compared to PTL.
 Power Considerations:
Static Power:
è Though the static power is very less in both the cases (order of pW).The PTL case (39.8 pW)
is having less static power dissipation than CMOS logic case.
è The reason behind this is again the area consideration.

Dynamic Power:
è Again the Pass Transistor Logic case (13.25nW) is having very less dynamic power
dissipation compared to CMOS logic case (443.7nW).
è The reason behind this is that in CMOS logic there are more number of transistors and hence
more capacitance and more ON resistance. Hence charging and discharging this more
capacitance and current flow across this more ON resistance causes more dynamic power
dissipation.

Conclusion:
We have reviewed CMOS logic and PTL techniques for XOR circuit. The mentioned
design techniques are compared based on Area, Noise Margins, delay and power consumption.
The performances of these techniques have been evaluated by cadence 0.18µm CMOS
technology. Based on the simulation results, it has been culminated that in the Pass Transistor
Logic based XOR the output high (or low) voltage is deviated from the VDD (or ground) by a
multiple of threshold voltage. Except the Noise Margin, the PTL XOR is far more superior to
CMOS logic XOR.