Why FPGAs are better than DSPs for Motor Control ? - PE-FPGA.com http://www.pe-fpga.com/?

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Oct.26, 2010 in Motor Control IP, Embedded Systems, FPGA, Applications

That’s the main question I have been asked at last IEEE Energy Conversion & Congress Expo (ECCE2010) at Atlanta last
month where Alizem had its booth demoing its COTS Motor Control IP for Pump and Fan Applications released last spring
(see white paper and datasheet on Alizem’s website).

The answer to this question may be similar to asking if the latest Lady Gaga album is better on CD or as mp3 files running on
an iPod. Technically, the IP performance (the music) is going the be the same on both platforms, the difference is the IP
form factor and all its implications for the singer, the music platform manufacturer and the user. CDs need to be
manufactured, delivered, may be scratched, stolen, etc. while mp3 files (whatever the format) are pure IP that can be easily
dowloaded from anywhere at practically no cost, has higher margins, no degradation over time, etc. I already did that kind of
exposé in by Motor Control IC vs Motor Control IP blog post.

On another perspective, if we strictly consider FPGA vs DSP chip for motor control (and in a general embedded system
design perspective) it is obvious that DSP wins the battle. Why ? Because FPGAs are blank chips while DSP are chips
having built-in processor & peripherals meaning that out-of-the box you can begin to develop your application software on a
DSP while you cannot on an FPGA (you need to design the HW layer first then proceed to SW development). Hence FPGAs
have one level of complexity higher than DSP and while this can become on one side an advantage (increased flexibility for
new features bringing more value) it is on the other side a disadvantage because the same solution is going to cost more and
take more time to develop (based on the same engineering methodology which to build everything in-house from scratch).
We are not even talking about the fact that most motor control people are currently DSP/MCU users hence have not
necessarily the skills for HW development.

Hence the strict FPGA approach doesn’t offer to motor control designer to have “more with less” compared to DSP. At that
level, the only tangible advantage for FPGAs is to provide to motor control system designer a single design environment
where the complete system - HW&SW - can be developped (as opposed to the conventional approach where each chip has
its own tools that needs to be learnt and where lots of time is invested in component integration).

To overcome this problem, we need to consider “FPGA & IP” vs DSP. That is completely different. With an FPGA & IP
approach, the HW development phase is reduced to its minimum which is to integrate IP components together (processor IP,
motor control IP, communications IP, HMI IP, etc.). While this process can be a nightmare if not done correctly, it takes
only a few minutes if done with the correct tools (e.g. using SOPC Builder in the case of Altera FPGAs - hence their slogan
‘from ideas to system in minutes’ - or using Xilinx’s Platform Studio).

Real gains over DSP approach are made by using system components around the processor that are application-specific
(here’s a great blog article on application-specific intellectual property, ASIP): not only the designer has the freedom to
select IP components that strictly fits its design (no more, no less), but his IP providers are continously working to improve
them to specifically fit their needs (this goes beyond traditionnal processor peripherals) hence providing always more value
over time (wheter functionnal features and/or reducing integration time).

For motor control systems, that means passing from one-fits-all/generic PWM blocks and transducer interfaces (to be
configured by the system designer) to specific (pre-configured) motor control block that includes PWM, transducers
interfaces and software drivers running on a FPGA embedded processor (read this white paper for more details). That
processor can even be the same processor that you have always been using but integrated on an FPGA (I am refering here to

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Why FPGAs are better than DSPs for Motor Control ? - PE-FPGA.com http://www.pe-fpga.com/?p=40

Freescale’s ColdFire processor that’s available as IP for Altera FPGAs, there’s certainly more to come) !

DSP FPGA FPGA & IP

Out-of-the-box experience
Great. Low. Great.

Processor Fixed. None. Configurable.

HW components (peripherals)
Fixed. None. Configurable.

System components integration

Tedious (HW) Easy (SW). Easy (SW)

Requires Motor Control expert

Yes. Yes. No.

Cost of HW/SW maintenance

High. Very High. Low.

In this scheme, we can see a shift of the “secret” motor control sauce from the system designer to the (application-specific)
IP provider. In reality, the real secret sauce is always in the hands of the motor control system designer which is to build the
best machine for a targeted application. By leveraging motor control IP in his design, he can invest his time and ressources in
doing a better sauce, quicker and cheaper.

All this happens by considering the FPGA chip as a system integration platform for third-party IP where gains (leading to
lower TCO) come from ease of component integration (software integration) in a single design environment and leverage of
outsourced domain expertise through IP procurement/reuse, especially in the case of very complex applications such as
motor control.

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Motor Control IP: IP Subsystems - The Next IP Market Paradigm http://bit.ly/g9qP3i http://bit.ly/gvdfe6 #FPGA
#semip #embedded 1 day ago
FPGA Technology as a Platform for Innovation Integration in Motor Drives Applications e-Drive conf.
http://bit.ly/fXQdp1 #FPGA #embedded 1 day ago
Motor Control: RT @MaxMaxfield: Xilinx FPGA development platforms accelerate industrial system designs
http://bit.ly/fQlFO3 2 days ago
RT @alizemip: Creating industrial apps with Altera FPGAs and Alizem motor-control IP: EE Times http://bit.ly

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Why FPGAs are better than DSPs for Motor Control ? - PE-FPGA.com http://www.pe-fpga.com/?p=40

/gdymND 2 days ago

I will attend EETimes Virtual Conference System-on-Chip 2.0 tomorrow, let's meet there! http://goo.gl/A7ijW 7
days ago

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