IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO.
5, MAY 2009
Single-Phase Multilevel PWM Inverter Topologies
Using Coupled Inductors
John Salmon, Member, IEEE, Andrew M. Knight, Senior Member, IEEE,
and Jeffrey Ewanchuk, Student Member, IEEE
Abstract—The number of voltage levels available in pulsewidth
modulation (PWM) voltage source inverters can be increased by
using a split-wound coupled inductor within each inverter leg and
interleaved PWM switching of the upper and lower switches. The
magnetizing inductance of the symmetrical split-wound inductor
filters the high-frequency PWM voltage differences between the
upper and lower switches. The same inductor presents a three-level
PWM voltage at the inverter output terminals, with the winding
leakage inductance being located in series with the low-frequency
output current. Deadtime PWM signal delays can be reduced as
dc-rail short circuits are not possible: as a result, the quality and
voltage range of the PWM output is improved. Since the inductor
windings are technically exposed to high-frequency PWM ac volt-
ages with no dc components, device voltage drops help to reduce
the buildup of winding dc currents. Theoretical analysis and a sam-
ple design case are presented to illustrate how to design suitable
inductors for the various topologies. Simulation and experimental
results are used to illustrate the operation of the proposed inverter
structures.
Index Terms—Coupled inductors, interleaved pulsewidth mod-
ulation (PWM), multilevel inverters, PWM rectifiers, single-phase
rectifiers.
I. INTRODUCTION
HE STANDARD two-switch and four-switch inverters
T [Fig. 1(a) and (b)] are the preferred topologies in many
low-power single-phase systems such as fractional horsepower
ac drives, lighting equipment, alternative energy systems, etc. As
the performance factors, power level and fundamental operating
frequencies are increased, the ac filter inductor size and device
switching frequencies become restrictive design factors: high
energy storage requirements increase the inductor size, and max-
imum switching frequencies are limited by power losses, gate
drive restrictions, pulsewidth modulation (PWM) deadtimes,
etc. As a result, the high-frequency current ripple at the inverter
output may not be as low as required and can cause problems
such as excessive heating in motor drives, electromagnetic in-
terference (EMI)/RF interference (RFI), and larger-than-desired
Manuscript received May 14, 2008; revised September 30, 2008. Current
version published April 29, 2009. This work was supported by the Natural
Science and Engineering Research Council of Canada and the University of
Alberta. Recommended for publication by Associate Editor P.-T. Cheng.
The authors are with the Department of Electrical and Computer Engi-
neering, University of Alberta, Edmonton, AB T6G 2V4, Canada (e-mail:
salmon@ece.ualberta.ca; knight@ece.ualberta.ca; ewanchuk@ece.ualberta.ca).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2008.2012110
0885-8993/$25.00 © 2009 IEEE
1259
output ac filters (large ac filter inductors are expensive, increase
losses, and have a large fundamental voltage drop).
Parallel-connected inverter modules, which either use cur-
rent ripple cancellation or alternatively multilevel PWM output
voltages [1]–[9] [e.g., Fig. 1(c), (e), and (f)], are widely used
techniques for increasing the effective PWM and current ripple
frequency above the device switching frequency. This often re-
sults in lower device losses, smaller inductors, a lowering of the
current ripple magnitude, and a faster inverter transient response.
Parallel-connected modules often use interleaved PWM and ac
filter inductors connected between the modules to achieve high-
frequency current ripple cancellation and a lower output current
ripple. There are many current balancing issues [4]–[8] and since
the various inductors cannot be guaranteed to have the same
characteristics, harmonic current cancellation may not be opti-
mal. Inverters with increased PWM levels have been proposed
in motor drives [9] and interleaved PWM is used in parallel-
connected inverters [10], [11], boost converters [12], [13], buck
converters [14], [15], and an asymmetrical bridge [16]. Cou-
pled inductors [17] and interleaved PWM techniques [18],
three-level half-bridge [20], and four-level half-bridge [21] are
also used in many situations. PWM signal deadtimes are used
to avoid shorting the dc supply, and many papers have been
written to provide compensation for their undesirable features
[21]–[24].
The proposed inverter topology differs from many of these
schemes because, rather than adding more switch modules and
ac inductors, coupled inductors are included inside the standard
modules using interleaved PWM of the upper and lower switches
in an inverter leg [see Fig. 2(a) and (b)]. Multilevel PWM output
voltages are obtained with a PWM frequency higher than the
switching frequency. The resultant topologies use smaller ac
filter inductors, faster transient response, fewer switches, do not
experience critical dc supply shorts, improve the quality of the
PWM waveforms by eliminating the need for switch deadtimes,
and are immune to circulating currents.
II. PROPOSED TOPOLOGY USING COUPLED INDUCTORS
This section places the proposed topologies in context with
existing topologies and describes how coupled inductors can be
used to produce multilevel PWM voltages.
One technique used in high-power motor drives for producing
multilevel PWM waveforms with an increased PWM frequency
is to stack modules in series and use separate isolated dc voltage
sources for each module [Fig. 1(c)]. This technique is suited
for high-power systems and often uses harmonic cancellation
ac input transformers. The four-switch three-level neutral point
1260
Fig. 1. Single-phase multilevel inverters. (a) Standard two-switch inverter leg. (b) Standard four-switch H-bridge. (c) Stacked dual inverter. (d) Eight-switch
H-bridge. (e) Interleaved dual inverter: current ripple cancellation. (f) Interleaved dual inverter with multilevel PWM voltage output.
Fig. 2. Proposed single-phase inverters using coupled inductors. (a) Two-
switch inverter leg. (b) Four-switch H-bridge.
clamped (NPC) inverter leg is considered a suitable technique in
high-voltage and high-power applications because the switches
are exposed to half the dc-rail voltage and three-level PWM volt-
ages are produced at the output of each inverter leg [Fig. 1(d)].
An often used technique for parallel-connected inverters is to
connect the inverter output terminals using ac filter inductors
and interleaved PWM for current ripple cancellation: as a result,
the effective size of the ac filter inductors can also be reduced
[Fig. 1(e)]. An alternative scheme uses interphase inductors, or
chokes, and interleaved PWM switching to produce multilevel
PWM voltages at the output terminals [Fig. 1(f)]. This tech-
nique is especially useful if the load is inductive, e.g., motors
and high-speed generators. The interphase inductors are small
in size due to their relatively low magnetic ac flux magnitude.
AC filter inductors may be required to filter the output, but their
size is reduced because of the high-frequency multilevel PWM
voltages produced.
The inverters described before are more complex, increase
switch count, have issues with circulating currents, and experi-
ence unbalanced operation due to parasitic variations in the cir-
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 5, MAY 2009
cuit parameters. The proposed topologies alleviate some of these
problems by placing coupled inductors inside the structures of
the standard inverters (Fig. 2). The upper and lower inverter leg
switches experience two-level PWM switching; however, the
proposed two-switch topology produces three-level PWM volt-
ages at its output terminal and the four-switch topology produces
five-level PWM voltages across its two output terminals.
The proposed H-bridge produces PWM voltage waveforms
similar in nature to the eight-switch NPC H-bridge shown in
Fig. 1(d), e.g., five-level across the two output terminals. How-
ever, the proposed H-bridge may be considered as having several
desirable features relative to the NPC H-bridge.
1) Four switches and 8 diodes are used compared with eight
switches and 12 diodes for the NPC H-bridge.
2) The frequencies of the various PWM waveforms are dou-
ble that of the NPC H-bridge.
3) For the same output current ripple, the proposed H-bridge
uses an ac filter inductor half the size than required for the
NPC H-bridge: as a result, lower ac filter inductor losses
can be achieved.
4) A single dc supply is required compared with the capacitor
split dc-rail for the NPC H-bridge.
5) The coupled inductor allows the switch deadtimes to be
removed. As a result, a higher fundamental output voltage
and device switching frequency are possible compared
with the NPC H-bridge.
6) Half the device voltage drops are experienced relative to
the NPC H-bridge.
The proposed topology has several disadvantages relative to
the NPC H-bridge inverter. The NPC H-bridge has lower switch-
ing losses due to the lower device voltage stresses. The NPC
H-bridge has half the switch voltage stress and can be operated
with very low device switching frequencies, which are consid-
ered very useful characteristics in high-power applications. The
SALMON et al.: SINGLE-PHASE MULTILEVEL PWM INVERTER TOPOLOGIES USING COUPLED INDUCTORS 1261

Fig. 3. Magnetic core and winding arrangements for the coupled inductors. Fig. 5. Equivalent circuits of the proposed inverter leg. (a) Transformer equiv-
(a) Windings located on the center limb. (b) Layered winding. alent model. (b) Output terminal model. (c) Circuit model between the switches.

Fig. 4. Switching states of the proposed inverter leg. (a) Basic switching cell.
(b) S a U , S b L ON: v a = v d c /2. (c) S a U , S a L OFF: v a = v d c /2. (d) S a U OFF,
S a L ON: v a = 0. (e) S a U ON, S a L OFF: v a = v d c .

proposed H-bridge requires relatively high device switching fre-

quencies to lower the size of the coupled inductor, resulting in
extra inductor core losses. These disadvantages can be traded
with a lower overall inductor size and weight, lower core losses
in the ac filter inductor, and a much higher PWM frequency at
the output terminals than is possible with the NPC H-bridge.
The latter can result in removing PWM frequency losses from a
load that is sensitive to such losses, e.g., a high-speed machine.
The coupled inductor losses can be of the same order as the
conduction losses associated with the extra switches used in the
NPC H-bridge.
The main feature of the proposed topologies is the insertion
of a symmetrical split-wound coupled inductor between the up-
per and lower switches in the inverter legs, with the coupling
direction as indicated by the dots, and the center tap of the in-
ductor forming the output terminal [Fig. 2(a) and (b)]. The two
windings of the inductor are closely coupled, with a low leakage
inductance, and can be wound on a standard three-limb mag-
netic core, as shown in Fig. 3. This inductor provides more than
just protection against dc-rail shorts; it also allows interleaved
PWM switching of the upper and lower switches and an extra
output voltage level equal to one-half of the dc supply voltage.
Fig. 6. Two-level interleaved PWM control to produce a three-level PWM
III. OPERATION OF THE PROPOSED THREE-LEVEL output.
INVERTER LEG
The switching operation of the proposed two-switch inverter inverter leg includes a winding leakage inductance L
, magne-
leg is described here. The coupled inductor and two-level in- tizing inductance Lm , and an ideal transformer (Fig. 5). The
terleaved PWM switching of the upper and lower switches are equivalent circuits illustrate that the output terminal consists of
shown to produce three-level PWM output voltage waveforms three-level PWM voltages [see va , with L
/2 in series, Fig. 5(b)]
with balanced winding currents and no dc offsets. and a large magnetizing reactance in series between the switches
If the two switches in the proposed inverter leg are controlled [Fig. 5(c)]. A typical two-level interleaved PWM control scheme
using standard two-level interleaved PWM techniques, then four is illustrated in Fig. 6, together with the three-level output
switching states are possible (Fig. 4). A simplified model for the voltage va . The experimental waveforms shown in Fig. 7(a)
1262
Fig. 7. Experimental waveforms for the split-wound coupled inductor and inverter leg. (a) 60 Hz fundamental cycle. (b) Expanded waveforms.
show that high-quality three-level sinusoidally modulated PWM
voltages are obtained at the output terminals (see ia and va ). The
nature of the voltage waveform va illustrates that the leakage
inductance between the windings is low. The inductor voltage
vaUL [Fig. 7(b)] illustrates that the PWM cycle inductor volt-
age is symmetrical with no dc component. This feature exists
over the complete output voltage range; hence, no winding dc
current drifts or core saturation is produced by the interleaved
PWM control scheme.
There is always a concern that dc and circulating currents are
produced in parallel-connected inverters. Ideally, the parallel
circuit paths have identical voltage drops and the natural vari-
ations in the device operating conditions can cause unbalanced
currents. The device voltage drops in the proposed topology
produce a net negative voltage drop across the inductor (equal
to one switch and one diode voltage drop on average) that acts
against dc current drifts or circulating currents. Experimental
testing illustrated that the switch turn-OFF times can produce a
positive inductor voltage drop, and hence, a dc current. How-
ever, practically, this can be overcome easily by introducing a
small difference between the switching of the upper and lower
switches to provide a small net negative inductor winding volt-
age drop, and hence, guarantee that no dc current builds up.
It should be noted, however, that the inductor windings have a
natural dc current component determined by the magnitude of
the ac output current (see iaU , iaL in Fig. 7).
IV. RIPPLE CURRENT AND INDUCTOR SIZE
The analysis presented in this section uses a per unit system to
allow inductor sizes to be chosen based upon the current ripple
Vs2
Ls = Lsp.u. Lb Pbase = Vs Ibase Lbase =
2πfs Pbase
A test condition is used to compare the inductor size and the
high-frequency current ripple for the various inverter topologies:
Vs = 120 V, fs = 60 Hz, Is,pk = 10 A, ∆Im ax = 5% peak-to-
peak (pk-pk), Vdc = 1.5 Vs , switching frequency fc = 10 kHz
(note: Vs is the ac load voltage).
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 5, MAY 2009
A. AC Supply Filter Inductor Ls
The maximum high-frequency pk-pk current ripple for the ac
filter inductor Ls is ∆Im ax and can be sized relative to the 60 Hz
pk-pk value of the ac output current Ipp using Ris , Rf , and Rv
Ipp fc Vdc
Ris = Rf = Rv = √ . (2)
∆Im ax fs 2Vs
Hence, for the test condition, Ris = 20, Rv = 1.06, and Rf =
166.7.
For the standard two-switch inverter leg, ∆Im ax occurs when
the inverter output terminal has a 50% duty ratio with the volt-
age switching between +Vdc and −Vdc [Fig. 1(a)]. The supply
inductor Ls sees a PWM voltage that is a symmetrical square
wave at the carrier frequency fc and magnitude Vdc
Vdc 2Ipp fc Ls
∆Im ax = Ris = . (3)
2fc Ls Vdc
Equations (1)–(3) can be used to link Lsp.u. with ∆Im ax . Similar
analysis can be conducted for each of the topologies shown in
Figs. 1(a) and (b), and 2(a) and (b), with the results given in
Table I.
Hence, suitable inductors to meet the test conditions are as
follows.
1) Two-switch inverter leg (Lsp.u. = (1.57)[(20 × 1.06)/
166.7] = 0.2 p.u.): With Lbase = 45 mH and Ls = 9 mH,
this inductor will have a 20% fundamental voltage drop at
the rated current.
2) Four-switch standard H-bridge (Lsp.u. = 0.392[(20 ×
1.06)/166.7] = 0.05 p.u.): With Lbase = 45 mH, Ls =
2.25 mH, this inductor will have a 5% fundamental volt-
age drop at the rated current.
. (1) 3) Two-switch coupled inductor (Lsp.u. = 0.392[(20 ×
1.06)/166.7] = 0.05 p.u.): Ls is the same as for the four-
switch H-bridge, 2.25 mH, with a 5% fundamental voltage
drop across the inductor at rated current.
4) Four-switch coupled inductor (Lsp.u. = 0.1[(20 ×
1.06)/166.7] = 0.0127 p.u.): With Lbase = 45 mH
and Ls = 0.57 mH, this inductor will have a 1.3%
SALMON et al.: SINGLE-PHASE MULTILEVEL PWM INVERTER TOPOLOGIES USING COUPLED INDUCTORS 1263

TABLE I TABLE II
DESIGN PARAMETERS FOR THE AC FILTER INDUCTOR L s DESIGN PARAMETERS FOR THE COUPLED INDUCTOR L t

fundamental voltage drop at rated current and is four TABLE III

times smaller than required for the standard four-switch INDUCTOR DESIGNS USING LOW-PERMEABILITY CORES
inductor.

B. Inverter Leg Coupled Inductor Lt

1) Two-switch coupled: The maximum pk-pk high-frequency
current ripple occurs when the inductor Lt sees a PWM
symmetrical square-wave voltage of magnitude ±2 Vdc
and frequency fc .
2) Four-switch coupled: Similarly, the coupled inductor Lt
has a maximum current ripple when it sees a PWM sym-
metrical square-wave voltage of magnitude ±Vdc and fre-
quency fc
Design parameters for the inductors are given in Table II using
the design parameter
Ipp
Rit = . (4)
∆It,m ax

A recommended minimum value for Rit should be 4 to avoid

excessive core losses and discontinuous winding currents; 8 or
higher value significantly lowers the core losses and results in
the high-frequency current ripple, but significant Cu losses can
then be experienced.
The four-switch H-bridge under the test conditions: Rit = 4,
Rv = 1.06, Rf = 166.7: Lt,p.u. = 0.04 p.u. = 1.8 mH.
Tables I and II allow the designer to pick suitable inductors,
in terms of millihenries, given a desired current ripple. When
compared with the standard topologies, the coupled inductors
reduce the ac filter inductor by a factor of 4. The high-frequency
ripple in the ac filter inductor is twice the carrier frequency for
the proposed two-switch topology (four times for the H-bridge)
and the inductor losses are significantly reduced, as the inductor
current ripple magnitude is much smaller.
In general, the standard two-switch inverter has a very large
relative current ripple, but when using the coupled inductors,
it produces a ripple current magnitude equal to the standard
H-bridge. The four-switch H-bridge with a coupled inductor
produces a current ripple magnitude comparable to when us-
ing two 4-switch H-bridges and a standard ac filter inductor.
Inverters using the coupled inductors produce the same perfor-
mance as standard inverters using twice the power electronics
and lower the size of the ac inductors and their fundamental
voltage drop. This increases the fundamental load voltage and
lowers the load current. This has the effect of lowering the losses
in the semiconductors and inductors. Fig. 8. Experimental inductors.
1264
Fig. 9. Experimental comparison between the standard H-bridge and the proposed H-bridge. (a) Standard. (b) Using coupled inductors.
V. INDUCTOR DESIGN STUDY
Inductor design parameters are compared here for a single-
phase four-switch H-bridge inverter using the following design
criteria: Vs = 120 V, fs = 60 Hz, Is = 7 A, with fc = 20 kHz
and Vdc = 200 V. Designs are considered for several max-
imum current ripple magnitudes: ∆It,m ax = 1.5, 4, and 6 A
(see Table III).
Inductors used in Table III are:
1) Ls1 : standard H-bridge ac inductor;
2) Ls2 : ac inductor for the proposed H-bridge;
3) Ls3 : experimental ac inductor used for the proposed
H-bridge;
4) Lta,b : H-bridge coupled inductors (1: ∆It,m ax = 1.5 A,
2: ∆It,m ax = 4 A, 3: ∆It,m ax = 6 A).
The coupled inductor required for each winding current ripple
can be compared with each other and the ac filter inductor Ls .
Several design guidelines were used.
1) Low-permeability cores with a distributed airgap were
considered for all the ac inductors due to their slow sat-
uration characteristics. The maximum permissible core
saturation was set at 50%.
2) High-permeability ferrite cores with an airgap were not
considered, as all inductors can be exposed to surge cur-
rents and have significant “dc flux” and energy storage.
3) The wire size was chosen to have the minimum cross
section suitable for the rms current with no attempt to
minimize the Cu losses.
4) The maximum ripple in the ac flux (Bac ) and manufacturer
data was used to estimate the core losses. This produces a
large overestimate in the predicted core losses but is useful
for comparison purposes.
Note that the designs for the ac filter inductors (Ls1 and Ls2
in Table III) were chosen to give the same current ripple in
both the bridge types, e.g., the standard H-bridge and the pro-
posed H-bridge (see ∆Im ax in Table III). For the experimental
waveforms, a 1-mH inductor was used for both cases (Ls3 in
Fig. 8) to compare the effect on the ac current ripple of using the
proposed H-bridge rather than the standard H-bridge. A typical
design table for the various inductors is given in Table III and all
the inductors used in experimental testing are shown in Fig. 8.
For the coupled inductor Lt (see Table III), the winding ripple
current cases of 4 and 1.5 A, the total weight, WtTotal , of the
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 5, MAY 2009
inductors used is less than the weight of the ac filter inductor
required for the standard H-bridge.
1) Standard H-bridge: WtTotal = 2222 g.
2) Proposed H-bridge (∆It,m ax = 6 A): WtTotal = 650 +
2 × 265 = 1170 g.
3) Proposed H-bridge (∆It,m ax = 4 A): WtTotal = 650 +
2 × 402 = 1604 g.
4) Proposed H-bridge (∆It,m ax = 1.5 A): WtTotal = 650 +
2 × 1002 = 2652 g.
If the winding ripple current is made too small, e.g.,
∆It,m ax = 1.5 A, the total inductor weight required can be
increased above that required for the standard inverters: if too
large, ∆It,m ax = 6 A, excessive core losses can be experienced.
These results illustrate that the proposed topology can halve the
number of switches and can also be used to lower the com-
bined inductor weight. This weight reduction is limited by the
winding dc magnetizing current component and the inductor
core losses. Magnetic cores with lower core loses should be
considered rather than those used here. The main benefit of the
proposed approach is to allow multilevel PWM switching using
half the power electronics and suitable for applications using an
inductive load such as a motor.
VI. EXPERIMENTAL WAVEFORMS
The experimental waveforms presented in this section used
a general-purpose laboratory test inverter with the following
inductors (see Fig. 8) and load parameters.
1) Vs = 120 V; Is = 7 A, fs = 60 Hz, Vdc = 200 V, fc =
20 kHz.
2) Standard H-bridge: ac filter inductor = Ls1 .
3) Proposed H-bridge: ac filter inductor = Ls3 .
4) Coupled inductor = Lt1a,b , Lt2a,b .
The same standard laminated iron ac filter inductor was used
in all cases (Ls3 = 1 mH, Fig. 8) to allow comparison of the
ac load current ripple magnitude. The interleaved PWM signals
were generated using a TI TMS320F2812 DSP.
Since the proposed four-switch H-bridge produces five-level
PWM voltage waveforms across its two output terminals com-
pared with the three-level in the standard H-bridge, the out-
put current ripple is reduced by 25% relative to the standard
H-bridge (Fig. 9).
SALMON et al.: SINGLE-PHASE MULTILEVEL PWM INVERTER TOPOLOGIES USING COUPLED INDUCTORS
Fig. 10. Experimental comparisons of the coupled inductor winding currents as a result of using different inductor sizes (see Table III for the inductor parameters).
(a) L ta , b = L t2 a , b . (b) L ta , b = L t1 a , b .
Fig. 11. Experimental waveforms for the proposed inverter leg illustrating the
three-level PWM output voltage and a “raised cosine” winding current wave
shape: L ta , b = L t1 a , b (see Table III for the inductor parameters).
Fig. 12. Experimental coupled inductor winding dc magnetizing current ic m
compared with the ac load current ia : L ta , b = L t1 a , b (see Table III for the
inductor parameters).
The magnitude of the coupled inductor winding current rip-
ple does not affect the load current ripple or the quality of the
PWM output voltage waveforms (Figs. 9 and 10). The coupled
inductor winding currents have a magnetizing current icm with a
dc component equal to half the peak ac output current (Figs. 10
and 12) and a high-frequency current ripple determined by the
inductor size. The three-level inverter leg output voltage wave-
1265
form is shown in Fig. 11 with the middle voltage level sitting at
one-half the dc-rail voltage. The coupled inductor magnetizing
current and its ripple, relative to the ac load current, are shown
in Fig. 12. Since this dc component is about one-half the peak
current, its physical size is reduced.
VII. CONCLUSION
The use of a coupled split-wound inductor has been described
to allow interleaved PWM switching of the upper and lower
switches in an inverter leg. This increases the number of PWM
voltage levels at the inverter output terminals and doubles the
PWM frequency. The main benefits of this topology are the
following.
1) Multilevel PWM uses half the power electronics of alter-
native schemes; e.g., when compared with the standard
topologies, two-level is increased to three-level and three-
level is increased to five-level.
2) The load high-frequency current ripple in the ac output
current is lowered, which can lower the losses in the ac fil-
ter inductor or an ac motor: the latter has potential benefits
in terms of increasing the motor power ratings and effi-
ciency of the machine. These features have great potential
in high-speed machine drives. The multilevel output volt-
age waveforms also places less stress on the motor wind-
ings and help to alleviate motor winding dv/dt stresses.
3) The ac filter inductor can be reduced in size and its fun-
damental voltage drop reduced: this results in more fun-
damental voltage reaching the load.
4) The switch control deadtimes can be eliminated, helping
to improve the quality of the PWM voltage generation
and increasing the maximum potential output voltage and
switching frequency.
5) The coupled inductor provides excellent protection against
dc-rail shoot-through conditions.
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John Salmon (S’86–M’86) received the B.Sc.
(Eng.) and Ph.D. degrees from Imperial College,
London, U.K., in 1982 and 1987, respectively, and
the M.Eng. degree from McGill University, Montreal,
QC, Canada, in 1984.
In 1987, he joined the Department of Electrical
and Computer Engineering, University of Alberta,
Edmonton, AB, Canada, as an Assistant Professor,
where he has been a Full Professor since 1996. He
has conducted industrially funded power electronics
research projects covering a wide range of applica-
tions, such as electronic ballasts for fluorescent lamps and metal halide HID
lamps, utility interface of microturbine generators using high-speed permanent-
magnet generators, medium-voltage industrial drive systems, and soft starters
for medium-voltage induction motors. His current research interests include
industrial drive systems and their utility interface, multipulse utility rectifiers,
pulsewidth modulation (PWM) current control techniques using analog and DSP
electronics, multilevel voltage source converters for application in variable-
speed drive systems, high-speed flywheel energy storage systems applied to
rapid transit systems and wind power generators, multifunctional PWM con-
verter topologies using multifunctional PWM control techniques, and phase-
lock loop control techniques.
Andrew M. Knight (S’95–M’99–SM’06) received
the B.A. degree in electrical and information sciences
and the Ph.D. degree in electrical power engineering
from the University of Cambridge, Cambridge, U.K.,
in 1994 and 1998, respectively.
In 1999, he joined the University of Alberta,
Edmonton, AB, Canada, as an Assistant Professor,
where he is currently an Associate Professor in the
Department of Electrical and Computer Engineering.
His current research interests include the efficient
utilization of electrical energy, including energy con-
version, storage, and transmission. He is also involved in the fields of renewable
energy and electrical machines and drives. In addition to his interest in the prac-
tical analysis and design of electrical systems, he also has carried out research
on modeling of nonlinear magnetic systems, including both finite-element and
analytical modeling techniques.
Jeffrey Ewanchuk (S’06–M’08) received the B.Sc.
degree (with distinction) in electrical engineering in
2006 from the University of Alberta, Edmonton, AB,
Canada, where he is currently working toward the
M.Sc. degree in power electronics/engineering.
His current research interests include dc/dc con-
verters, pulsewidth modulation (PWM) techniques,
power electronics in renewable energy applications,
and electric motors/drives.
Mr. Ewanchuk was a recipient of the Natural Sci-
ence and Engineering Research Council of Canada
(NSERC) Postgraduate Scholarship (PGS) M (Canadian)/Informatics Circle of
Research Excellence (ICORE) Postgraduate Scholarship (Alberta) for 2007–
2008.