EE/CE 6301: Advanced Digital Logic

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Dept. of EE
Univ. of Texas at Dallas

Session 02

Overview of HDL-for-Synthesis

2
 Fundamental Concepts

Hardware Modeling Using HDL

• HDL: Hardware Description Language - A
high level programming language used to model
hardware.

• Hardware Description Languages

— have special hardware related constructs.
— can be used to build models for simulation, synthesis and test
— have been extended to the system design level
— VHDL: VHSIC Hardware Description Language
– VHSIC – Very High Speed Integrated Circuit Program
– Mostly used in academia
— Verilog HDL
– Mostly used in commercial electronics industry

4
Concept of Synthesis
• Logic synthesis
— A program that “designs” logic from abstract descriptions of the logic
– takes constraints (e.g. size, speed)
– uses a library (e.g. 3-input gates)
— The aim of synthesis is to produce hardware which will do what the
concurrent statements specify.
– This includes processes as well as other concurrent statements.
• How?
— You write an “abstract” HDL description of the logic
— The synthesis tool provides alternative implementations
constraints

VHDL synthesis or …
Description

library 5

Goal
• We know the function we want, and can specify
in C-like form.
—… but we don’t always know the exact gates (nor
logic elements)…
—… we want the tool to figure this out…

x
tmp0
x sbar
MUX f
s f
y

y
s tmp1

6
Importance of Synthesis
• In order to map an HDL
code on a FPGA, the
code should be Synthesizable
Synthesizable
VHDL Synthesis
VHDL
synthesizable! Code
Code

— An HDL code that

functions correctly in
simulation, does not
necessarily mean it is
synthesizable.

— Once you have gone

through the synthesis
tool for your HDL code Place and
Route
without errors, your
code is synthesizable.

VHDL Statements
• Concurrent
—Signal assignment
—Instantiation
—when-else
—with-select-when
—process (as a wrapper for sequential statements)
• Sequential
—Signal assignment - ONLY statement that is
concurrent and sequential.
—if-then-elsif-else - ONLY within a process
—case-when - ONLY within a process

8
General VHDL Programming Flow
• LIBRARY and USE statements
Entity declaration:
• ENTITY entity_name IS
— Identify the input and output PORTs and their data types
• END [entity_name];

Provide design description:

• ARCHITECTURE architecture_name OF entity_name IS
— [SIGNAL declarations]
— [CONSTANT declarations]
— [TYPE declarations]
— [COMPONENT declarations]
— [ATTRIBUTE specifications]
• BEGIN
— {COMPONENT instantiation statement ;}
— {CONCURRENT ASSIGNMENT statement ;}
— {PROCESS statement ;}
— {GENERATE statement ;}
• END [architecture_name] ; 9

VHDL Syntax
• The basis of most of the VHDL is the logical
interactions between signals in the modules.
— Most of this is very intuitive, representative of logical
functions.
• Another commonly used form of syntax is the
conditional statements.
—These work very much like the conditional
statements of procedural programming that you
should be used to.
• Keywords in VHDL are not case-sensitive.
• Names that user defines are case-sensitive.
• END statements do not require name of design
entity or architecture to be followed.
10
 Introductory Example

11

Introductory Example
• 2-1 Multiplexer
x MUX f • Characteristic table:
• Truth table: y
s s f
s x y f 0 x
0 0 0 0 1 y
0 0 1 0
0 1 0 1
0 1 1 1
• Boolean Equation:
1 0 0 0
f =s⋅x+ s⋅ y
1 0 1 1
1 1 0 0
1 1 1 1
12
Introductory Example
• 2-1 Multiplexer
• Gate-level
• VHDL Code: description:
--Example 1: 2-1 Mux in VHDL x
LIBRARY IEEE;
USE IEEE.std_logic_1164.all; s f

ENTITY multiplexer2 IS y
PORT ( x, y, s : IN BIT ;
f : OUT BIT ) ;
END multiplexer2 ;
ARCHITECTURE multiplexer2_arch OF multiplexer2 IS
BEGIN
f <= (x AND NOT s) OR (y AND s) ;
END multiplexer2_arch ;
13

Introductory Example: Synopsys Synthesis

• Unoptimized circuit
— Full Schematic View in
Synopsys Design
Analyzer graphical
environment:

— Gates used from

Synopsys libraries:

14
Introductory Example: Synthesis (cont’d)
• Schematic of circuit
after compilation
and design
optimization:

• After synthesis and compilation, the tool picks different

gate configuration for the HDL code we have written

15

Testbench and Simulation

• The aim of simulation is to produce outputs (signals, integers, etc.)
from specified input signals.
— Concurrent statements are evaluated whenever any input changes.
— If the evaluation of any concurrent statement results in an input signal
change for any concurrent statement then that concurrent statement is
evaluated.
• Processes are a little different in that you must list the conditions
that initiate evaluation of the process.
— This can be done by WAIT statements or by a SENSITIVITY LIST.
• Synthesis usually ignores the sensitivity list.

• Testbench is used for generating stimulus for the entity under test.

• Different values are given to the primary input(s), output(s) are

then observed in a wave graph or textual format to test the
correctness of the design.
16
Introductory Example: Testbench
• Testbench code for 2-1 multiplexer:
--Test bench for Example 1: 2-1 Mux
library IEEE;
USE IEEE.std_logic_1164.all;
entity tbmultiplexer2 is
end tbmultiplexer2;
architecture tbmultiplexer2_arch of tbmultiplexer2 is
component multiplexer2
PORT ( x, y, s : IN BIT ;
f : OUT BIT ) ;
end component;
signal in_x, in_y, in_s, out_f: bit := '0';
begin
imultiplexer2:multiplexer2 port map(x=>in_x, y=>in_y, s=>in_s, f=>out_f);
in_x<='0', '1' after 20 ns, '0' after 40 ns, '1' after 60 ns;
in_y<='0', '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns,
'1' after 50 ns, '0' after 60 ns, '1' after 70 ns;
in_s<='0', '1' after 40 ns;
end tbmultiplexer2_arch;
configuration cf_multiplexer2 of tbmultiplexer2 is
for tbmultiplexer2_arch
for imultiplexer2:multiplexer2
use entity WORK.multiplexer2 (multiplexer2_arch);
end for;

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end for;
end cf_multiplexer2;

Introductory Example: Simulation

• Simulation Waveforms for 2-1 Mux
— Scirocco Virsim Waveform Graph from Synopsys is invoked:

• IN_S is the select line.

• IN_X and IN_Y are the inputs.
• OUT_F is the output -> Correct functionality achieved 18
 Dataflow Modeling

19

Dataflow Modeling
• In Dataflow style of modeling, the internal
working of an entity can be implemented using
concurrent signal assignment.
• VHDL code Example: • Schematics after
--Example: 2-1 Mux Dataflow Modeling in VHDL Synthesis:
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY multiplexer2 IS
PORT ( x, y, s : IN BIT ;
f : OUT BIT ) ;
END multiplexer2 ;
ARCHITECTURE multiplexer2_arch OF multiplexer2 IS
BEGIN
f <= (x AND NOT s) OR (y AND s) ;
END multiplexer2_arch ;

20
 Behavioral Modeling

21

Behavioral Description
• In Behavioral design, we specify the behavior of
the circuit, and do not necessarily know the
gate level implementation.

• The internal working of an entity can be

implemented using a set of statements

• Synthesis takes care of implementing the circuit

in gate level

• May or may not produce the most optimized

circuit after synthesis
22
Example 2: Behavioral 2-1 Mux
• VHDL Code: --Example 2: Mux2 Behavioral VHDL code
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity behmux2 is

port ( x, y, s : in std_logic ;

f : out std_logic ) ;
end behmux2;

architecture behmux2_arch of behmux2 is

begin
with s select
f <= x when '0',
y when '1',
'0' when others;
end behmux2_arch;

• Behavior of 2-1 MUX is written using “with-

select-when” statement in VHDL . 23

Example 2: Synthesis and Simulation

• Synopsys Synthesis
—Schematics before and after compilation:

• Wave graph simulation:

24
 Structural Modeling

25

Structural Description
• Structural design forces the tool to use certain
gates with specified connections for synthesis.
• Gate level structure should be known. Example:

x
tmp1
sbar

s f

y
tmp2

• Components and port mapping is used.

• Structure of the circuit would not alter after
synthesis.
26
 Structural Modeling
• The implementation of an entity is done through a set
of interconnected components
• Contains:
— Signal declaration
— Component instances
— Port maps
— May contain wait statements (for simulation)
• Before instantiating the component it should be
declared using component declaration.
• Component declaration declares the name of the entity
and interface of a component.
• By structural modeling, we can force synthesizer to
synthesize an exact gate-level structure with no
optimization.
27

Example 3: Structural 2-1 Mux

• VHDL Code:
--Example 3: Structural 2-1 Mux
LIBRARY IEEE; --------------------------------------
USE IEEE.std_logic_1164.all; LIBRARY IEEE;
USE IEEE.std_logic_components.all; USE IEEE.std_logic_1164.all;
-------------------------------------- USE IEEE.std_logic_components.all; port ( A, B : in std_logic;
entity and2 is entity not1 is Z : out std_logic);
port ( A, B : in std_logic; end component;
port ( A : in std_logic;
Z : out std_logic); component or2
Z : out std_logic); port ( A, B : in std_logic;
end and2; end not1; Z : out std_logic);
architecture beh_and2 of and2 is architecture beh_not1 of not1 is end component;
begin -- beh_and2 begin -- beh_not1 component not1
Z <= A and B; port ( A : in std_logic;
Z <= not A;
end beh_and2; Z : out std_logic);
end beh_not1; end component;
-------------------------------------- --------------------------------------
LIBRARY IEEE; --TOP LEVEL MODULE SIGNAL tmp1, tmp2, sbar: std_logic;
USE IEEE.std_logic_1164.all; LIBRARY IEEE; BEGIN
USE IEEE.std_logic_components.all; S_1 : not1 port map( A => s, Z =>
USE IEEE.std_logic_1164.all;
entity or2 is sbar);
USE IEEE.std_logic_components.all; S_2 : and2 port map( A => x, B =>
port ( A, B : in std_logic; ENTITY strucmux2 IS sbar, Z => tmp1);
Z : out std_logic); PORT ( x, y, s : IN std_logic ; S_3 : and2 port map( A => y, B => s,
end or2; f : OUT std_logic ) ; Z => tmp2);
architecture beh_or2 of or2 is S_4 : or2 port map( A => tmp1, B =>
END strucmux2;
begin -- beh_or2 tmp2, Z => f);
ARCHITECTURE strucmux2_arch OF END;
Z <= A or B; strucmux2 IS
end beh_or2; component and2

28
Example 3: Synthesis
• Schematics after synthesis and compilation:

tmp1

sbar

tmp2

• Gate level-structure after synthesis remains just

as we specified
—Useful for test (DFT) purposes for specified circuits.
29

Don’t-Cares in VHDL

30
 Don’t-Cares in VHDL
• In logic synthesis and logic simulation, a don't-care is one
of the values in a multi-valued logic system that denotes an
unknown value, or a value that the designer (for whatever
reason) does not care about.
• A don’t-care or X value does not exist in hardware. In
simulation, an X value can result from two or more sources
driving a signal simultaneously, or the stable output of a flip-
flop not having been reached.
• In synthesized hardware, however, the actual value of such a
signal will be either 0 or 1, but will not be determinable from
the circuit's inputs.
• Synthesis tools can use don't-care values to determine where
and how to perform area optimization. For example, a
synthesis tool can use don't-care values to reduce the
number of states and circuit size of finite state machines.
31

Example 4: Don’t-Cares in VHDL

• Don’t-care in digital design denotes a value could be either 0 or 1.
• Don’t-cares are specified with ‘-’ in VHDL.
• Suppose f is a function of minterms of a, b, c, and d such that:

f (a, b, c, d ) = ∑ m(1,4,5,7,13) + d (3,6)

• Example 4 VHDL Code:

--Example 4: VHDL code including don't-cares q <= a & b & c & d; --concatenating to produce abcd
library ieee; with q select
use ieee.std_logic_1164.all; f<='1' when "0001" | "0100" | "0101" | "0111" | "1101",
use ieee.numeric_std.all; '-' when "0011" | "0110",
use ieee.std_logic_unsigned.all; '0' when others;
use ieee.std_logic_arith.all; end archf;
entity func is
port (
a,b,c,d: in std_logic;
f: out std_logic);
end func;
architecture archf of func is
signal q:std_logic_vector(3 downto 0);
begin

32
Example 4: Synthesis
• f is a function of a, b, c, and d:

• After synthesis and design optimization:

33

Don’t-Cares in VHDL
• When CASE or IF statements do not cover all
possible input conditions unwanted latches
may be generated to hold the output.
—Conditions that are not covered does not mean that
they are don’t-cares!

• Including the final ELSE clause or WHEN

OTHERS clause in an IF or CASE statement
can prevent this unwanted latch from being
generated.

34
 Don’t-Cares in VHDL (cont’d)
• Example 4.1: 3-1 MUX with all conditions covered in
case-when statement using when-others:
--Example 4.1: 3-1 MUX with all conditions covered
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_components.all; MUX
entity mux3r is
port ( A, B, C: in std_logic;
sel: in std_logic_vector(1 downto 0);
Z : out std_logic);
end mux3r;
ARCHITECTURE mux3r_arch OF mux3r IS
BEGIN
pMux : process (A,B,C,sel)
begin No Latch generated in Synthesis
case sel is
when "00" => Z <= A;
when "01" => Z <= B;
when others => Z <= C;
end case;
end process pMux;
END; 35

Don’t-Cares in VHDL (cont’d)

• Example 4.2: 3-1 MUX when all conditions are not
covered in case-when statement:
--Example 4.2: 3-1MUX when all conditions are not covered
LIBRARY IEEE;
USE IEEE.std_logic_1164.all; Latch Inferred!
USE IEEE.std_logic_components.all;
entity mux3w is
port ( A, B, C: in std_logic;
sel: in std_logic_vector(1 downto 0);
Z : out std_logic);
end mux3w;
ARCHITECTURE mux3w_arch OF mux3w IS
BEGIN
pMux : process (A,B,C,sel)
begin
case sel is
when "00" => Z <= A;
when "01" => Z <= B;
when "10" => Z <= C;
when others => NULL;
end case;
end process pMux;
END;
36
 Synthesizer Analysis Report

37

Metrics Often Reported

• The three main metrics of the synthesized design
(and other metrics) can be reported by the tool.
• Depending on which library Synopsys tool uses
(class, gtech, etc.), design metric values would
differ.
• Total combinational area is reported in terms of
equivalent 2-input NAND gates
• Non-combinational area would be non-zero for
sequential designs containing flip-flops.
• Total dynamic power can be reported by the tool.
• Timing characteristics can be reported, and the
values are given with respect to rising (r) and falling
(f) times in nanoseconds. 38
 Area Report (2-Input MUX Example)

****************************************
Report : area
Design : behmux2
Version: V-2003.12
Date : Sun Jan 11 03:36:57 2009
****************************************
Library(s) Used:
class (File: /home/cad/synopsys-2003/syn/libraries/syn/class.db)
Number of ports: 4
Number of nets: 5
Number of cells: 2
Number of references: 2
Combinational area: 4.000000
Noncombinational area: 0.000000
Net Interconnect area: undefined (Wire load has zero net area)
Total cell area: 4.000000
Total area: undefined
1
design_analyzer>
****************************************

39

Power Report
****************************************
Report : power
-analysis_effort low
Design : behmux2
Version: V-2003.12
Date : Sun Jan 11 03:36:57 2009
****************************************
Library(s) Used:
class (File: /home/cad/synopsys-2003/syn/libraries/syn/class.db)
Warning: The library cells used by your design are not characterized for internal power. (PWR-26)
Operating Conditions:
Wire Load Model Mode: top
Design Wire Load Model Library
------------------------------------------------
behmux2 05x05 class
Global Operating Voltage = 5
Power-specific unit information :
Voltage Units = 1V
Capacitance Units = 0.100000ff
Time Units = 1ns
Dynamic Power Units = 100nW (derived from V,C,T units)
Leakage Power Units = Unitless
Cell Internal Power = 0.0000 nW (0%)
Net Switching Power = 4.5201 uW (100%)
---------
Total Dynamic Power = 4.5201 uW (100%)
Cell Leakage Power = 0.0000
design_analyzer> 40
****************************************
Timing Report
Report : timing
-path full
-delay max
-max_paths 1
Design : behmux2
Version: V-2003.12
Date : Sun Jan 11 03:36:57 2009
****************************************
Operating Conditions:
Wire Load Model Mode: top
Startpoint: x (input port)
Endpoint: f (output port)
Path Group: (none)
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
behmux2 05x05 class
Point Incr Path
-----------------------------------------------------------
input external delay 0.00 0.00 f
x (in) 0.00 0.00 f
U13/Z (IV) 0.58 0.58 r
U12/Z (EON1) 0.90 1.48 f
f (out) 0.00 1.48 f
data arrival time 1.48
-----------------------------------------------------------
(Path is unconstrained) 41
design_analyzer>

Report (cont’d)
• Report of Area, Power and Timing:
(Path is unconstrained)
1
design_analyzer>
****************************************
Report : area
Design : behmux2
Version: V-2003.12
Date : Sun Jan 11 03:37:01 2009
****************************************
Library(s) Used:
class (File: /home/cad/synopsys-2003/syn/libraries/syn/class.db)
Number of ports: 4
Number of nets: 5
Number of cells: 2
Number of references: 2
Combinational area: 4.000000
Noncombinational area: 0.000000
Net Interconnect area: undefined (Wire load has zero net area)
Total cell area: 4.000000
Total area: undefined
1
design_analyzer>
****************************************

42
Report (cont’d)
• Report of Area, Power and Timing:
Report : power
-analysis_effort low
Design : behmux2
Version: V-2003.12
Date : Sun Jan 11 03:37:01 2009
****************************************
Library(s) Used:
class (File: /home/cad/synopsys-2003/syn/libraries/syn/class.db)
Warning: The library cells used by your design are not characterized for internal power. (PWR-
26)
Operating Conditions:
Wire Load Model Mode: top
Design Wire Load Model Library
------------------------------------------------
behmux2 05x05 class
Global Operating Voltage = 5
Power-specific unit information :
Voltage Units = 1V
Capacitance Units = 0.100000ff
Time Units = 1ns
Dynamic Power Units = 100nW (derived from V,C,T units)
Leakage Power Units = Unitless
Cell Internal Power = 0.0000 nW (0%)
Net Switching Power = 4.5201 uW (100%)
---------
Total Dynamic Power = 4.5201 uW (100%)
43

Report (cont’d)
• Report of Area, Power and Timing:
Cell Leakage Power = 0.0000 input external delay
1 0.00 0.00 f
design_analyzer> x (in)
**************************************** 0.00 0.00 f
Report : timing U13/Z (IV)
0.58 0.58 r
-path full
U12/Z (EON1)
-delay max 0.90 1.48 f
-max_paths 1 f (out)
Design : behmux2 0.00 1.48 f
Version: V-2003.12 data arrival time
Date : Sun Jan 11 03:37:01 2009 1.48
**************************************** ------------------------------------------
Operating Conditions: -----------------
Wire Load Model Mode: top (Path is unconstrained)
Startpoint: x (input port) 1
Endpoint: f (output port) design_analyzer>
Path Group: (none)
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
behmux2 05x05 class
Point Incr Path
-----------------------------------------------------------

44