It’s a Mixed-Bag of New/Interesting Ideas

Emerging ADCs Which will emerge

g
(New/interesting ideas for ADC design) as the winner?
This tutorial

Presentation at Columbia University – NYC Taste of a

variety
September
p 17, 2010

Un-Ku Moon
Oregon State University Emerging
Electrical Engineering and Computer Science
ADCs
Still brewing…
U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 2

What Motivates These Emerging Ideas? Today’s Presentation

CMOS Scaling Š Let me summarize/present, and let us ponder

ƒ Analog switches difficult to operate
ƒ High gain opamps difficult to build
ƒ Noise immunity worsens with increasing
integration and smaller signal swing
ƒ Minimum size device matching degrades with
device scaling
ƒ Add your favorite problem/challenge here
And general others… such as future and
emerging
g g markets/applications, etc.
Š We will look at
ƒ Selective/popular emerging ADCs
ƒ Random slices of emerging ADCs
Š We won’t make any serious value judgment
ƒ But we can argue about it ::-))
ƒ Ultimately future will make that judgment
Š Primarily
y to p
provide exposure
p to various ideas
ƒ For you to take home and digest/improve/innovate
ƒ For you to critique, filter, ridicule…

U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 3 U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 4
 Presentation Content First Things First
ƒ Zero-crossing detector (comparator) based ADC I would like to acknowledge and thank my
ƒ VCO (noise-shaping quantizer) based ADC colleagues and graduate students who provided
ƒ Continuous-time input pipelined ADC much of the following material
ƒ Correlated level shifting (CLS) based ADC
Dr Rob Gregoire
Dr. Hoyoung Lee
ƒ Stochastic (mostly digital) ADC Dr. David Gubbins Dr. Nima Maghari
ƒ Asynchronous SAR ADC Ben Hershberg Dr. Tawfiq Musah
Yue Hu Dr. Skyler Weaver
Perhaps your favorite is missing…

U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 5 U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 6

Comparator-Based SC (CBSC) Circuits

Zero--Crossing Detector (Comparator) Based ADC

Zero

Sepke et al. ISSCC 2006 & JSSC Dec-2006

Brooks et al. ISSCC 2007 & JSSC Dec-2006
Shin et al. VLSI 2008
Brooks et al. ISSCC 2009
Chu et al. VLSI 2010
Š Opamp is replaced with a comparator and a switched
Huang et al. TCAS2 May-2009 current source
Musah et al. CICC 2009 Š High gain comparator can be designed as a cascade of
several stages since it has no stability constraint
Š Minimum
Mi i comparator
t delay
d l ensures marginal
i l overshoot
h t

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 Comparator-Based Pipelined ADC Zero-Crossing-Based Circuits (ZCBC)
Sepke et al. ISSCC 2006 Brooks et al. ISSCC 2007

Φ2 Q Φ2 Φ2
CF CF
Φpcb I1 I2
VIN Φ1 Q1 I1 VIN Φ1 Φ2
Φ2 Q
CS VX CS VX
VO CL
Φ1 ΦPC Φ1
VO
Φpc
Φ2 Φ1 Φ2 Φ2 Φ1
Q2 ΦPC
Φ2 Φ2 CL
VCM
I2 Q1 Φpc Φpcb
DVRP VCM DVRP VCM ZCD
Q Q2 Q VX

VCM
VX VCM
VO

Š First/proof-of-concept
Fi t/ f f t realization
li ti off the
th CBSC Š Comparator
C t replaced
l d with
ith simple
i l zero-crossing
i detector
d t t (ZCD)
Š Comparator is a cascade of several gain stages Š Currents split to minimize switch nonlinearities
Š A fine charging phase minimizes overshoot Š 8bit ((6.4 ENOB)) 200MS/s p
pipelined
p ADC in 0.18µm
µ CMOS
Š 10bit (52dB SNDR) 8MS/s pipelined ADC in 0.18µm
U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 9 U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 10

Fully Differential ZCBC with CMFB Fully Differential ZCBC – No CMFB

I1
Shin et al. VLSI 2008 Φ2
I1 I2 Brooks et al. ISSCC 2009
Φ1
Φ1 Φ2
CF
Φ2
CF VOP
I2 VOP VINP Φ1
VINP CS VXP Φ2
Φ1
CS VXP Φ2 Φ2
Φ2 Φ1 ΦPC CL
CL ΦPC
Φ1 ΦPC Φ2 Φ1
ΦPC
Φ2 Φ1 ΦPC DVRP Q
Q1
DVRP ZCD DVRN
VCM ZCD VCM
VCM OCC + VCM QA
DVRN Φ2 Φ1
logic QA ΦPC
Φ2 Φ1 Q2 ΦPC CL
ΦPC Φ1
Φ2 VXN
CS VXN
Φ1
Φ2 CL QB
CS VXN VINN
VON
Φ1
VINN I2 CF VXP
VON Φ2
Φ1
CF
VXN
Φ2
Φ2
Also see…
I1 I2
VOP Li et al. JSSC Sep-2004
CMFB VXP
VON Ahmed et al. ISSCC 2009
Š Output differentially sampled (floating switch) – No CMFB
Š ZCD cascade of two differential pairs and an inverter Š ZCDs digitally trimmed (background) to remove overshoot
Š CMFB and overshoot correction improves accuracy Š Replica/dummy current sources for matching and noise rejection
Š 10bit 26MS/s pipelined ADC in 65nm CMOS Š 12bit (62dB SNDR) 50MS/s pipelined ADC in 90nm CMOS
U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 11 U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 12
 FOM of These Pipelined ADCs Improving Fully Differential CBSC Integrator (∆Σ)
VRN VRP
Q1 I1 Huang et al. TCAS2 May-2009
CF
Φ2 Φ2
FOM = P/(fs*2ENOB) Φ1

Q2 I2 VOP
VINP CS
Φ2
Φ1 Φ2 Φ2
CL
ΦPC
Φ1 Φ2
ΦPC
VXP VRN
VCM VCM
VRP Q1
Φ1 VXN Φ2
ΦPC
Φ1 Φ2 Φ2 CL Q2
Chu et al.
VLSI 2010 VINN CS
Q2 I2 VON
VXN
(100 MS/s)
Φ2 Φ2
53-80 fJ/step VRP VRN
CF Q1
VXP

X
Š Coarse/fine charging with CMFB (not shown)
Š Comparator realized as self-biased
self biased differential amplifier
Š Second-order 2-level DSM in 0.18µm CMOS
U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 13 U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 14

Fully Differential ZCBC Integrator (∆Σ)

Musah et al. CICC 2009 VCO (Noise-
(Noise-Shaping Quantizer)
Quantizer) Based ADC

Hovin
H i ett al.
l JSSC Jan-1997
J 1997
Iwata et al. ISCAS 1998 & TCAS2 Jul-1999
Wismar et al al. ESSCIRC 2006
Kim et al. ISCAS 2006
Straayer et al. VLSI 2007 & JSSC Apr-2008
Apr 2008
Straayer et al. VLSI 2008 & JSSC Apr-2009
Park et al. ISSCC 2009
CBSC/ZCBC integrator:
More issues… Maghari et al. EL Jun-4-2009
Š Use of resistor current sources eliminates need for CMFB
Š New charging scheme reduces some errors & maximizes swing
Š Second-order 2-level DSM in 45nm digital CMOS
U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 15 U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 16
 Time Domain Signal Processing VCO Based ADC Resolution

Sampling period Number

of
rising edges

fmax 8 f max f
resolution = log 2 ( − min )
f sample f sample
1LSB(2π)
KVCO ⋅ Vtuningrange
= log 2 ( )
f sample

fmin 2
The proponents make
1LSB(2π)
the case that time
domain signal resolution
Issues:
is independent
p of supply
pp y
ƒ Need wide/linear VCO tuning range for high resolution ADC
scaling and more robust
ƒ VCO based ADC linearity limited by nonlinear voltage-to-
to voltage noise
frequency conversion

U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 17 U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 18

VCO as Voltage-to-Frequency/Phase Conversion Noise-Shaping VCO Quantizer Based “DSM”

P[ n] = KVCO ⋅ TS ⋅ X [ n] − e[ n − 1] Hovin et al. JSSC Jan-1997
Wismar et al. ESSCIRC 2006
Y [ n ] = P[ n ] + e[ n] Kim et al. ISCAS 2006
1
= {K VCO ⋅ TS ⋅ X [ n] − e[ n − 1] + e[ n ]}
2π

1
Y [ z] = {KVCO ⋅ TS ⋅ X [ z ] + (1 − z −1 ) E[ z ]}
2π

NTF = (1 − z −1 )

ƒ Quantization = Edge counting

ƒ Inherent first-order noise shaping
ƒ VCO as continuous
ti signal
i l integrator
i t t
ƒ VCO input spans entire input range
Hovin et al. JSSC Jan-1997
Iwata et al. ISCAS 1998 & TCAS2 Jul-1999 VCO nonlinearity and phase noise unfiltered

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 VCO-Based Delta-Sigma (Higher Order) ADC Linear Voltage-to-Phase Quantization
Park et al. ISSCC 2009
Iwata et al. ISCAS 1998 & TCAS2 Jul-1999
Straayer et al. VLSI 2007 & JSSC Apr-2008

ƒ High gain filter placed before VCO

ƒ VCO input span attenuated Š PHASE instead of frequency is quantized and fed back via
DAC equivalent (this is just the quantizer portion of DSM)
ƒ VCO nonlinearity and phase noise filtered
(largely improved but still nonlinear) ƒ leverages infinite gain of VCO as a phase integrator
ƒ Nonlinearity of VCO quantizer eliminated
Also see: Straayer et al
al. VLSI 2008 & JSSC Apr-2009
Apr 2009
Gated ring oscillator (GRO) based time-to-digital converter (TDC) Š Higher order filter (∆Σ) for further noise shaping
U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 21 U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 22

Dual Slope Based Noise-Shaping Quantizer

C Maghari et al. EL Jun-4-2009

ϕ1 R
Vout Š Quantization error…
error
X
ϕ2 ƒ Stored on integrating
cap (not reset)
Continuous--Time Input Pipelined ADC
Continuous
VD
ƒ Effectively added to
the new input sample Gubbins et al.
Vout ϕ1 ϕ2 ϕ1 CICC 2008, CICC 2009, JSSC-2010
Æ First-order
noise-shaping
t (like the VCO)
Dout
LSB - e(n)
This opens paths to
t many possibilities…
Traditional Proposed
Stop Discharge Stop Discharge

U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 23 U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 24
 Problem Statement Conceptual Front-end Sampler
Š Interfacing to high performance ADC is not trivial
ƒ Many application notes written
ƒ Incorrect external circuitry leads to poor ADC results
Š Typical application circuit

Gray, Smith, EDN May 1998

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Continuous-Time Input Prediction Filter

Zeros and poles:
Goal of equiripple magnitude and linear phase lead

Gubbins et al. CICC 2008

Š Prediction block and sub-ADC

ƒ Eased accuracy requirements
ƒ Analog filter requires tweaking/calibration
ƒ Idac has half a period to settle like S/C MDAC

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 Filter Frequency Response Windowed Continuous-Time Input
• Prediction filter provides T/2 phase lead Gubbins et al. CICC 2009
– Filter does not affect ADC frequency response

Window = SINC filtering

Anti alias filter merged into first stage
Anti-alias
Residue is windowed and sampled into second stage
U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 29 U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 30

Measured ADC Frequency Response Improved Jitter Performance (Simulation)

SNR vs. Input Frequency (Spectre 13b ADC model)
84

Fs=26MHz 79
SNR(impulse sampling)
-14dB -40dB/dec
40dB/dec SNR(window sampling)
74 SNR(window residue sampling)

SNR [dB]
ADC 69
Gain
64
(dBs)
59

54
0 2 4 6 8 10 12 14
Input Frequency [MHz]

~3dB improvement at Nyquist (12.5MHz)

Input Signal Frequency (MHz)
U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 31
ƒ Jitter affects input
p signal
g and reference ((i.e. correlated))
ƒ Low frequency number depends on first stage resolution
U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 32
 Low Voltage Issues
0.9V
0.15V

0.6V
Correlated Level Shifting (CLS) Based ADC Bias
“useful”
range

Gregoire et al. ISSCC 2008 & JSSC Dec-2008 0.15V

Hershberg et al. ISSCC 2010 & JSSC Dec-2010 0.0V

Š Limited “useful” range

Š Low and nonlinear g
gain – hard to digitally
g y calibrate
Š Process scaling will not increase headroom
Š 1/3 supply unusable (in this example)
Š 2.25x
2 25 capacitance
it ((power)) ffor same SNR

U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 33 U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 34

CLS Closed-Loop Performance CLS Step 1

Sample input 1
0.9V
2

3
LS
Bias Out
OP OUT
IN

OP

0.0V

=1/2
IN IN
IN IN
OUT
Š 30dB opamp: ~5 bits, small swing
Š CLS: > 10 bits,
bits large swing 0 0

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 CLS Step 2 CLS Step 3
Flip around, sample output Level shift

2VIN
1 + A/2

2VIN 2VIN 2VIN

1+
1 + A/2 1+
1 + A/2 (1+
1 + A/2 )2

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CLS ≠ CDS (Approach) CLS ≠ CDS (Open-Loop)

ƒ CLS LS
CLS
ƒ Subtracts signal 36dB ƒ (gain)·(best gain+)
ƒ Opamp processes
error CDS
ƒ (gain)2

Š CDS
Best
Gain
30 dB opamp
DS
ƒ (gain)
ƒ Subtracts error
ƒ Opamp
O processes
signal

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 Testing (Beyond) Rail-to-Rail Measured ENOB

VDD =0.9V
VREF=1.0V
Fs=20MHz
Fin=1, 10MHz
6.2mW (analog)
( g)

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Split-CLS Advantage
Hershberg et al. ISSCC 2010 & JSSC Dec-2010

ФA Vo VDD = 1V
ФS 150mV
Ф1 CCLS
Vx
Vi 450mV
A1 Stochastic ADC
ФA
1V 600mV
100 V
100mV (Mostly Digital and Hopefully Synthesizable ADC)
(+/-Vr,0) A2
Ф2 Ф1
ФS 450mV
Weaver et al. ASSCC 2008 & TCAS1 2010
VCMI 150mV
VCMO

Š Aeff = A1·A2 1 2
Š High gain using simple opamps, 20dB + 60dB
even in deep submicron (80dB)

A1 – use zero-crossing detector (ZCD)

11+ ENOB results
A2 – use low-swing high-gain opamp

U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 43 U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 44
 Fundamental Observation
Š Comparator offset defines flash ADC
Š Offset is random
Š Individual offsets are unknown
Š Offset distribution can be known
System Level Consideration: A Closer Look
Š Apply ramp to comparators with random offsets
Š Shift in reference shifts transfer function
Š Two Gaussian CDFs spaced 2σ sum to a line
512
384

utput
256

Ou
Σ
128
0
-3 -2 -1 0 1 2 3 1024
Input (σ)

768

Output
–1σ
Input-referred offset
x512
Σ 512
ensity

0.4 ramp input 256

Σ
Probability De

0.3 512

0.2 384 0
-3 -2 -1 0 1 2 3

Output
256
0.1 128 Input (σ)
0 +1σ x512 0
P

-3 -2 -1 0 1 2 3 -3 -2 -1 0 1 2 3
Input (σ)
Comparator Offset σ
()

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2.4mm x 2.4mm in 0.18µm CMOS Measurement Results

0.75 1500
Area

Power ( μW)
Area (m m )
2
0.5 1000

0.25 500
Power
0 0
384 768 1152 1536 1920
Comparators

6
5.5
NOB

5
EN

Nonlinearity reduction
4.5
Gaussian lookup table
4
384 768 1152 1536 1920
Comparators
192 x 20 x 2 = 7680 comparators
U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 47 U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 48
 Can We Fully Synthesize ADC? This Just Might Work…

Add digital-like analog blocks to digital library Entire ADC described in verilog/VHDL
ƒ Match supply
pp y pitch
p and library
y rules
ƒ Generate other files required by synthesis tool

module adc_block(in,out);
input in;
reg out;

endmodule

ADC Layout
verilog/VHDL
Desired synthesis
La o t LEF,
Layout, LEF Verilog,
Verilog etc
etc.
analog
block

Digital library
U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 49 U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 50

Conventional SAR Architecture

QM

QS
Asynchronous SAR ADC Dn-1

Ch ett al.
Chen l ISSCC 2006 Dn-2

D0
Yang et al. CICC 2009 & JSSC 2010
C.C. Liu et al. Š Binary search algorithm
N clock per N-b

VLSI 2009 & JSSC 2010, ISSCC 2010, VLSI 2010 ƒ Reduces both circuit complexity and power consumption
Š Charge redistribution for high accuracy
Š Relatively low speed operation
ƒ N clock periods needed for N-bit conversion
ƒ Power
Po er cons
consumed
med in high speed clock generator

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 Asynchronous Clocking Metastability in Asynchronous SAR
Chen et al. ISSCC 2006 Yang et al. CICC 2009 & JSSC 2010
DO
Š Generate metastability information for each
Vin Vx
VREF
Capacitor
Network
SAR conversion
ƒ e.g. Look at how many cycles are completed for each
Async.
Async
QS CLK conversion
i (less
(l the
th full
f ll countt = metastability)
t t bilit )

Async Clock
Š When metastability occurs
Generator Async. ƒ Fill remaining
g bits with the opposite
pp polarity
p y of the last
CLK
resolved bit (all were reset to zero before conversion)
ƒ In other words, replace the unresolved bits (including
Next clock is generated from previous latch output
the metastabilityy one)) with “10…0” or “01…1”
ƒ No need for high-speed synchronous clock generator
ƒ Could minimize clock timing margin
This is my interpretation of Yang’s presentation
ƒ Delay decreased with submicron scaling
Contact the author for clarification!
Æ Low noise and low power…
U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 53 U. Moon ƒ Oregon State University ƒ Emerging ADCs Page 54

Record Setting (FOM) Asynchronous SARs Concluding Comments

C.C. Liu et al. VLSI 2009 & JSSC 2010
Vref

10 bit 50 MSPS in 0.13μm

Š Well… this is your favorite/LAST slide!
Clk_in
C1 C2 C3 C4 C5 C6 C7 C8 C9
Energy
gy efficient
Vip 10 asymmetric switching to Š What looks most promising to you?
SAR Dout
Vin yield 52 fJ/cs FOM ƒ Comparator/zero-crossing based circuits
Bootstrapped
Switch C1 C2 C3 C4 C5 C6 C7 C8 C9
ƒ VCO-based/noise-shaping quantizers
Cunit=10fF, Ci=2Ci+1, i=1~8
Vref
ƒ Correlated Level Shifting (CLS)
ƒ Continuous-time input pipeline
C.C. Liu et al. ISSCC 2010
10
0 bit
b t 100
00 MSPS
S S in 90
90nm
ƒ Something else?...
else? all passive architectures,
architectures SAR varieties
varieties,
15.5 fJ/cs FOM with
dynamic source follower, etc.
added redundancy

Š Maybe none of the above... still brewing!

Emerging
ADCs

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