Virtual Memory

II

CSCI-0310
Pascal Van Hentenryck

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 Physical Memory
page 0

page 1

page 2

page 3

page 4

…………..

page 220-1

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 Address Space
virtual page 0

virtual page 1

virtual page 2

virtual page 3

virtual page 4

……………...

virtual page 252-1

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 Address Space
Where is the address space stored?
•  On a disk which is large and slow

The disk!

We do not want to use the disk for

memory accesses
•  it would be way to slow

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 Address Translation

63 62 … 12 11 … 0

virtual page number offset

Translate

31 … 12 11 … 0

physical page offset

number

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 Physical Memory
page 0 (4K) vpn LRU Dirty

page 1 (4K) vpn LRU Dirty

page 2 (4K) vpn LRU Dirty

page 3 (4K) vpn LRU Dirty

page 4 (4K) vpn LRU Dirty

…
…………..

page 220-1 (4K) vpn LRU Dirty

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 Address Translation

63 62 … 12 11 … 0

virtual page number offset

Translate

31 … 12 11 … 0

physical page offset

number

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 Address Translation

How do we do the translation?

  find out whether a virtual page is in
memory or not
  linear in the number of physical pages

How many physical pages?

  220
  Should we care?

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 Address Translation

Page table
  Keep track of where the virtual pages
are (in memory or on the disk)
  for each virtual page number, keep
whether it is on the disk or in memory
and where

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 Page Table

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 Translation

The page table contains mapping

from virtual to physical pages.
  physical pages can be in RAM (bit 1)
  or on disk (bit 0)

How many entries in the page table?

  as many as there are virtual pages

The page table is like

  a fully associative cache to retrieve
the physical page number from the
virtual page number

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 Mapping Virtual to Physical
63 62 … 12 11 … 0
52 bits

valid physical page number

…
12 bits

Page 20 bits
Table

31 30 … 12 11 … 0

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 Translation

The page table contains mapping

from virtual to physical pages.
  physical pages can be in RAM (bit 1)
  or on disk (bit 0)

How many entries in the page table?

  as many as there are virtual pages

The hardware has a special page

table register that contains the
address of the current page table.

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Mapping Virtual to Physical
PTR 63 62 … 12 11 … 0

valid physical page number

…
Page
Table
12
bits

20 bits

31 30 … 12 11 … 0

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 Reading/writing
What happens on a read?
  Find out if the page is in
memory by accessing the page
table
  If the bit is valid, the page table
has the physical address (hit)
 Otherwise, page fault. Bring the
page to the RAM (swap in) and
update the page table
What happens on “swap out”

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 Reading/writing
What happens on a read?
  Find out if the page is in
memory by accessing the page
table
  If the bit is valid, the page table
has the physical address (hit)
 Otherwise, page fault. Bring the
page to the RAM (swap in) and
update the page table
What happens on “swap out”
  update the page table to be
invalid
  how can we do this?

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 Physical Memory
page 0 (4K) VPN LRU Dirty

page 1 (4K) VPN LRU Dirty

page 2 (4K) VPN LRU Dirty

page 3 (4K) VPN LRU Dirty

page 4 (4K) VPN LRU Dirty

…
…………..

page 220-1 (4K) VPN LRU Dirty

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 Speeding Up
The virtual-to-physical address
mapping currently requires (at least)
one extra memory reference.
  The program must access the page
tables before trying to access the
physical address
 This will double the time to service
memory requests.
 It is even worse if the value is in the
cache

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 Speeding Up
The virtual-to-physical address mapping
currently requires (at least) one extra
memory references.

The solution?
 another “cache”
The translation-lookaside buffer (TLB) is a
special cache for storing translation of
virtual to physical address

When you need to translate an address:

 if it’s in the TLB, you know the physical
page number right away
 if it’s not in the TLB, access the page
table and update the TLB with the
mapping
  special locality again

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 Speeding Up
63 62 … 12 11 … 0

TLB valid tag physical address

31 30 … 12 11 … 0

cache valid HO-bits data

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 Speeding Up

Technicalities in presence of a cache

•  where do you think that we should
store the LRU information?

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 Reading Time Again

How to read a location?

 Access the TLB to find the physical
address
 If miss, access the page table and
update the TLB
 [We now have the physical address]
 Access the cache
 if hit, we have the data
 if miss, access the RAM and update
the cache

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 Reading Time

What happens with the LRU bits

when we have a TLB miss?
•  they must be copied to memory

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 Page Table
With a 64-bit address space and 4K
pages, the page table takes about
8,000,000 megabytes
•  offset: 12 bits
•  virtual page: 52 bits
•  how many virtual pages?
252
•  what do we store per page?
> 2 words

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 Page Table
With a 64-bit address space and 4K
pages, the page table takes about
8,000,000 megabytes
•  offset: 12 bits
•  virtual page: 52 bits
•  how many virtual pages?
252
•  what do we store per page?
> 2 words
What are we going to do?
•  segmented paging
•  inverted page table

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 Segmented Paging

26 26

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 Segmented Paging

Segments
•  Entries point to page tables
Page tables
•  Entries point to pages
Features
•  Segment table is much smaller
•  Keep the segment page in memory
Still not enough (?)
•  Add one more level
Main drawback
•  How many memory accesses?

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 Inverted Page Table

A fancy name for hashing

•  the page table is simply a hashtable
•  The virtual address is hashed to get
an entry in a table which gives access
to the physical location of the pages
•  used on IBM Risc machines and
PowerPc

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 Reading Time Again

How to read a location?

 Access the TLB to find the physical
address
 If miss, access the page table
  if the page is in memory, the page

table has its entry.

  Otherwise, page fault. Page it in

and update the page

  and update the TLB

 [We now have the physical address]

 Access the cache
 if hit, we have the data
 if miss, access the RAM and update
the cache
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 Disks

The page table does not store the

address on the disk
•  What does it store?
The disk has also a translation
•  Between virtual addresses and disk
pages
•  There is one big difference of course
Wants more information
•  Take CS-167/169

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