Practical Aspects of Using PowerMOS

Transistors to Drive Inductive Loads

Application Note October 1999 AN-7517

Introduction transistors all exhibit an increase in rDS(ON) with temperature.

Usually this is given in the form of a curve of rDS(ON) vs tem-
Many of the more recent applications of PowerMOS transis- perature on the datasheet. The worst case rDS(ON) at any ele-
Title tors, particularly low voltage devices, have been as solenoid vated junction temperature is determined as follows. First,
N75 drivers. In this type of application the device is simply used using the rDS(ON) vs temperature curve for the device, obtain
as a switch to turn the current through a solenoid, relay or the multiplicative factor at the expected operating junction
) other inductive load on and off (Figure 1). Since the dissipa- temperature. Finally multiply the maximum 25oC rDS(ON) rat-
ub- tion is low, a very small or no heat sink will be required. This ing by the previously determined factor.
ct note will cover the application of the rating and characteris-
The third state we should consider is when the switch transi-
tics of PowerMOS transistors to that type of application and
racti- tions from “on” to “off” or vice versa. In many solenoid switch
illustrate the process of selecting a suitable transistor.
l applications the major dissipation occurs while the Power-
MOS transistor is “on”, but turn on and turn off also dissipate
pect Defining the Problem
power in the transistor. The switching speed of most Power-
of The circuit used in most solenoid switch applications is very MOS transistors is so fast that turn on losses are usually
ing simple. It simply consists of an inductor and resistance in very small. An exception is when the drive current available
wer- series with the drain and a gate drive circuit (Figure 2). Ana- is very very small. Usually this does not occur in the real
lyzing this circuit can lead to some simplifications that will world. For example the Fairchild RFP70N06 PowerMOS
OS transistor requires a maximum of 115nC of gate charge to
speed design efforts.
an transition from “off” to fully “on”. For a gate drive which sup-
There are three circuit states that we should analyze. The
tors simplest state is when the PowerMOS transistor is “off”,
plies 1.0mA this would mean that the transition would take
less than 115µs. This will make a negligible change in the
when the gate and source are at the same potential. Under
junction temperature of the PowerMOS transistor.
ive this condition the dissipation in the device is simply the leak-
age current times the supply voltage VCC. Usually this is Turn-off subjects the PowerMOS transistor to Unclamped
duc- negligible. The second state we should consider is when the Inductive Switching. Modern PowerMOS transistors can
e gate drive is “on”. The PowerMOS transistor can best be rep- withstand this type of stress and give clear ratings in their
ads) resented as a series resistor. The current through that resis- datasheets to let customers calculate whether or not they
utho tor is: are operating within the devices’ capability. The energy dissi-
V CC pated in the PowerMOS transistor each time the current is
) I T = ---------------------------------
- interrupted is:
R L + r DS(ON) (EQ. 1.1)
ey-
ords  L × I T × V DSS
The dissipation (PT) in the PowerMOS transistor while the E T =  ------------------------------------ × 1 – K × In  1 + ---
1-
(EQ. 1.4)
 RL   K
nter- device is “on” is:
2
P T = ( I T ) × r DS(ON) (EQ. 1.2) See Fairchild Application Note AN-7514.
orpo-
Where:
ion, If we make the simplifying assumption that RL >> rDS(ON)
mi- this is: V BRK – V CC
K = ---------------------------------
-
n-  V CC 2 IT × RL
P T =  ------------ × r DS(ON) (EQ. 1.3)
ctor  RL 
Please note that the VBRK used here is the rated breakdown
where rDS(ON) is the worst case resistance of the PowerMOS voltage, since that is worst case, rather than the 1.3 x rated
re- transistor at its operating junction temperature. PowerMOS breakdown voltage used in Application Note AN-7514.
or ()
OC L L RL

FO
f-
ark + +
VDD VDD
VGS RG VGS RG
- -

0V 0V

FIGURE 1. TYPICAL INDUCTIVE SWITCHING CIRCUIT FIGURE 2. SOLENOID SWITCHING APPLICATION CIRCUIT

©2002 Fairchild Semiconductor Corporation Application Note 7517 Rev. A2

 Application Note 7517

The power dissipated in the device due to UIS will be directly

proportional to the number of times the interruption could IT × RL
 
t AV =  ------- × In  ------------------------------------------------ + 1
occur per second. If a human provides the interruptions, 5 L
(EQ. 1.5)
R   ×
times per second would probably be sufficient. L 1.3 V BRK – V CC

All of the losses in the PowerMOS transistor summed, multi-

4×4
t AV =  ----------- × In  ------------------------------------- + 1
plied by the total thermal resistance (junction to case, case 0.05
 4   1.3 × 100 – 16
to heat sink and heatsink to ambient) gives the rise in junc-
tion temperature above the ambient. From that temperature
t AV = 1.64ms
the operating rDS(ON) can be determined and the calcula-
tions iterated. Sometimes several iterations are required. Capability at 4.0A, 175oC is 0.9ms.

Example 1 (Unit is not suitable for this application!)

The following example assumes a set of operating condi- C. Try RFP45N06

tions and computes the suitability of various Fairchild Power-
MOS devices to operate under those assumed conditions. Assume TJ = 175oC.

The assumed circuit conditions are: Check to be sure UIS stress is within RFP45N06
capability.
L = 50mH, VCC = 16V, RL = 4Ω, IERC PSD1-2U Heat sink.
 IT × RL 
t AV =  ------- × In  ------------------------------------------------ + 1
L (EQ. 1.5)
In addition, the following operational conditions are R  ×
L  1.3 V BRK – V CC
assumed:
Rep Rate = 5 pulses/s, TA = 125oC, charged current 4×4
t AV =  ----------- × In  ---------------------------------- + 1
0.05
level ≈ 4A. Sufficient time was allotted for the inductor to 4 1.3 × 60 – 16
charge; we chose ten time constants (125ms). The inductor
also had to discharge to less than 1% of the charged current t AV = 2.9ms
level between pulses, and finally; 10ms of deadtime were
allotted between pulses. Capability at 4.0A, 175oC is 3.2ms. OK for UIS.
Please note: the number of significant figures in all interme- Check to see if TJ ≤ 175oC.
diate calculation values were truncated to aid readability.
r DS(ON) = 2.1 × 0.028 (See Figure 7, RFP45N06 datasheet.)
Check UIS capability and verify junction temperature is less
than 175oC. r DS(ON) = 0.059 Ω
A. Try RFP3055
Dissipation during conduction:
Assume TJ = 175oC.
2
 V CC
Check to be sure UIS stress is within RFP3055 capability. P T =  ------------ × r DS(ON) (EQ. 1.3)
 RL 
 IT × RL 
t AV =  ------- × In  ------------------------------------------------ + 1
L
(EQ. 1.5)
R   1.3 × V BRK – V CC 16.0 2
L P T =  ----------- × 0.059
 4 
(Reference AN-7514.)
P T = 0.941W
4×4
t AV =  ----------- × In  ---------------------------------- + 1
0.05
 4   1.3 × 60 – 16 Dissipation due to UIS:

 L × I T × V DSS
t AV = 2.9ms E T =  ------------------------------------ × 1 – K × In  1 + ---
1- (EQ. 1.4)
 RL   K
Capability at 4.0A, 175oC is 0.04ms.
(Unit is not suitable for this application!)

B. Try RFP22N10
Assume TJ = 175oC.
Check to be sure UIS stress is within RFP22N10 capability.

©2002 Fairchild Semiconductor Corporation Application Note 7517 Rev. A2

 Application Note 7517

Where Check to see if TJ ≤ 175oC.

V DSS – V CC r DS(ON) = 2.1 × 0.022 (See Figure 7, RFP50N06 datasheet.)
K = ---------------------------------
-
IT × RL

r DS(ON) = 0.046 Ω
60 – 16-
K = ------------------
4×4
Dissipation during conduction:
K = 2.75  V CC 2 (EQ. 1.3)
P T =  ------------ × r DS(ON)
 RL 
0.05 × 4 × 60
E T = ---------------------------------- × [ 1 – 2.75 × In ( 1.36 ) ]
4
16.0 2
P T =  ----------- × 0.046
E T = 0.441J 4

P T = 0.739W
Dissipation due to UIS = ET x Rep Rate: (EQ. 1.6)

P T = 0.441 × 5 = 2.206W
Dissipation due to UIS:

 L × I T × V DSS (EQ. 1.4)

E T =  ------------------------------------ × 1 – K × In  1 + ----
P TOTAL = 0.941 + 2.206 = 3.147W 1
 RL   K
θ JA = θ JC + θ CHS + θ HS (EQ. 1.7)
Where
o V DSS – V CC
θ JC = 1.14 C ⁄ W (See page 2, RFP45N06 datasheet).
K = ---------------------------------
-
IT × RL
o
θ CHS = 1.0 C ⁄ W (estimated)
60 – 16
K = -------------------
o 4×4
θ HS = 14.4 C ⁄ W (IERC short form catalog dated 8/93.)

K = 2.75
o
θ JA = 16.54 C ⁄ W
0.05 × 4 × 60
E T = ---------------------------------- × [ 1 – 2.75 × In ( 1.36 ) ]
∆ TJUNCTION = θ JA × P TOTAL (EQ. 1.8) 4

o E T = 0.441J
∆ TJUNCTION = 3.147 × 16.54 = 52.05 C

∆ TJUNCTION = 125 + 52.1 = 177.1 C

o Dissipation due to UIS = ET x Rep Rate: (EQ. 1.6)

(Unit is not suitable for this application!) P T = 0.441 × 5 = 2.206W

But we could use a lower thermal resistance heat sink and

P TOTAL = 0.739 + 2.206 = 2.945W
make it work.
θ JA = θ JC + θ CHS + θ HS (EQ. 1.7)
C. Try RFP50N06
Assume TJ = 175oC. o
θ JC = 1.14 C ⁄ W (See page 2, RFP50N06 datasheet.)
Check to be sure UIS stress is within RFP50N06
capability. o
θ CHS = 1.0 C ⁄ W (estimated)
 IT × RL 
t AV =  ------- × In  ------------------------------------------------ + 1
L (EQ. 1.5) o
R   × θ HS = 14.4 C ⁄ W (IERC short form catalog dated 8/93.)
L 1.3 V BRK – V CC
o
θ JA = 16.54 C ⁄ W
4×4
t AV =  ----------- × In  ---------------------------------- + 1
0.05
 4   1.3 × 60 – 16
∆ TJUNCTION = θ JA × P TOTAL (EQ. 1.8)
t AV = 2.9ms
o
∆ TJUNCTION = 2.945 × 16.54 = 48.7 C
Capability at 4.0A, 175oC is 3.2ms. OK for UIS.
o
∆ TJUNCTION = 125 + 48.7 = 173.7 C

OK for both UIS and TJ .

©2002 Fairchild Semiconductor Corporation Application Note 7517 Rev. A2

 Application Note 7517

D. Try RFP70N03
P T = 0.500 × 5 = 2.500W
Assume TJ = 175oC.
Check to be sure UIS stress is within RFP70N03 P TOTAL = 0.256 + 2.500 = 2.756W
capability.
IT × RL θ JA = θ JC + θ CHS + θ HS (EQ. 1.7)
 
t AV =  ------- × In  ------------------------------------------------ + 1
L (EQ. 1.5)
R   ×
L 1.3 V BRK – V CC o
θ JC = 1.0 C ⁄ W (See page 2, RFP70N03 datasheet.)
4×4
t AV =  ----------- × In  ---------------------------------- + 1
0.05
 4   1.3 × 30 – 16 o
θ CHS = 1.0 C ⁄ W (estimated)

t AV = 6.6ms o
θ HS = 14.4 C ⁄ W (IERC short form catalog dated 8/93.)

Capability at 4.0A, 175oC is 24ms. OK for UIS. o

θ JA = 16.4 C ⁄ W
Check to see if TJ ≤ 175oC.
∆ TJUNCTION = θ JA × P TOTAL (EQ. 1.8)
r DS(ON) = 1.6 × 0.010 (See Figure 7, RFP70N03 datasheet.)
o
∆ TJUNCTION = 2.756 × 16.4 = 45.2 C
r DS(ON) = 0.016 Ω
o
∆ TJUNCTION = 125 + 45.2 = 170.2 C
Dissipation during conduction:
OK for both UIS and TJ .
 V CC 2 (EQ. 1.3)
P T =  ------------ × r DS(ON)
 RL  E. Try RFP70N06

2 Assume TJ = 175oC.
P T =  ----------- × 0.016
16.0
 4  Check to be sure UIS stress is within RFP70N06
capability.
P T = 0.256W
 IT × RL 
t AV =  ------- × In  ------------------------------------------------ + 1
L (EQ. 1.5)
R   ×
Dissipation due to UIS: L 1.3 V BRK – V CC

 L × I T × V DSS
E T =  ------------------------------------ × 1 – K × In  1 + ---
1- (EQ. 1.4) 4×4
t AV =  ----------- × In  ---------------------------------- + 1
0.05
 RL   K  4   1.3 × 60 – 16

Where t AV = 2.9ms
V DSS – V CC
K = ---------------------------------
- Capability at 4.0A, 175oC is 9.0ms. OK for UIS.
IT × RL
Check to see if TJ ≤ 175oC.
30 – 16-
K = ------------------
4×4 r DS(ON) = 2.1 × 0.014 (See Figure 7, RFP70N06 datasheet.)

K = 0.875
r DS(ON) = 0.0294 Ω

0.05 × 4 × 30
E T = ---------------------------------- × [ 1 – 0.875 × In ( 2.143 ) ]
4 Dissipation during conduction:

E T = 0.500J  V CC 2 (EQ. 1.3)

P T =  ------------ × r DS(ON)
 RL 
Dissipation due to UIS = ET x Rep Rate: (EQ. 1.6)
2
P T =  ----------- × 0.0294
16.0
 4 

P T = 0.470W

©2002 Fairchild Semiconductor Corporation Application Note 7517 Rev. A2

 Application Note 7517

Dissipation due to UIS: The assumed conditions are:

 L × I T × V DSS L = 10mH, VCC = 24V, RL = 24Ω, rep rate = 5/s, No Heat

E T =  ------------------------------------ × 1 – K × In  1 + ----
1 (EQ. 1.4)
 sink, ambient = +125oC, I ≈ 1A, Check UIS capability and
 RL  K
verify junction temperature is less than +175oC.
Where
A. Try RFD3055
V DSS – V CC
K = ---------------------------------
IT × RL
- Assume TJ = 175oC.
Check to be sure UIS stress is within RFP3055
60 – 16-
K = ------------------ capability.
4×4
 IT × RL 
t AV =  ------- × In  ------------------------------------------------ + 1
L (EQ. 1.5)
R   ×
K = 2.75 L 1.3 V BRK – V CC

0.05 × 4 × 60 1 × 24
t AV =  ----------- × In  ---------------------------------- + 1
0.01
E T = ---------------------------------- × [ 1 – 2.75 × In ( 1.36 ) ]  24   1.3 × 60 – 24
4

E T = 0.441J t AV = 0.172ms

Dissipation due to UIS = ET x Rep Rate: (EQ. 1.6) Capability at 1.0A, +175oC is 0.6ms.
Unit is OK for UIS.
P T = 0.441 × 5 = 2.206W
Check to see if TJ ≤ +175oC.
P TOTAL = 0.470 + 2.206 = 2.676W r DS(ON) = 2.1 × 0.150 (See Figure 7, RFD3055 datasheet.)

(EQ. 1.7) r DS(ON) = 0.315 Ω

θ JA = θ JC + θ CHS + θ HS

o
Dissipation during conduction:
θ JC = 1.14 C ⁄ W (See page 2, RFP50N06 datasheet.)
 V CC 2
P T =  ------------ × r DS(ON) (EQ. 1.3)
o
θ CHS = 1.0 C ⁄ W (estimated)  RL 

o 24.0 2
θ HS = 14.4 C ⁄ W (IERC short form catalog dated 8/93.) P T =  ----------- × 0.315
 24 
o
θ JA = 16.54 C ⁄ W P T = 0.315W

Dissipation due to UIS:

∆ TJUNCTION = θ JA × P TOTAL (EQ. 1.8)

 L × I T × V DSS
E T =  ------------------------------------ × 1 – K × In  1 + ---
1-
o (EQ. 1.4)
∆ TJUNCTION = 2.676 × 16.54 = 44.3 C  RL   K

o Where
∆ TJUNCTION = 125 + 44.3 = 169.3 C
V DSS – V CC
OK for both UIS and TJ . K = ---------------------------------
-
IT × RL

Conclusion 60 – 24
K = ------------------
-
This leaves us with the result that the smallest device that 1 × 24
will safely handle a 4A switch application under these ground
K = 1.5
rules is a 50A rated device.
0.01 × 1 × 60
E T = ---------------------------------- × [ 1 – 1.5 × In ( 1.667 ) ]
Example 2 24

The following example assumes a set of operating condi- E T = 5.84mJ

tions and computes the suitability of various Fairchild Power-
MOS devices to operate under those assumed conditions.

©2002 Fairchild Semiconductor Corporation Application Note 7517 Rev. A2

 Application Note 7517

Dissipation due to UIS = ET x Rep Rate: (EQ. 1.6) on resistance and thermal resistance to conduction dissipa-
tion and operating temperature.
P T = 0.00584 × 5 = 0.029W
The supply voltage, load resistance and junction and
P TOTAL = 0.315 + 0.029 = 0.344W ambient temperatures are defined and therefore constant.
The on resistance multiplied by the thermal resistance must
be less than or equal to this constant. The equation to
θ JA = θ JC + θ CA (EQ. 1.7)
calculate the dissipation (PT) in the PowerMOS transistor
o while the device is “on” assuming that RL >> rDS(ON) was
θ JC = 2.8 C ⁄ W (See page 2, RFD3055 datasheet.) given on Page 1 as:
2
o  V CC
θ CA = 100 C ⁄ W (See page 2, RFD3055 datasheet.) P T =  ------------ × r DS(ON) (EQ. 1.3)
 RL 

θ JA = 102.8 C ⁄ W
o Substituting terms in the equation:

TJ – TA  V CC 2
∆ TJUNCTION = θ JA × P TOTAL (EQ. 1.8) ------------------- =  ------------ × r DS(ON) (EQ. 2.1)
R θ JA  RL 

o
∆ TJUNCTION = 102.8 × 0.344 = 35.4 C Where

TJ – TA
o P T = ------------------- (EQ. 2.2)
∆ TJUNCTION = 125 + 35.4 = 160.4 C R θ JA

OK for both UIS and Tj . and rearranging as follows:

2
 RL 
Conclusion r DS(ON) × R θ JA ≤  ------------ × T J – T A (EQ. 2.3)
 V CC
It is not necessary to use a larger device to switch this cur-
rent. provides the equation for device selection.

Example 3 A. Try the RFP3055

Example 1 concludes we need a device with an on resis-  RL  2 (EQ. 2.3)

r DS(ON) × R θ JA ≤  ------------ × T J – T A
tance of less than 50mΩ and a 30A continuous current rating  V CC
at +125oC case temperature. This seems to be a bit of over-
kill, since the application has a peak current of 4A. The pos-
4Ω 2
0.315 Ω × 18.2 C ⁄ W ≤  ----------- × 175 C – 125 C
o o o
sibility of a more cost-effective alternative should be  16V
investigated. A circuit configuration using a smaller MOSFET
and a commutating diode will be examined to determine if
o o
that is a better solution. 5.733 Ω C ⁄ W > 3.125 Ω C ⁄ W

The assumed circuit conditions are:

The on resistance thermal resistance product is greater than
L = 50mH, VCC = 16V, RL = 4Ω, IERC PSD1-2U Heat sink. the constant. (This unit is not suitable!)
In addition, the following operational conditions are
B. Try the RFD16N05
assumed:
Rep Rate = 5pulses/s, ambient temperature = +125oC,  RL  2
r DS(ON) × R θ JA ≤  ------------ × T J – T A (EQ. 2.3)
charged current level ≈ 4A. Sufficient time was allotted for  V CC
the inductor to charge; we chose ten time constants
(125ms). The inductor also had to discharge to less than 1% 4Ω 2
0.999 Ω × 17.5 C ⁄ W ≤  ----------- × 175 C – 125 C
o o o
of the charged current level between pulses, and finally;  16V
10ms of deadtime were allotted between pulses.
The selection process can be divided into two parts; MOS- o o
1.733 Ω C ⁄ W < 3.125 Ω C ⁄ W
FET and diode, as each will perform different functions. The
MOSFET will function as a switch, the diode as a discharge This unit is capable of dissipating the conduction losses!
path for the inductor.
Since the MOSFET is only a switch in this configuration, we
need only be concerned with the conduction dissipation
when selecting the proper device. Equation 2.3 provides a
basis for determining the MOSFET using the relationship of

©2002 Fairchild Semiconductor Corporation Application Note 7517 Rev. A2

 Application Note 7517

With a suitable MOSFET selected a diode is next. discharge time could be no greater than:
The energy dissipated by the diode due to one UIS pulse is t ≤ Pulse Width (1 pulse) – ( Charge Time + 10ms )
calculated as follows:

E = I0 × V D ×  ---- × k
L t ≤ 200ms – ( 125ms + 10ms )
 R (EQ. 2.4)

Where t ≤ 65ms
I0 = the current level at the time the MOSFET was turned off
If parasitic inductances and resistances are negligible; a
VD = the voltage across the diode useful approximation of the discharge time can be calculated
as follows:
( In ( 1 ⁄ ( 1 + s ) ) )
k = 1 + ----------------------------------------
s L
t = ------- × In ( 1 + s )
RL
I0 × R
s = --------------
-
VD

0.05mH
t = --------------------- × In ( 1 + 36.4 )
4Ω
E = 4A × 0.84V ×  ---------------- × 0.843
50mH
 4Ω 
t = 45.3ms
E = 35.4mJ
The discharge time is less than the allowable 65ms. This
The total power dissipation due to the 5 UIS pulses is calcu- approach will work. The inductor would discharge to less
lated; using the calculated value, determine a thermal resis- than 1% of the initial current level between each pulse.
tance necessary to dissipate the power. The thermal
resistance of the device, interface and heat sink must be less
than or equal to the calculated value. Conclusion
A properly selected MOSFET, capable of withstanding oper-
P T = E × 5 pulses/s (EQ. 1.5) ation in the avalanche mode was the best choice of the solu-
tions examined for this application. The MOSFET operating
P T = 177mW as a switch dissipates little power while “on” and provides a
means of discharging the inductor between pulses; making it
functionally compatible for the application. Finally and
T JMAX – T A equally important; the avalanche rated MOSFET is also the
R θ JA = -------------------------------
-
PT most economical choice of the solutions evaluated.
o o The selected MOSFET diode combination is also function-
175 C – 125 C
R θ JA = ----------------------------------------- ally compatible for this application. The combination selected
0.177W
in this example is more expensive than the stand alone
o MOSFET. However, the thermal resistance calculated for the
R θ JA ≤ 282 C ⁄ W
diode suggests a smaller less expensive diode could be sub-
C. Try the RURD410 stituted. The cost reduction from the substitution of a less
expensive diode may make the combination a more attrac-
R θ JA = R θ JC + R θ CHS + R θ HS (EQ. 1.7) tive solution. The examination of more economical diodes is
left to the reader.
o
R θ JA = 5.0 C ⁄ W + 1.0 C ⁄ W + 14.4 C ⁄ W
o o In this application; functionality, economics and a defined set
of operating conditions were the constraints to the eventual
solution. Rather than reach a rigid conclusion; the Applica-
o
R θ JA = 20.4 C ⁄ W tion note intended to illustrate a methodology to determine
the best solution for a set of design constraints.
The RURD410, interface and heat sink junction to ambient
thermal resistance are less than the requirement. This unit is
suitable.
The next consideration is to determine the time necessary
for the inductor to fully discharge. Earlier we established the
conditions for discharge. The current level must decay to 1%
of its initial value, the discharge time to the 1% current level
must be no greater than the pulse width of one pulse minus
the sum of the charge time and 10ms. In this illustration the

©2002 Fairchild Semiconductor Corporation Application Note 7517 Rev. A2

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EnSignaTM LittleFET™ QS™ SyncFET™
FACT™ MicroFET™ QT Optoelectronics™ TinyLogic™
FACT Quiet Series™ MicroPak™ Quiet Series™ TruTranslation™
STAR*POWER is used under license
DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER

NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. H5