Lovely School of Technology& Sciences

HOMEWORK NO: 2

ATM Networks

(CSE-884)

Submitted to:
Ms. Yash Pal
Submitted By:
Komal Chalotra
Reg No.: 5050070058
Roll No.: ROE115A54

B.Tech (HONS)-CSE
 PART-A:

Q1. Determine whether the new call (with PCR 55cells/s) is admitted or not if 25% of
Bandwidth (assuming total 550cells/s) is reserved for CBR Services. Already 4 CBR
connections (with PCRs 10,20,35,45 cells/s) are running and max allowed PCR is 60cells/s
and maximum number of CBR connections is 7.
Ans1. Total of PCR’s= 10+20+35+45=110
Adding 55 to 110= 165
Now 550 cells are reserved for CBR
Therefore, 550/4= 137.5
Now as the value of PCR is greater than CBR, so the connection will not be established and the
call will not be admitted.

Q2. List different constraints in designing of ATM switch? How they are handled?
Ans2. Most of the issues in switch design pertain to two important aspects:
1. Buffering: It relates to the placement of buffers in the switch.
2. Internal Routing: It relates to the design of switching fabric.
Both of them are not independent concepts, because fixing any one of them imposes constraints
on the other.
Moreover, there are two ways of designing a switch.
First is either one can choose a particular buffering technique and then decide from one of the
interconnection structure possible.
Second is one can first chose a particular interconnection structure and then decide upon the
buffering technique that suits it best.

Fundamental challenges in designing the switch are:

1. Tackling the problem of conflict: Conflict is the phenomenon occurring during the
switching process, whereby the switching process is hindered.
Conflicts are of two types:
1. External Conflict: The most common way to handle the external conflict is to
buffer the excess packet.
 2. Internal Conflict: It occurs when s5witch is incapable of forwarding arrived
packets when even external conflict has not occurred.
2. Blocking: Depending upon whether there are contentions/conflicts in the switching
process, a switch is classified as blocking and non blocking.
3. Buffering: Processing of storing excess packets, includes input buffering88, shared
buffering and output buffering.
4. Memory Look-up: Memory in switch is used for two purposes a) to store connection
related information, b) to buffer packets.
5. Multicasting: One to many transmission technique, in which instead of sending a copy
of data to each recipient, data is sent to a group of received using a multicast address.

Q3. Analyze the different parameters which act as the basis of GFC and ABR Flow Control
Mechanisms.
Ans3. Generic Flow Control:
Generic Flow Control is a link level flow control scheme to control the amount of data flowing
at the UNI. This mechanism is only applicable to data flowing in the forward direction, but not
in the backward direction.
In the UNI cell header part there are four bits of Generic Flow Control bits. The scope of the
ATM depends upon the configuration of the end system. An end system can be configured as
controlled system or uncontrolled system. GFC procedures are not applicable for uncontrolled
systems.
Connections from controlled equipment fall into two different categories:
1. Controlled Connections: This implies to a connection whose cell emission rate is
controlled by the GFC signal. No resource is reserved in advance for controlled
connections.
2. Uncontrolled Connections: This implies to connections whose cell emission rate is not
controlled by GFC signals. In this resource is reserved in advance for uncontrolled
connections.
The GFC procedure assumes a master slave relationship between the network and the user.
Therefore the network element is referred to as controlling equipment and the end system is
referred to as the controlled system.
There are basically three important GFC signals:
1. Halt: This signal is used to stop transmission of assigned ATM layer cells for both
controlled and uncontrolled ATM connections. It signals to limit the amount of cells
generated by n ATM end system at a UNI.
2. SET: The controlling devices issues SET signal to set the credit counter o a specified
integer value.
3. Null: The controlling device may at times send NULL signal, indicating that no action
has to be taken.

ABR Flow Control:

The source controls its data injection rates according to the loading conditions of the network for
ABR traffic. The current load of the network is conveyed to the source by through resource
management (RM) cells.
ABR ensures an efficient means to access the bandwidth available in the network. A flow control
feedback loop is used to achieve it.

Two Flow control approaches are used:

1. Credit Based Flow Control: Credit based flow control is a hop-by-hop feedback
mechanism. In this mechanism, source periodically receives credit from the next hop,
using which it further sends the data. Amount of data that a source can send is specified
by the credit. On receiving credits source can send data at any rate, provided it has
sufficient credits to do so. If the credit count reaches zero, the sender is prohibited to send
further data.
2. Rate Based Flow Control: It was proposed for an end to end feedback mechanism.
There is one feedback loop from source to destination. The destination sends back control
information to the sender. Moreover, any intermediate node can also change the control
information and forward it towards the source.

PART-B:

Q4. Discuss the various Issues of VPI/VCI Functions in an ATM Switch.

Ans4. The control plane in the ATM reference model is responsible for the establishment,
monitoring, and release of switched virtual circuit. All these control plane functions are
performed by exchanging signaling messages. As far as signaling is concerned, an ATM
switches forwards all the signaling cells received over the reserved VPI/VCI pair (0,5) to the
CAC module. The CAC module processes every connection request, and depending upon the
availability of resources, determines whether new connections can be accepted or not.

ATM needs some method to identify the intended destination for each unit of information (cell)
that gets sent. Unlike most other topologies, ATM actually uses two types of addresses to
accomplish this task: Virtual Path Indicator/Virtual Channel Indicator (VPI/VCI) addresses and
Network Services Access Point (NSAP) addresses.

VPI/VCI Addresses

VPI/VCI, the first type of address used by ATM, is placed in the 5-byte header of every cell.
This address actually consists of two parts: the Virtual Path Indicator (VPI) and the Virtual
Channel Indicator (VCI). They are typically written with a slash separating the VPI and the VCI
values—for example, 0/100, together these two values are used by an ATM edge device (such as
a router) to indicate to ATM switches which virtual circuit a cell should follow.

An ATM-Based Network Using Virtual Circuits

The following diagram adds the VPI/VCI detail to the network.

VPI/VCI Usage in an ATM Network

The NY router uses a single physical link connected to Port 0 on the NY ATM switch carrying
both virtual circuits. It simply makes decisions based on VPI/VCI values placed in ATM cell
headers by the router. If the NY router (the ATM edge device) places the VPI/VCI value 0/50 in
the cell header, the ATM switch uses a preprogrammed table indicating that the cell should be
forwarded out Port 2, sending it to LA. table needs to instruct the switch to convert the VPI/VCI
value to 0/51 as the cells leave the Port 1 interface (only the VCI is changed). The ATM switch
in LA has a similar table indicating that the cell should be switched out Port 1 with a VPI/VCI
value of 0/52. However, if the NY router originates a cell with the VPI/VCI value 0/65, the NY
ATM switch forwards the cell to DC.

Q5. Show that the Prelude Switch Provides High-throughput and flexible Switching
capability for Integrated Broadband Networks.
Ans5. Prelude switch was designed by CNET in France. The aim was to provide high throughput
to support high bandwidth applications like video and flexible switching capability for integrated
broadband networks to provide a multi-service environment that is capable of supporting
different applications including video, voice and data.
There are four distinct stages in prelude switch
In the first stage the packets are converted from serial to parallel form. The state delivers a cell
stream byte by byte without any phase relationship from one output to another.
Second stage is the clock adaptation and phase alignment stage. This stage time-shifts the
packets by one byte from one link to next, which results in a diagonal alignment.
Third is the super multiplexing stage. The diagonally aligned packets are then fed into the
super multiplexing stage. It is a rotative space division switch that assumes cyclically N different
switching patterns. Multiplexing of the payload is not done arbitrarily. The second output line
always carries octet 1 of each payload. Similarly, the third output line carries octet 2 of each
payload. This is the reason that the number of lines is equal to the number of payload.
Fourth stage is the central memory in which the new header along with the payload octet, is
stored in the shared memory. At each byte time, the controller delivers the address of a packet,
which to be extracted from other memory banks.

Q6. Elaborate the Concept of Statistical Multiplexing used in ATM Networks by taking
some examples.
Ans6. Not to be done

Q7. What is the concept Leaky bucket algorithm for Traffic Shaping? How it decides the
conformance of an ATM Cell?

Ans7. The continuous state leaky bucket algorithm can be considered as a bucket with a
capacity of (I+L), where each cell pours in I data units of fluid into the bucket, and the bucket is
leaking at a rate of 1 data-unit/time-unit.

The capacity of the leaky bucket at any instant of time is maintained by variable X.

A cell is declared confirming if, at the time of its arrival, the fluid in the bucket is less than or
equal to L. Otherwise the cell is declared nonconforming.

LCT = The last conformance time which stores the last time a conforming cell was accepted.

On the arrival of a cell, the amount of fluid drained since last LCT is subtracted from the bucket
capacity
It is represented as X* = X-( ta(k)-LCT)

Where, (ta(k)-LCT) gives the amount of liquid drained since the last conforming cell arrived.

So, X* gives the capacity of the leaky bucket at time ta(k).

Conformance of an ATM cell:

Once the capacity of leaky bucket is determined, the conformity of the cell depends upon
whether there are I data units available in the bucket.

It depends upon two conditions:

1. If the amount of fluid id less than L, the cell is declared conforming and LCT is set to the
new arrival time and the amount of the fluid is increased by I.

2. Else, the cell is declared nonconforming, and the value of the variables X and LCT are
left unchanged.