Truth table of 2lint

to 4 line decoder

sr Binary Input Decoding OUTPUT

A A' function
D0 D1 D2 D3
0 0 0 A'A'00 1 0 0 0

1 0 1 A'A 01 0 1 0 0

2 1 0 A A'10 0 0 1 1

3 1 1 A A 11 0 0 0 1

LOGIC DIAGRAM WIHT

ACTIVE HIGH

PIN DIAGRAM WITH

logic symble AND GATE
INPUT OUTPUT
1 PIN DIAGRAM
G1 3
2
1 14
4
G2 6
5 2 13
2I
1I

13 I
12 I
G1
3 G4 12
O3

8
G3 10 O 11
9 4 11
5I
4I

12 G4 5 G2 10
11
10 I
O6

13
9I

6 G3 9
7 GND
O8

7 8
14 VCC

7 GND
14 VCC
LOGIC DIAGRAM

0V 5V

A A0

10 I 0,0
O8
9I

12 I 0,1
O 11
13 I

4I
1,0
O6
5I

1I
1,1
O3
2I

A A' A A'
 2LINE TO 4LINE DECODER WITH CMOS CONFIGRATION

Truth table of 2lint

to 4 line decoder

sr Decoding OUTPUT
Binary Input
A A' function D0 D1 D2 D3
0 A'A'00 1 0 0 0
0 0
1 A'A 01 0 1 0 0
0 1
2 A A'10 0 0 1 1
1 0
3 A A 11 0 0 0 1
1 1

LOGIC DIAGRAM WIHT

ACTIVE HIGH

logic symble
INPUT OUTPUT
1
G1 3
2

4
G2 6
5

8
G3 10
9
12 G4
13 11

7 GND
14 VCC
PIN DIAGRAM WITH AND GATE

PIN DIAGRAM

1 14

2 13
2I
1I

13
12

G1
I
I

3 G4 12
O3

O
11

4 11
6I
5I

G2
5 10
O4

9I
8I

6 G3 9
O
10

7 8

7 GND
14 VCC

LOGIC DIAGRAM cmos configration

 0V 5V

A A0

10 I 0,0
O8
9I

12 I 0,1
O 11
13 I

4I
1,0
O6
5I

1I
1,1
O3
2I

A A' A A'
 0V 5V

A A0

10 I 0,0
O8
9I

12 I 0,1
O 11
13 I

4I
1,0
O6
5I

1I
1,1
O3
2I

A A' A A'
2 LINE TO 4 LINE DECODER WITH ACTIVE LOW CONFIGRATION

Truth table of 2lint

to 4 line decoder

sr Binary Input Decoding OUTPUT

A A' function D0 D1 D2 D3
0 0 0 A'A'00 0 1 1 1

1 0 1 A'A 01 1 0 1 1

2 1 0 A A'10 1 1 0 1

3 1 1 A A 11 1 1 1 0

logic symble
INPUT OUTPUT
1
G1 12
2
13
3 G2
4 6
5
9
G3 8
10
11
7 GND
14 VCC

1
G4 12
2
13
3
4 6
5
9
8
10
11 7 GND
14 VCC
 LOGIC DIAGRAM WITH TTL
5V 5V

A A0

1I 0,0
2I O 12
13 I

9I
10 I O 8 0,1
11 I

3I 1,0
4I O 6
5I

1,1
1I
2I O 12
13 I

A A' A A'

PIN DIAGRAM
14
1 1I
1 0I

1
9I

G1
2 13
O 8

3 12
5I
4I
3I

4 G2 11
O 6 1 3I

5 10
2
1I

6
I

G3 9
7 GND
O 12

7 8 14 VCC

1 14
1 3I
2I
1I

2 G4 13
O 1 2 4I

3 12
5I
3I

4 11
O 6 11 01I

5 10
9I

6 9
I
O 8

7 8

7 GND
14 VCC
 Truth table of 2lint
to 4 line decoder

sr Binary Input Decoding OUTPUT

A A' function D0 D1 D2 D3
0 0 0 A'A'00 0 1 1 1

1 0 1 A'A 01 1 0 1 1

2 1 0 A A'10 1 1 0 1

3 1 1 A A 11 1 1 1 0

logic symble
INPUT OUTPUT
1
G1 12
2
13
3 G2
4 6
5
9
G3 8
10
11
7 GND
14 VCC

1
G4 12
2
13
3
4 6
5
9
10 8
11 7 GND
14 VCC
 LOGIC DIAGRAM WITH TTL
5V 5V

A A0

1I 0,0
2I O 12
13 I

9I
10 I O 8 0,1
11 I

3I 1,0
4I O 6
5I

1,1
1I
2I O 12
13 I

A A' A A'

LOGIC DIAGRAM WIHT ACTIVE

low
 PIN DIAGRAM WITH
AND GATE

PIN DIAGRAM

1 14
G1
2 13

3 12

4 G2 11
5 10
6 G3 9
7 GND
7 8 14 VCC

1 14

2 G4 13

3 12

4 11
5 10
6 9

7 8

7 GND
14 VCC