Intro To UNIX Software Development - Mak... http://www.cs.bu.edu/teaching/c/makefile...

Makefiles

What is make?
Make is a utility to track dependencies in a system of files, and to
automate compilations
Examples of dependencies - C program
Objs depend on source for that object
Objs depend on headers
Binary depends on objs
Libs depend on objs
Uses files called Makefiles as configuration
Hierarchical dependencies determined by mod time - if any
dependency is newer than target, remake target with command
Many things described here are specific to GNU make (gmake in the gnu
locker on Athena).

Makefiles - basic
naming - GNUmakefile, makefile, Makefile in that order
"Makefile" is recommended - fairly standard, appears at top of dir
use GNUmakefile only for gmake-specific makefiles.
explicit rules (basic)
TARGET... : DEPENDENCIES... [; COMMAND]
COMMAND
...
...

Command lines MUST start with tabs

\newline syntax for breaking up lines
Phony targets i.e. clean, all
No dependencies
Executed every time target is goal
(gmake specific) declare as phony to avoid name conflicts with
special target keyword .PHONY:
.PHONY : clean
clean :
rm $(OBJS)

Default goal is first rule that does not start with a period
Comments - `#' starts

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Commands
Each line is run in a different shell, if you want to cause a command to
affect the next, use ; in the command so that make interprets it as a
single command:
foo:
cd foodir ; doit

or
foo:
cd foodir ; \
doit

To ignore errors from a command, prefix command with "-"

foo:
-rm -f *~ *.o

Variables
Naming
Case sensitive
Any characters except trailing whitespace, `:', `#', or `='
Should avoid all but alphanumerics and underscore
Setting
VARNAME = VARVALUE (note: trailing spaces not truncated)
make VARNAME=value
inherits most environment variables except $SHELL and a few
others
Referencing: $(VARNAME)
Standard variables for program Makefiles
$(OBJS)
$(SHELL)
$(MAKE)
$(CC)
$(CFLAGS)
$(INCLUDE)
$(LDFLAGS)
Automatic variables - make sets these in special cases for substitutions
and other purposes. More later

Multiple targets and rules

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Multiple targets equivalent to list of rules for each target

foo bar baz: blah
doit

and

foo: blah
doit
bar: blah
doit
baz: blah
doit

are equivalent
Multiple rules for a single target are acceptable - make will check all
files that depend on a given updated file. Useful for adding
dependencies.
FILES = foo bar baz
foo: bar
doit
bar baz: blah
dothat
$(FILES): gag
# no commands allowed here

will add dependency on gag to $(FILES) (ie, if gag changes, files will
get rebuild)
Multiple commands are NOT acceptable - there can be only one set of
commands for a given target; all other rules using the target must not
have commands.
exception - double-colon rules' commands are independent.

Implicit rules
Default rules, either internal to make or user-defined, which set
dependencies based on classes of filename.
Pattern rules
TARGET-PATTERN: DEP-PATTERN
COMMANDS

eg

%.o: %.c
$(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@

Can be chained, i.e. .y -> .c -> .o -> the .c file does not exist, but make
considers it for dependency purposes. Make deletes the temp files
when it's done.

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A number of useful implicit rules are predefined e.g. .c -> .o as above.

Static pattern rules

Used to take analagous dependencies and execute commands
constructed from names
TARGETS ...: TARGET-PATTERN: DEP-PATTERNS ...
COMMANDS
...

Example:
OBJS = foo.o bar.o
$(OBJS): %.o: %.c
$(CC) -c $(CFLAGS) $< -o $@

TARGET-PATTERN is used to construct names to place into

DEP-PATTERNS
Special Variables
`%' - is the variable which matches the stem of the targets, which
is then substituted into the `%' in the dependency pattern to make
the actual command.
`$<' is the automatic variable which holds the name of the
dependency.
`$@' is the automatic variable which holds the name of the target.
`$*' is an automatic variable which will expand to the stem (what
matched the %)
Different from implicit rules in that it only applies to the list of targets
you specify.

Including other Makefiles

directive: include FILENAMES
FILENAMES can include shell globs and make vars
useful for including global rules and vars

makedepend
Parses .c files for other files they include, then writes them in the form
of a dependency rule in a makefile.

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For example, if foo.c #includes foo.h, bar.h, and quux.c, it will add a
rule of the form:
foo.c: foo.h bar.h quux.c

to the makefile
old way to use:

dep:
makedepend $(CPPFLAGS) *.c

will remake all dependencies when make dep is called, and write them
to the end of the current makefile
gmake way to use (as suggested by Mike Whitson):
include *.d
%.d: %.c
$(SHELL) -ec '$(CC) -M \
$(CPPFLAGS) $< | \
sed '\''s/$*.o/& $@/g'\'' \
> $@'

(gmake considers all included makefiles as targets, and, if any needed

to be recreated, reruns itself with the updated makefiles.)

Recursion
Useful if you want to have subsections of code in subdirs with their own
makefiles
Basic syntax:
subsystem:
cd subdir; $(MAKE)

Always use $(MAKE) rather than passing `make' - inherits path to make
and command line arguments
Exporting variables to sub-makes normally only happens for variables
defined in the environment or the command line.
export VARIABLE
unexport VARIABLE

Archives (libraries)
A specific member of an archive can be target or dependency:
ARCHIVE(MEMBERS)

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eg
libfoo.a(foo.o bar.o): foo.o bar.o
ar -r libfoo.a foo.o bar.o

Other functionality
GNU gmake supports conditionals, loops, functions, and more
Look in info pages (M-x info in emacs) for more information

Other options
imake and xmkmf
autoconf and configure

Prepared by Erik Nygren (nygren@mit.edu) and Mike Whitson

(mwhitson@mit.edu)

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